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cell-binutils  2.17cvs20070401
Defines
ia64-opc-m.c File Reference
#include "ia64-opc.h"
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Defines

#define M0   IA64_TYPE_M, 0
#define M   IA64_TYPE_M, 1
#define M2   IA64_TYPE_M, 2
#define bM(x)   (((ia64_insn) ((x) & 0x1)) << 36)
#define bX(x)   (((ia64_insn) ((x) & 0x1)) << 27)
#define bX2(x)   (((ia64_insn) ((x) & 0x3)) << 31)
#define bX3(x)   (((ia64_insn) ((x) & 0x7)) << 33)
#define bX4(x)   (((ia64_insn) ((x) & 0xf)) << 27)
#define bX6a(x)   (((ia64_insn) ((x) & 0x3f)) << 30)
#define bX6b(x)   (((ia64_insn) ((x) & 0x3f)) << 27)
#define bX7(x)   (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() */
#define bY(x)   (((ia64_insn) ((x) & 0x1)) << 26)
#define bHint(x)   (((ia64_insn) ((x) & 0x3)) << 28)
#define mM   bM (-1)
#define mX   bX (-1)
#define mX2   bX2 (-1)
#define mX3   bX3 (-1)
#define mX4   bX4 (-1)
#define mX6a   bX6a (-1)
#define mX6b   bX6b (-1)
#define mX7   bX7 (-1)
#define mY   bY (-1)
#define mHint   bHint (-1)
#define OpX3(a, b)   (bOp (a) | bX3 (b)), (mOp | mX3)
#define OpX3X6b(a, b, c)
#define OpX3X6bX7(a, b, c, d)
#define OpX3X4(a, b, c)
#define OpX3X4X2(a, b, c, d)
#define OpX3X4X2Y(a, b, c, d, e)
#define OpX6aHint(a, b, c)
#define OpXX6aHint(a, b, c, d)
#define OpMXX6a(a, b, c, d)   (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a)
#define OpMXX6aHint(a, b, c, d, e)
#define EMPTY   0,0,NULL
#define LDINCREG(c, h)   M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL
#define CMPXCHG(c, h)   M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY
#define CMPXCHG_P(c, h)   M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL
#define CMPXCHG16(c, h)   M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY
#define CMPXCHG16_P(c, h)   M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL
#define CMPXCHG_acq   0
#define CMPXCHG_rel   4
#define CMPXCHG_1   0
#define CMPXCHG_2   1
#define CMPXCHG_4   2
#define CMPXCHG_8   3
#define CMPXCHGn(n, s)
#define CMP8XCHG16(s)
#define CMPXCHG_ALL(s)
#define LDINCIMMED(c, h)   M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC, 0, NULL
#define STINCIMMED(c, h)   M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC, 0, NULL
#define FLDINCREG(c, h)   M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC, 0, NULL
#define LD(a, b, c)   M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC, 0, NULL
#define LFETCHINCREG(c, h)   M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC, 0, NULL
#define FLDINCIMMED(c, h)   M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC, 0, NULL
#define FSTINCIMMED(c, h)   M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC, 0, NULL
#define LFETCHINCIMMED(c, h)   M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC, 0, NULL

Define Documentation

#define bHint (   x)    (((ia64_insn) ((x) & 0x3)) << 28)

Definition at line 38 of file ia64-opc-m.c.

#define bM (   x)    (((ia64_insn) ((x) & 0x1)) << 36)

Definition at line 29 of file ia64-opc-m.c.

#define bX (   x)    (((ia64_insn) ((x) & 0x1)) << 27)

Definition at line 30 of file ia64-opc-m.c.

#define bX2 (   x)    (((ia64_insn) ((x) & 0x3)) << 31)

Definition at line 31 of file ia64-opc-m.c.

#define bX3 (   x)    (((ia64_insn) ((x) & 0x7)) << 33)

Definition at line 32 of file ia64-opc-m.c.

#define bX4 (   x)    (((ia64_insn) ((x) & 0xf)) << 27)

Definition at line 33 of file ia64-opc-m.c.

#define bX6a (   x)    (((ia64_insn) ((x) & 0x3f)) << 30)

Definition at line 34 of file ia64-opc-m.c.

#define bX6b (   x)    (((ia64_insn) ((x) & 0x3f)) << 27)

Definition at line 35 of file ia64-opc-m.c.

#define bX7 (   x)    (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() */

Definition at line 36 of file ia64-opc-m.c.

#define bY (   x)    (((ia64_insn) ((x) & 0x1)) << 26)

Definition at line 37 of file ia64-opc-m.c.

#define CMP8XCHG16 (   s)
Value:
{"cmp8xchg16."#s,       CMPXCHG16   (0x20|CMPXCHG_##s, 0)}, \
    {"cmp8xchg16."#s,       CMPXCHG16_P (0x20|CMPXCHG_##s, 0)}, \
    {"cmp8xchg16."#s".nt1", CMPXCHG16   (0x20|CMPXCHG_##s, 1)}, \
    {"cmp8xchg16."#s".nt1", CMPXCHG16_P (0x20|CMPXCHG_##s, 1)}, \
    {"cmp8xchg16."#s".nta", CMPXCHG16   (0x20|CMPXCHG_##s, 3)}, \
    {"cmp8xchg16."#s".nta", CMPXCHG16_P (0x20|CMPXCHG_##s, 3)}
#define CMPXCHG (   c,
 
)    M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY
#define CMPXCHG16 (   c,
 
)    M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY
#define CMPXCHG16_P (   c,
 
)    M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL
#define CMPXCHG_1   0
#define CMPXCHG_2   1
#define CMPXCHG_4   2
#define CMPXCHG_8   3
#define CMPXCHG_acq   0
#define CMPXCHG_ALL (   s)
Value:
CMPXCHGn(1, s), \
                       CMPXCHGn(2, s), \
                       CMPXCHGn(4, s), \
                       CMPXCHGn(8, s), \
                       CMP8XCHG16(s)
#define CMPXCHG_P (   c,
 
)    M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2}, PSEUDO, 0, NULL
#define CMPXCHG_rel   4
#define CMPXCHGn (   n,
  s 
)
Value:
{"cmpxchg"#n"."#s,       CMPXCHG   (CMPXCHG_##n|CMPXCHG_##s, 0)}, \
    {"cmpxchg"#n"."#s,       CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 0)}, \
    {"cmpxchg"#n"."#s".nt1", CMPXCHG   (CMPXCHG_##n|CMPXCHG_##s, 1)}, \
    {"cmpxchg"#n"."#s".nt1", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 1)}, \
    {"cmpxchg"#n"."#s".nta", CMPXCHG   (CMPXCHG_##n|CMPXCHG_##s, 3)}, \
    {"cmpxchg"#n"."#s".nta", CMPXCHG_P (CMPXCHG_##n|CMPXCHG_##s, 3)}
#define EMPTY   0,0,NULL

Definition at line 74 of file ia64-opc-m.c.

#define FLDINCIMMED (   c,
 
)    M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC, 0, NULL
#define FLDINCREG (   c,
 
)    M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC, 0, NULL
#define FSTINCIMMED (   c,
 
)    M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC, 0, NULL
#define LD (   a,
  b,
  c 
)    M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC, 0, NULL
#define LDINCIMMED (   c,
 
)    M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC, 0, NULL
#define LDINCREG (   c,
 
)    M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL
#define LFETCHINCIMMED (   c,
 
)    M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC, 0, NULL
#define LFETCHINCREG (   c,
 
)    M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC, 0, NULL
#define M   IA64_TYPE_M, 1

Definition at line 25 of file ia64-opc-m.c.

#define M0   IA64_TYPE_M, 0

Definition at line 24 of file ia64-opc-m.c.

#define M2   IA64_TYPE_M, 2

Definition at line 26 of file ia64-opc-m.c.

#define mHint   bHint (-1)

Definition at line 49 of file ia64-opc-m.c.

#define mM   bM (-1)

Definition at line 40 of file ia64-opc-m.c.

#define mX   bX (-1)

Definition at line 41 of file ia64-opc-m.c.

#define mX2   bX2 (-1)

Definition at line 42 of file ia64-opc-m.c.

#define mX3   bX3 (-1)

Definition at line 43 of file ia64-opc-m.c.

#define mX4   bX4 (-1)

Definition at line 44 of file ia64-opc-m.c.

#define mX6a   bX6a (-1)

Definition at line 45 of file ia64-opc-m.c.

#define mX6b   bX6b (-1)

Definition at line 46 of file ia64-opc-m.c.

#define mX7   bX7 (-1)

Definition at line 47 of file ia64-opc-m.c.

#define mY   bY (-1)

Definition at line 48 of file ia64-opc-m.c.

#define OpMXX6a (   a,
  b,
  c,
  d 
)    (bOp (a) | bM (b) | bX (c) | bX6a (d)), (mOp | mM | mX | mX6a)

Definition at line 66 of file ia64-opc-m.c.

#define OpMXX6aHint (   a,
  b,
  c,
  d,
  e 
)
Value:
(bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \
       (mOp | mM | mX | mX6a | mHint)

Definition at line 68 of file ia64-opc-m.c.

#define OpX3 (   a,
  b 
)    (bOp (a) | bX3 (b)), (mOp | mX3)

Definition at line 51 of file ia64-opc-m.c.

#define OpX3X4 (   a,
  b,
  c 
)
Value:
(bOp (a) | bX3 (b) | bX4 (c)), \
                            (mOp | mX3 | mX4)

Definition at line 56 of file ia64-opc-m.c.

#define OpX3X4X2 (   a,
  b,
  c,
  d 
)
Value:
(bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \
                            (mOp | mX3 | mX4 | mX2)

Definition at line 58 of file ia64-opc-m.c.

#define OpX3X4X2Y (   a,
  b,
  c,
  d,
  e 
)
Value:
(bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | bY (e)), \
                            (mOp | mX3 | mX4 | mX2 | mY)

Definition at line 60 of file ia64-opc-m.c.

#define OpX3X6b (   a,
  b,
  c 
)
Value:
(bOp (a) | bX3 (b) | bX6b (c)), \
                            (mOp | mX3 | mX6b)

Definition at line 52 of file ia64-opc-m.c.

#define OpX3X6bX7 (   a,
  b,
  c,
  d 
)
Value:
(bOp (a) | bX3 (b) | bX6b (c) | bX7 (d)), \
                            (mOp | mX3 | mX6b | mX7)

Definition at line 54 of file ia64-opc-m.c.

#define OpX6aHint (   a,
  b,
  c 
)
Value:
(bOp (a) | bX6a (b) | bHint (c)), \
                            (mOp | mX6a | mHint)

Definition at line 62 of file ia64-opc-m.c.

#define OpXX6aHint (   a,
  b,
  c,
  d 
)
Value:
(bOp (a) | bX (b) | bX6a (c) | bHint (d)), \
                            (mOp | mX | mX6a | mHint)

Definition at line 64 of file ia64-opc-m.c.

#define STINCIMMED (   c,
 
)    M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC, 0, NULL