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cell-binutils  2.17cvs20070401
ia64-opc-i.c
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00001 /* ia64-opc-i.c -- IA-64 `I' opcode table.
00002    Copyright 1998, 1999, 2000, 2002, 2005, 2006
00003    Free Software Foundation, Inc.
00004    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
00005 
00006    This file is part of GDB, GAS, and the GNU binutils.
00007 
00008    GDB, GAS, and the GNU binutils are free software; you can redistribute
00009    them and/or modify them under the terms of the GNU General Public
00010    License as published by the Free Software Foundation; either version
00011    2, or (at your option) any later version.
00012 
00013    GDB, GAS, and the GNU binutils are distributed in the hope that they
00014    will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016    the GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with this file; see the file COPYING.  If not, write to the
00020    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00021    02110-1301, USA.  */
00022 
00023 #include "ia64-opc.h"
00024 
00025 #define I0    IA64_TYPE_I, 0
00026 #define I     IA64_TYPE_I, 1
00027 #define I2    IA64_TYPE_I, 2
00028 
00029 /* instruction bit fields: */
00030 #define bC(x)        (((ia64_insn) ((x) & 0x1)) << 12)
00031 #define bIh(x)              (((ia64_insn) ((x) & 0x1)) << 23)
00032 #define bTa(x)              (((ia64_insn) ((x) & 0x1)) << 33)
00033 #define bTag13(x)    (((ia64_insn) ((x) & 0x1)) << 33)
00034 #define bTb(x)              (((ia64_insn) ((x) & 0x1)) << 36)
00035 #define bVc(x)              (((ia64_insn) ((x) & 0x1)) << 20)
00036 #define bVe(x)              (((ia64_insn) ((x) & 0x1)) << 32)
00037 #define bWh(x)              (((ia64_insn) ((x) & 0x3)) << 20)
00038 #define bX(x)        (((ia64_insn) ((x) & 0x1)) << 33)
00039 #define bXb(x)              (((ia64_insn) ((x) & 0x1)) << 22)
00040 #define bXc(x)              (((ia64_insn) ((x) & 0x1)) << 19)
00041 #define bX2(x)              (((ia64_insn) ((x) & 0x3)) << 34)
00042 #define bX2a(x)             (((ia64_insn) ((x) & 0x3)) << 34)
00043 #define bX2b(x)             (((ia64_insn) ((x) & 0x3)) << 28)
00044 #define bX2c(x)             (((ia64_insn) ((x) & 0x3)) << 30)
00045 #define bX3(x)              (((ia64_insn) ((x) & 0x7)) << 33)
00046 #define bX6(x)              (((ia64_insn) ((x) & 0x3f)) << 27)
00047 #define bYa(x)              (((ia64_insn) ((x) & 0x1)) << 13)
00048 #define bYb(x)              (((ia64_insn) ((x) & 0x1)) << 26)
00049 #define bZa(x)              (((ia64_insn) ((x) & 0x1)) << 36)
00050 #define bZb(x)              (((ia64_insn) ((x) & 0x1)) << 33)
00051 
00052 /* instruction bit masks: */
00053 #define mC    bC (-1)
00054 #define mIh   bIh (-1)
00055 #define mTa   bTa (-1)
00056 #define mTag13       bTag13 (-1)
00057 #define mTb   bTb (-1)
00058 #define mVc   bVc (-1)
00059 #define mVe   bVe (-1)
00060 #define mWh   bWh (-1)
00061 #define mX    bX (-1)
00062 #define mXb   bXb (-1)
00063 #define mXc   bXc (-1)
00064 #define mX2   bX2 (-1)
00065 #define mX2a  bX2a (-1)
00066 #define mX2b  bX2b (-1)
00067 #define mX2c  bX2c (-1)
00068 #define mX3   bX3 (-1)
00069 #define mX6   bX6 (-1)
00070 #define mYa   bYa (-1)
00071 #define mYb   bYb (-1)
00072 #define mZa   bZa (-1)
00073 #define mZb   bZb (-1)
00074 
00075 #define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
00076        (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
00077        (mOp | mZa | mZb | mVe | mX2a | mX2b)
00078 #define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
00079   (bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
00080        (mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
00081 #define OpX2X(a,b,c)        (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
00082 #define OpX2XYa(a,b,c,d)    (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
00083                             (mOp | mX2 | mX | mYa)
00084 #define OpX2XYb(a,b,c,d)    (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
00085                             (mOp | mX2 | mX | mYb)
00086 #define OpX2TaTbYaC(a,b,c,d,e,f) \
00087        (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
00088        (mOp | mX2 | mTa | mTb | mYa | mC)
00089 #define OpX2TaTbYaXcC(a,b,c,d,e,f,g) \
00090        (bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bXc (f) | bC (g)), \
00091        (mOp | mX2 | mTa | mTb | mYa | mXc | mC)
00092 #define OpX3(a,b)           (bOp (a) | bX3 (b)), (mOp | mX3)
00093 #define OpX3X6(a,b,c)              (bOp (a) | bX3 (b) | bX6(c)), \
00094                             (mOp | mX3 | mX6)
00095 #define OpX3X6Yb(a,b,c,d)   (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \
00096                             (mOp | mX3 | mX6 | mYb)
00097 #define OpX3XbIhWh(a,b,c,d,e) \
00098   (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
00099   (mOp | mX3 | mXb | mIh | mWh)
00100 #define OpX3XbIhWhTag13(a,b,c,d,e,f) \
00101      (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
00102      (mOp | mX3 | mXb | mIh | mWh | mTag13)
00103 
00104 #define FULL17 ((ia64_insn)0x10ff001fc0LL)
00105 
00106 /* Used to initialise unused fields in ia64_opcode struct,
00107    in order to stop gcc from complaining.  */
00108 #define EMPTY 0,0,NULL
00109 
00110 struct ia64_opcode ia64_opcodes_i[] =
00111   {
00112     /* I-type instruction encodings (sorted according to major opcode).  */
00113 
00114     {"break.i",      I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL},
00115     {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL},
00116     {"hint.i",       I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL},
00117     {"chk.s.i",      I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY},
00118 
00119     {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL},
00120 #define MOV(a,b,c,d) \
00121     I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY
00122     {"mov.sptk",            MOV (7, 0, 0, 0)},
00123     {"mov.sptk.imp",        MOV (7, 0, 1, 0)},
00124     {"mov",                 MOV (7, 0, 0, 1)},
00125     {"mov.imp",                    MOV (7, 0, 1, 1)},
00126     {"mov.dptk",            MOV (7, 0, 0, 2)},
00127     {"mov.dptk.imp",        MOV (7, 0, 1, 2)},
00128     {"mov.ret.sptk",        MOV (7, 1, 0, 0)},
00129     {"mov.ret.sptk.imp",    MOV (7, 1, 1, 0)},
00130     {"mov.ret",                    MOV (7, 1, 0, 1)},
00131     {"mov.ret.imp",         MOV (7, 1, 1, 1)},
00132     {"mov.ret.dptk",        MOV (7, 1, 0, 2)},
00133     {"mov.ret.dptk.imp",    MOV (7, 1, 1, 2)},
00134 #undef MOV
00135     {"mov",   I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY},
00136     {"mov",   I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY},
00137     /* Don't remove one of the seemingly redundant FULL17-s.  */
00138     {"mov",   I, FULL17 | OpX3 (0, 3) | FULL17, {PR, R2}, PSEUDO, 0, NULL},
00139     {"mov",   I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY},
00140     {"mov",   I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY},
00141     {"mov",   I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY},
00142     {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY},
00143     {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY},
00144     {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY},
00145     {"zxt1",  I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY},
00146     {"zxt2",  I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY},
00147     {"zxt4",  I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY},
00148     {"sxt1",  I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY},
00149     {"sxt2",  I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY},
00150     {"sxt4",  I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY},
00151     {"czx1.l",       I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY},
00152     {"czx2.l",       I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY},
00153     {"czx1.r",       I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY},
00154     {"czx2.r",       I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY},
00155 
00156     {"dep",   I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY},
00157 
00158     {"shrp",  I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY},
00159 
00160     {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
00161      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
00162     {"extr.u",       I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY},
00163 
00164     {"shr",   I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
00165      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
00166     {"extr",  I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY},
00167 
00168     {"shl",   I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
00169      PSEUDO | LEN_EQ_64MCNT, 0, NULL},
00170     {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY},
00171     {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY},
00172     {"dep",   I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY},
00173 #define TF(a,b,c) \
00174        I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P1, P2, IMMU5b}, EMPTY
00175 #define TFCM(a,b,c) \
00176        I2, OpX2TaTbYaXcC (5, 0, a, b, 1, 1, c), {P2, P1, IMMU5b}, PSEUDO, 0, NULL
00177     {"tf.z",          TF   (0, 0, 0)},
00178     {"tf.nz",         TFCM (0, 0, 0)},
00179     {"tf.z.unc",      TF   (0, 0, 1)},
00180     {"tf.nz.unc",     TFCM (0, 0, 1)},
00181     {"tf.z.and",      TF   (0, 1, 0)},
00182     {"tf.nz.andcm",   TFCM (0, 1, 0)},
00183     {"tf.nz.and",     TF   (0, 1, 1)},
00184     {"tf.z.andcm",    TFCM (0, 1, 1)},
00185     {"tf.z.or",              TF   (1, 0, 0)},
00186     {"tf.nz.orcm",    TFCM (1, 0, 0)},
00187     {"tf.nz.or",      TF   (1, 0, 1)},
00188     {"tf.z.orcm",     TFCM (1, 0, 1)},
00189     {"tf.z.or.andcm",        TF   (1, 1, 0)},
00190     {"tf.nz.and.orcm",       TFCM (1, 1, 0)},
00191     {"tf.nz.or.andcm",       TF   (1, 1, 1)},
00192     {"tf.z.and.orcm",        TFCM (1, 1, 1)},
00193 #undef TF
00194 #undef TFCM
00195 #define TBIT(a,b,c,d) \
00196         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY
00197 #define TBITCM(a,b,c,d)     \
00198         I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL
00199     {"tbit.z",               TBIT   (0, 0, 0, 0)},
00200     {"tbit.nz",              TBITCM (0, 0, 0, 0)},
00201     {"tbit.z.unc",    TBIT   (0, 0, 0, 1)},
00202     {"tbit.nz.unc",   TBITCM (0, 0, 0, 1)},
00203     {"tbit.z.and",    TBIT   (0, 1, 0, 0)},
00204     {"tbit.nz.andcm",        TBITCM (0, 1, 0, 0)},
00205     {"tbit.nz.and",   TBIT   (0, 1, 0, 1)},
00206     {"tbit.z.andcm",  TBITCM (0, 1, 0, 1)},
00207     {"tbit.z.or",     TBIT   (1, 0, 0, 0)},
00208     {"tbit.nz.orcm",  TBITCM (1, 0, 0, 0)},
00209     {"tbit.nz.or",    TBIT   (1, 0, 0, 1)},
00210     {"tbit.z.orcm",   TBITCM (1, 0, 0, 1)},
00211     {"tbit.z.or.andcm",      TBIT   (1, 1, 0, 0)},
00212     {"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
00213     {"tbit.nz.or.andcm", TBIT   (1, 1, 0, 1)},
00214     {"tbit.z.and.orcm",  TBITCM (1, 1, 0, 1)},
00215 #undef TBIT
00216 #undef TBITCM
00217 #define TNAT(a,b,c,d) \
00218        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY
00219 #define TNATCM(a,b,c,d) \
00220        I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL
00221     {"tnat.z",               TNAT   (0, 0, 1, 0)},
00222     {"tnat.nz",              TNATCM (0, 0, 1, 0)},
00223     {"tnat.z.unc",    TNAT   (0, 0, 1, 1)},
00224     {"tnat.nz.unc",   TNATCM (0, 0, 1, 1)},
00225     {"tnat.z.and",    TNAT   (0, 1, 1, 0)},
00226     {"tnat.nz.andcm",        TNATCM (0, 1, 1, 0)},
00227     {"tnat.nz.and",   TNAT   (0, 1, 1, 1)},
00228     {"tnat.z.andcm",  TNATCM (0, 1, 1, 1)},
00229     {"tnat.z.or",     TNAT   (1, 0, 1, 0)},
00230     {"tnat.nz.orcm",  TNATCM (1, 0, 1, 0)},
00231     {"tnat.nz.or",    TNAT   (1, 0, 1, 1)},
00232     {"tnat.z.orcm",   TNATCM (1, 0, 1, 1)},
00233     {"tnat.z.or.andcm",      TNAT   (1, 1, 1, 0)},
00234     {"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
00235     {"tnat.nz.or.andcm", TNAT   (1, 1, 1, 1)},
00236     {"tnat.z.and.orcm",  TNATCM (1, 1, 1, 1)},
00237 #undef TNAT
00238 #undef TNATCM
00239 
00240     {"pmpyshr2",   I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY},
00241     {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY},
00242     {"pmpy2.r",         I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY},
00243     {"pmpy2.l",         I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY},
00244     {"mix1.r",          I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
00245     {"mix2.r",          I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
00246     {"mix4.r",          I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY},
00247     {"mix1.l",          I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
00248     {"mix2.l",          I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
00249     {"mix4.l",          I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY},
00250     {"pack2.uss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY},
00251     {"pack2.sss",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
00252     {"pack4.sss",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY},
00253     {"unpack1.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
00254     {"unpack2.h",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
00255     {"unpack4.h",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY},
00256     {"unpack1.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
00257     {"unpack2.l",  I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
00258     {"unpack4.l",  I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY},
00259     {"pmin1.u",         I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY},
00260     {"pmax1.u",         I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY},
00261     {"pmin2",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY},
00262     {"pmax2",    I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY},
00263     {"psad1",    I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY},
00264     {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY},
00265     {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY},
00266     {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
00267     {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
00268     {"shr",   I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY},
00269     {"pshr2.u",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
00270     {"pshr4.u",      I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
00271     {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY},
00272     {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
00273     {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY},
00274     {"pshr2.u",      I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
00275     {"pshr4.u",      I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY},
00276     {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
00277     {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
00278     {"shl",   I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
00279     {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
00280     {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
00281     {"popcnt",       I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY},
00282 
00283     {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
00284   };
00285 
00286 #undef I0
00287 #undef I
00288 #undef I2
00289 #undef L
00290 #undef bC
00291 #undef bIh
00292 #undef bTa
00293 #undef bTag13
00294 #undef bTb
00295 #undef bVc
00296 #undef bVe
00297 #undef bWh
00298 #undef bX
00299 #undef bXb
00300 #undef bX2
00301 #undef bX2a
00302 #undef bX2b
00303 #undef bX2c
00304 #undef bX3
00305 #undef bX6
00306 #undef bY
00307 #undef bZa
00308 #undef bZb
00309 #undef mC
00310 #undef mIh
00311 #undef mTa
00312 #undef mTag13
00313 #undef mTb
00314 #undef mVc
00315 #undef mVe
00316 #undef mWh
00317 #undef mX
00318 #undef mXb
00319 #undef mX2
00320 #undef mX2a
00321 #undef mX2b
00322 #undef mX2c
00323 #undef mX3
00324 #undef mX6
00325 #undef mY
00326 #undef mZa
00327 #undef mZb
00328 #undef OpZaZbVeX2aX2b
00329 #undef OpZaZbVeX2aX2bX2c
00330 #undef OpX2X
00331 #undef OpX2XYa
00332 #undef OpX2XYb
00333 #undef OpX2TaTbYaC
00334 #undef OpX3
00335 #undef OpX3X6
00336 #undef OpX3XbIhWh
00337 #undef OpX3XbIhWhTag13
00338 #undef EMPTY