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cell-binutils  2.17cvs20070401
i386-opc.h
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00001 /* Declarations for Intel 80386 opcode table
00002    Copyright 2007
00003    Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler.
00006 
00007    GAS is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2, or (at your option)
00010    any later version.
00011 
00012    GAS is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with GAS; see the file COPYING.  If not, write to the Free
00019    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00020    02110-1301, USA.  */
00021 
00022 #include "opcode/i386.h"
00023 
00024 typedef struct template
00025 {
00026   /* instruction name sans width suffix ("mov" for movl insns) */
00027   char *name;
00028 
00029   /* how many operands */
00030   unsigned int operands;
00031 
00032   /* base_opcode is the fundamental opcode byte without optional
00033      prefix(es).  */
00034   unsigned int base_opcode;
00035 #define Opcode_D     0x2 /* Direction bit:
00036                             set if Reg --> Regmem;
00037                             unset if Regmem --> Reg. */
00038 #define Opcode_FloatR       0x8 /* Bit to swap src/dest for float insns. */
00039 #define Opcode_FloatD 0x400 /* Direction bit for float insns. */
00040 
00041   /* extension_opcode is the 3 bit extension for group <n> insns.
00042      This field is also used to store the 8-bit opcode suffix for the
00043      AMD 3DNow! instructions.
00044      If this template has no extension opcode (the usual case) use None */
00045   unsigned int extension_opcode;
00046 #define None 0xffff         /* If no extension_opcode is possible.  */
00047 
00048   /* cpu feature flags */
00049   unsigned int cpu_flags;
00050 #define Cpu186                0x1  /* i186 or better required */
00051 #define Cpu286                0x2  /* i286 or better required */
00052 #define Cpu386                0x4  /* i386 or better required */
00053 #define Cpu486                0x8  /* i486 or better required */
00054 #define Cpu586               0x10  /* i585 or better required */
00055 #define Cpu686               0x20  /* i686 or better required */
00056 #define CpuP4         0x40  /* Pentium4 or better required */
00057 #define CpuK6         0x80  /* AMD K6 or better required*/
00058 #define CpuSledgehammer 0x100      /* Sledgehammer or better required */
00059 #define CpuMMX              0x200  /* MMX support required */
00060 #define CpuMMX2             0x400  /* extended MMX support (with SSE or 3DNow!Ext) required */
00061 #define CpuSSE              0x800  /* Streaming SIMD extensions required */
00062 #define CpuSSE2             0x1000 /* Streaming SIMD extensions 2 required */
00063 #define Cpu3dnow       0x2000      /* 3dnow! support required */
00064 #define Cpu3dnowA      0x4000      /* 3dnow!Extensions support required */
00065 #define CpuSSE3             0x8000 /* Streaming SIMD extensions 3 required */
00066 #define CpuPadLock    0x10000      /* VIA PadLock required */
00067 #define CpuSVME            0x20000 /* AMD Secure Virtual Machine Ext-s required */
00068 #define CpuVMX             0x40000 /* VMX Instructions required */
00069 #define CpuSSSE3      0x80000      /* Supplemental Streaming SIMD extensions 3 required */
00070 #define CpuSSE4a     0x100000   /* SSE4a New Instuctions required */ 
00071 #define CpuABM       0x200000   /* ABM New Instructions required */
00072 
00073   /* These flags are set by gas depending on the flag_code.  */
00074 #define Cpu64      0x4000000   /* 64bit support required  */
00075 #define CpuNo64      0x8000000   /* Not supported in the 64bit mode  */
00076 
00077   /* The default value for unknown CPUs - enable all features to avoid problems.  */
00078 #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
00079        |CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
00080        |Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuABM|CpuSSE4a)
00081 
00082   /* the bits in opcode_modifier are used to generate the final opcode from
00083      the base_opcode.  These bits also are used to detect alternate forms of
00084      the same instruction */
00085   unsigned int opcode_modifier;
00086 
00087   /* opcode_modifier bits: */
00088 #define D               0x1 /* has direction bit. */
00089 #define W               0x2 /* set if operands can be words or dwords
00090                                encoded the canonical way */
00091 #define Modrm           0x4 /* insn has a modrm byte. */
00092 #define ShortForm      0x10 /* register is in low 3 bits of opcode */
00093 #define Jump           0x40 /* special case for jump insns.  */
00094 #define JumpDword      0x80  /* call and jump */
00095 #define JumpByte      0x100  /* loop and jecxz */
00096 #define JumpInterSegment 0x200     /* special case for intersegment leaps/calls */
00097 #define FloatMF              0x400 /* FP insn memory format bit, sized by 0x4 */
00098 #define FloatR               0x800 /* src/dest swap for floats. */
00099 #define FloatD              0x1000 /* has float insn direction bit. */
00100 #define Size16              0x2000 /* needs size prefix if in 32-bit mode */
00101 #define Size32              0x4000 /* needs size prefix if in 16-bit mode */
00102 #define Size64              0x8000 /* needs size prefix if in 64-bit mode */
00103 #define IgnoreSize     0x10000  /* instruction ignores operand size prefix */
00104 #define DefaultSize    0x20000  /* default insn size depends on mode */
00105 #define No_bSuf             0x40000       /* b suffix on instruction illegal */
00106 #define No_wSuf             0x80000       /* w suffix on instruction illegal */
00107 #define No_lSuf            0x100000       /* l suffix on instruction illegal */
00108 #define No_sSuf            0x200000       /* s suffix on instruction illegal */
00109 #define No_qSuf       0x400000  /* q suffix on instruction illegal */
00110 #define No_xSuf       0x800000  /* x suffix on instruction illegal */
00111 #define FWait      0x1000000       /* instruction needs FWAIT */
00112 #define IsString     0x2000000     /* quick test for string instructions */
00113 #define regKludge    0x4000000     /* fake an extra reg operand for clr, imul */
00114 #define IsPrefix     0x8000000     /* opcode is a prefix */
00115 #define ImmExt           0x10000000       /* instruction has extension in 8 bit imm */
00116 #define NoRex64          0x20000000  /* instruction don't need Rex64 prefix.  */
00117 #define Rex64     0x40000000  /* instruction require Rex64 prefix.  */
00118 #define Ugh       0x80000000       /* deprecated fp insn, gets a warning */
00119 
00120   /* operand_types[i] describes the type of operand i.  This is made
00121      by OR'ing together all of the possible type masks.  (e.g.
00122      'operand_types[i] = Reg|Imm' specifies that operand i can be
00123      either a register or an immediate operand.  */
00124   unsigned int operand_types[MAX_OPERANDS];
00125 
00126   /* operand_types[i] bits */
00127   /* register */
00128 #define Reg8            0x1 /* 8 bit reg */
00129 #define Reg16           0x2 /* 16 bit reg */
00130 #define Reg32           0x4 /* 32 bit reg */
00131 #define Reg64           0x8 /* 64 bit reg */
00132   /* immediate */
00133 #define Imm8           0x10 /* 8 bit immediate */
00134 #define Imm8S          0x20 /* 8 bit immediate sign extended */
00135 #define Imm16          0x40 /* 16 bit immediate */
00136 #define Imm32          0x80 /* 32 bit immediate */
00137 #define Imm32S               0x100 /* 32 bit immediate sign extended */
00138 #define Imm64         0x200 /* 64 bit immediate */
00139 #define Imm1          0x400 /* 1 bit immediate */
00140   /* memory */
00141 #define BaseIndex     0x800
00142   /* Disp8,16,32 are used in different ways, depending on the
00143      instruction.  For jumps, they specify the size of the PC relative
00144      displacement, for baseindex type instructions, they specify the
00145      size of the offset relative to the base register, and for memory
00146      offset instructions such as `mov 1234,%al' they specify the size of
00147      the offset relative to the segment base.  */
00148 #define Disp8        0x1000 /* 8 bit displacement */
00149 #define Disp16              0x2000 /* 16 bit displacement */
00150 #define Disp32              0x4000 /* 32 bit displacement */
00151 #define Disp32S              0x8000       /* 32 bit signed displacement */
00152 #define Disp64              0x10000       /* 64 bit displacement */
00153   /* specials */
00154 #define InOutPortReg   0x20000     /* register to hold in/out port addr = dx */
00155 #define ShiftCount     0x40000     /* register to hold shift count = cl */
00156 #define Control             0x80000       /* Control register */
00157 #define Debug       0x100000       /* Debug register */
00158 #define Test        0x200000       /* Test register */
00159 #define FloatReg      0x400000     /* Float register */
00160 #define FloatAcc      0x800000     /* Float stack top %st(0) */
00161 #define SReg2      0x1000000       /* 2 bit segment register */
00162 #define SReg3      0x2000000       /* 3 bit segment register */
00163 #define Acc        0x4000000       /* Accumulator %al or %ax or %eax */
00164 #define JumpAbsolute 0x8000000
00165 #define RegMMX           0x10000000       /* MMX register */
00166 #define RegXMM           0x20000000       /* XMM registers in PIII */
00167 #define EsSeg     0x40000000       /* String insn operand with fixed es segment */
00168 
00169   /* RegMem is for instructions with a modrm byte where the register
00170      destination operand should be encoded in the mod and regmem fields.
00171      Normally, it will be encoded in the reg field. We add a RegMem
00172      flag to the destination register operand to indicate that it should
00173      be encoded in the regmem field.  */
00174 #define RegMem           0x80000000
00175 
00176 #define Reg   (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
00177 #define WordReg (Reg16|Reg32|Reg64)
00178 #define ImplicitRegister (InOutPortReg|ShiftCount|Acc|FloatAcc)
00179 #define Imm   (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
00180 #define EncImm       (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
00181 #define Disp  (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
00182 #define AnyMem       (Disp8|Disp16|Disp32|Disp32S|BaseIndex)   /* General memory */
00183   /* The following aliases are defined because the opcode table
00184      carefully specifies the allowed memory types for each instruction.
00185      At the moment we can only tell a memory reference size by the
00186      instruction suffix, so there's not much point in defining Mem8,
00187      Mem16, Mem32 and Mem64 opcode modifiers - We might as well just use
00188      the suffix directly to check memory operands.  */
00189 #define LLongMem AnyMem            /* 64 bits (or more) */
00190 #define LongMem AnyMem             /* 32 bit memory ref */
00191 #define ShortMem AnyMem            /* 16 bit memory ref */
00192 #define WordMem AnyMem             /* 16, 32 or 64 bit memory ref */
00193 #define ByteMem AnyMem             /* 8 bit memory ref */
00194 }
00195 template;
00196 
00197 extern const template i386_optab[];
00198 
00199 /* these are for register name --> number & type hash lookup */
00200 typedef struct
00201 {
00202   char *reg_name;
00203   unsigned int reg_type;
00204   unsigned int reg_flags;
00205 #define RegRex           0x1  /* Extended register.  */
00206 #define RegRex64    0x2  /* Extended 8 bit register.  */
00207   unsigned int reg_num;
00208 }
00209 reg_entry;
00210 
00211 /* Entries in i386_regtab.  */
00212 #define REGNAM_AL 1
00213 #define REGNAM_AX 25
00214 #define REGNAM_EAX 41
00215 
00216 extern const reg_entry i386_regtab[];
00217 extern const unsigned int i386_regtab_size;
00218 extern const reg_entry i386_float_regtab[];
00219 extern const unsigned int i386_float_regtab_size;
00220 
00221 typedef struct
00222 {
00223   char *seg_name;
00224   unsigned int seg_prefix;
00225 }
00226 seg_entry;
00227 
00228 extern const seg_entry cs;
00229 extern const seg_entry ds;
00230 extern const seg_entry ss;
00231 extern const seg_entry es;
00232 extern const seg_entry fs;
00233 extern const seg_entry gs;