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cell-binutils  2.17cvs20070401
Classes | Defines | Typedefs | Variables
i386-opc.h File Reference
#include "opcode/i386.h"
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Classes

struct  template
struct  reg_entry
struct  seg_entry

Defines

#define Opcode_D
#define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */
#define Opcode_FloatD   0x400 /* Direction bit for float insns. */
#define None   0xffff /* If no extension_opcode is possible. */
#define Cpu186   0x1 /* i186 or better required */
#define Cpu286   0x2 /* i286 or better required */
#define Cpu386   0x4 /* i386 or better required */
#define Cpu486   0x8 /* i486 or better required */
#define Cpu586   0x10 /* i585 or better required */
#define Cpu686   0x20 /* i686 or better required */
#define CpuP4   0x40 /* Pentium4 or better required */
#define CpuK6   0x80 /* AMD K6 or better required*/
#define CpuSledgehammer   0x100 /* Sledgehammer or better required */
#define CpuMMX   0x200 /* MMX support required */
#define CpuMMX2   0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */
#define CpuSSE   0x800 /* Streaming SIMD extensions required */
#define CpuSSE2   0x1000 /* Streaming SIMD extensions 2 required */
#define Cpu3dnow   0x2000 /* 3dnow! support required */
#define Cpu3dnowA   0x4000 /* 3dnow!Extensions support required */
#define CpuSSE3   0x8000 /* Streaming SIMD extensions 3 required */
#define CpuPadLock   0x10000 /* VIA PadLock required */
#define CpuSVME   0x20000 /* AMD Secure Virtual Machine Ext-s required */
#define CpuVMX   0x40000 /* VMX Instructions required */
#define CpuSSSE3   0x80000 /* Supplemental Streaming SIMD extensions 3 required */
#define CpuSSE4a   0x100000 /* SSE4a New Instuctions required */
#define CpuABM   0x200000 /* ABM New Instructions required */
#define Cpu64   0x4000000 /* 64bit support required */
#define CpuNo64   0x8000000 /* Not supported in the 64bit mode */
#define CpuUnknownFlags
#define D   0x1 /* has direction bit. */
#define W
#define Modrm   0x4 /* insn has a modrm byte. */
#define ShortForm   0x10 /* register is in low 3 bits of opcode */
#define Jump   0x40 /* special case for jump insns. */
#define JumpDword   0x80 /* call and jump */
#define JumpByte   0x100 /* loop and jecxz */
#define JumpInterSegment   0x200 /* special case for intersegment leaps/calls */
#define FloatMF   0x400 /* FP insn memory format bit, sized by 0x4 */
#define FloatR   0x800 /* src/dest swap for floats. */
#define FloatD   0x1000 /* has float insn direction bit. */
#define Size16   0x2000 /* needs size prefix if in 32-bit mode */
#define Size32   0x4000 /* needs size prefix if in 16-bit mode */
#define Size64   0x8000 /* needs size prefix if in 64-bit mode */
#define IgnoreSize   0x10000 /* instruction ignores operand size prefix */
#define DefaultSize   0x20000 /* default insn size depends on mode */
#define No_bSuf   0x40000 /* b suffix on instruction illegal */
#define No_wSuf   0x80000 /* w suffix on instruction illegal */
#define No_lSuf   0x100000 /* l suffix on instruction illegal */
#define No_sSuf   0x200000 /* s suffix on instruction illegal */
#define No_qSuf   0x400000 /* q suffix on instruction illegal */
#define No_xSuf   0x800000 /* x suffix on instruction illegal */
#define FWait   0x1000000 /* instruction needs FWAIT */
#define IsString   0x2000000 /* quick test for string instructions */
#define regKludge   0x4000000 /* fake an extra reg operand for clr, imul */
#define IsPrefix   0x8000000 /* opcode is a prefix */
#define ImmExt   0x10000000 /* instruction has extension in 8 bit imm */
#define NoRex64   0x20000000 /* instruction don't need Rex64 prefix. */
#define Rex64   0x40000000 /* instruction require Rex64 prefix. */
#define Ugh   0x80000000 /* deprecated fp insn, gets a warning */
#define Reg8   0x1 /* 8 bit reg */
#define Reg16   0x2 /* 16 bit reg */
#define Reg32   0x4 /* 32 bit reg */
#define Reg64   0x8 /* 64 bit reg */
#define Imm8   0x10 /* 8 bit immediate */
#define Imm8S   0x20 /* 8 bit immediate sign extended */
#define Imm16   0x40 /* 16 bit immediate */
#define Imm32   0x80 /* 32 bit immediate */
#define Imm32S   0x100 /* 32 bit immediate sign extended */
#define Imm64   0x200 /* 64 bit immediate */
#define Imm1   0x400 /* 1 bit immediate */
#define BaseIndex   0x800
#define Disp8   0x1000 /* 8 bit displacement */
#define Disp16   0x2000 /* 16 bit displacement */
#define Disp32   0x4000 /* 32 bit displacement */
#define Disp32S   0x8000 /* 32 bit signed displacement */
#define Disp64   0x10000 /* 64 bit displacement */
#define InOutPortReg   0x20000 /* register to hold in/out port addr = dx */
#define ShiftCount   0x40000 /* register to hold shift count = cl */
#define Control   0x80000 /* Control register */
#define Debug   0x100000 /* Debug register */
#define Test   0x200000 /* Test register */
#define FloatReg   0x400000 /* Float register */
#define FloatAcc   0x800000 /* Float stack top %st(0) */
#define SReg2   0x1000000 /* 2 bit segment register */
#define SReg3   0x2000000 /* 3 bit segment register */
#define Acc   0x4000000 /* Accumulator %al or %ax or %eax */
#define JumpAbsolute   0x8000000
#define RegMMX   0x10000000 /* MMX register */
#define RegXMM   0x20000000 /* XMM registers in PIII */
#define EsSeg   0x40000000 /* String insn operand with fixed es segment */
#define RegMem   0x80000000
#define Reg   (Reg8|Reg16|Reg32|Reg64) /* gen'l register */
#define WordReg   (Reg16|Reg32|Reg64)
#define ImplicitRegister   (InOutPortReg|ShiftCount|Acc|FloatAcc)
#define Imm   (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */
#define EncImm   (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */
#define Disp   (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */
#define AnyMem   (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */
#define LLongMem   AnyMem /* 64 bits (or more) */
#define LongMem   AnyMem /* 32 bit memory ref */
#define ShortMem   AnyMem /* 16 bit memory ref */
#define WordMem   AnyMem /* 16, 32 or 64 bit memory ref */
#define ByteMem   AnyMem /* 8 bit memory ref */
#define RegRex   0x1 /* Extended register. */
#define RegRex64   0x2 /* Extended 8 bit register. */
#define REGNAM_AL   1
#define REGNAM_AX   25
#define REGNAM_EAX   41

Typedefs

typedef struct template template

Variables

const template i386_optab []
const reg_entry i386_regtab []
const unsigned int i386_regtab_size
const reg_entry i386_float_regtab []
const unsigned int i386_float_regtab_size
const seg_entry cs
const seg_entry ds
const seg_entry ss
const seg_entry es
const seg_entry fs
const seg_entry gs

Class Documentation

struct template

Definition at line 24 of file i386-opc.h.

Class Members
unsigned int base_opcode
unsigned int cpu_flags
unsigned int extension_opcode
char * name
unsigned int opcode_modifier
unsigned int operand_types
unsigned int operands
struct reg_entry

Definition at line 471 of file tc-arm.c.

Collaboration diagram for reg_entry:
Class Members
unsigned char builtin
int image
char * name
const char * name
struct neon_typed_alias * neon
int number
unsigned char number
unsigned int reg_flags
char * reg_name
unsigned int reg_num
unsigned int reg_type
reg_type type
unsigned char type
union reg_entry value
struct seg_entry

Definition at line 218 of file i386-opc.h.

Class Members
char * seg_name
unsigned int seg_prefix

Define Documentation

Acc Acc Acc Acc   0x4000000 /* Accumulator %al or %ax or %eax */

Definition at line 160 of file i386-opc.h.

#define AnyMem   (Disp8|Disp16|Disp32|Disp32S|BaseIndex) /* General memory */

Definition at line 179 of file i386-opc.h.

#define BaseIndex   0x800

Definition at line 138 of file i386-opc.h.

#define ByteMem   AnyMem /* 8 bit memory ref */

Definition at line 190 of file i386-opc.h.

#define Control   0x80000 /* Control register */

Definition at line 153 of file i386-opc.h.

#define Cpu186   0x1 /* i186 or better required */

Definition at line 48 of file i386-opc.h.

#define Cpu286   0x2 /* i286 or better required */

Definition at line 49 of file i386-opc.h.

#define Cpu386   0x4 /* i386 or better required */

Definition at line 50 of file i386-opc.h.

#define Cpu3dnow   0x2000 /* 3dnow! support required */

Definition at line 61 of file i386-opc.h.

#define Cpu3dnowA   0x4000 /* 3dnow!Extensions support required */

Definition at line 62 of file i386-opc.h.

#define Cpu486   0x8 /* i486 or better required */

Definition at line 51 of file i386-opc.h.

#define Cpu586   0x10 /* i585 or better required */

Definition at line 52 of file i386-opc.h.

#define Cpu64   0x4000000 /* 64bit support required */

Definition at line 72 of file i386-opc.h.

#define Cpu686   0x20 /* i686 or better required */

Definition at line 53 of file i386-opc.h.

#define CpuABM   0x200000 /* ABM New Instructions required */

Definition at line 69 of file i386-opc.h.

#define CpuK6   0x80 /* AMD K6 or better required*/

Definition at line 55 of file i386-opc.h.

#define CpuMMX   0x200 /* MMX support required */

Definition at line 57 of file i386-opc.h.

#define CpuMMX2   0x400 /* extended MMX support (with SSE or 3DNow!Ext) required */

Definition at line 58 of file i386-opc.h.

#define CpuNo64   0x8000000 /* Not supported in the 64bit mode */

Definition at line 73 of file i386-opc.h.

#define CpuP4   0x40 /* Pentium4 or better required */

Definition at line 54 of file i386-opc.h.

#define CpuPadLock   0x10000 /* VIA PadLock required */

Definition at line 64 of file i386-opc.h.

#define CpuSledgehammer   0x100 /* Sledgehammer or better required */

Definition at line 56 of file i386-opc.h.

#define CpuSSE   0x800 /* Streaming SIMD extensions required */

Definition at line 59 of file i386-opc.h.

#define CpuSSE2   0x1000 /* Streaming SIMD extensions 2 required */

Definition at line 60 of file i386-opc.h.

#define CpuSSE3   0x8000 /* Streaming SIMD extensions 3 required */

Definition at line 63 of file i386-opc.h.

#define CpuSSE4a   0x100000 /* SSE4a New Instuctions required */

Definition at line 68 of file i386-opc.h.

#define CpuSSSE3   0x80000 /* Supplemental Streaming SIMD extensions 3 required */

Definition at line 67 of file i386-opc.h.

#define CpuSVME   0x20000 /* AMD Secure Virtual Machine Ext-s required */

Definition at line 65 of file i386-opc.h.

#define CpuUnknownFlags
#define CpuVMX   0x40000 /* VMX Instructions required */

Definition at line 66 of file i386-opc.h.

movb< start > SP movb< start > X movw pc D   0x1 /* has direction bit. */

Definition at line 86 of file i386-opc.h.

#define Debug   0x100000 /* Debug register */

Definition at line 154 of file i386-opc.h.

#define DefaultSize   0x20000 /* default insn size depends on mode */

Definition at line 101 of file i386-opc.h.

#define Disp   (Disp8|Disp16|Disp32|Disp32S|Disp64) /* General displacement */

Definition at line 178 of file i386-opc.h.

#define Disp16   0x2000 /* 16 bit displacement */

Definition at line 146 of file i386-opc.h.

#define Disp32   0x4000 /* 32 bit displacement */

Definition at line 147 of file i386-opc.h.

#define Disp32S   0x8000 /* 32 bit signed displacement */

Definition at line 148 of file i386-opc.h.

#define Disp64   0x10000 /* 64 bit displacement */

Definition at line 149 of file i386-opc.h.

#define Disp8   0x1000 /* 8 bit displacement */

Definition at line 145 of file i386-opc.h.

#define EncImm   (Imm8|Imm16|Imm32|Imm32S) /* Encodable gen'l immediate */

Definition at line 177 of file i386-opc.h.

#define EsSeg   0x40000000 /* String insn operand with fixed es segment */

Definition at line 164 of file i386-opc.h.

#define FloatAcc   0x800000 /* Float stack top %st(0) */

Definition at line 157 of file i386-opc.h.

#define FloatD   0x1000 /* has float insn direction bit. */

Definition at line 96 of file i386-opc.h.

#define FloatMF   0x400 /* FP insn memory format bit, sized by 0x4 */

Definition at line 94 of file i386-opc.h.

#define FloatR   0x800 /* src/dest swap for floats. */

Definition at line 95 of file i386-opc.h.

#define FloatReg   0x400000 /* Float register */

Definition at line 156 of file i386-opc.h.

#define FWait   0x1000000 /* instruction needs FWAIT */

Definition at line 108 of file i386-opc.h.

#define IgnoreSize   0x10000 /* instruction ignores operand size prefix */

Definition at line 100 of file i386-opc.h.

#define Imm   (Imm8|Imm8S|Imm16|Imm32S|Imm32|Imm64) /* gen'l immediate */

Definition at line 176 of file i386-opc.h.

#define Imm1   0x400 /* 1 bit immediate */

Definition at line 136 of file i386-opc.h.

#define Imm16   0x40 /* 16 bit immediate */

Definition at line 132 of file i386-opc.h.

#define Imm32   0x80 /* 32 bit immediate */

Definition at line 133 of file i386-opc.h.

#define Imm32S   0x100 /* 32 bit immediate sign extended */

Definition at line 134 of file i386-opc.h.

#define Imm64   0x200 /* 64 bit immediate */

Definition at line 135 of file i386-opc.h.

#define Imm8   0x10 /* 8 bit immediate */

Definition at line 130 of file i386-opc.h.

#define Imm8S   0x20 /* 8 bit immediate sign extended */

Definition at line 131 of file i386-opc.h.

#define ImmExt   0x10000000 /* instruction has extension in 8 bit imm */

Definition at line 112 of file i386-opc.h.

Definition at line 175 of file i386-opc.h.

#define InOutPortReg   0x20000 /* register to hold in/out port addr = dx */

Definition at line 151 of file i386-opc.h.

#define IsPrefix   0x8000000 /* opcode is a prefix */

Definition at line 111 of file i386-opc.h.

#define IsString   0x2000000 /* quick test for string instructions */

Definition at line 109 of file i386-opc.h.

#define Jump   0x40 /* special case for jump insns. */

Definition at line 90 of file i386-opc.h.

#define JumpAbsolute   0x8000000

Definition at line 161 of file i386-opc.h.

#define JumpByte   0x100 /* loop and jecxz */

Definition at line 92 of file i386-opc.h.

#define JumpDword   0x80 /* call and jump */

Definition at line 91 of file i386-opc.h.

#define JumpInterSegment   0x200 /* special case for intersegment leaps/calls */

Definition at line 93 of file i386-opc.h.

#define LLongMem   AnyMem /* 64 bits (or more) */

Definition at line 186 of file i386-opc.h.

#define LongMem   AnyMem /* 32 bit memory ref */

Definition at line 187 of file i386-opc.h.

#define Modrm   0x4 /* insn has a modrm byte. */

Definition at line 88 of file i386-opc.h.

#define No_bSuf   0x40000 /* b suffix on instruction illegal */

Definition at line 102 of file i386-opc.h.

#define No_lSuf   0x100000 /* l suffix on instruction illegal */

Definition at line 104 of file i386-opc.h.

#define No_qSuf   0x400000 /* q suffix on instruction illegal */

Definition at line 106 of file i386-opc.h.

#define No_sSuf   0x200000 /* s suffix on instruction illegal */

Definition at line 105 of file i386-opc.h.

#define No_wSuf   0x80000 /* w suffix on instruction illegal */

Definition at line 103 of file i386-opc.h.

#define No_xSuf   0x800000 /* x suffix on instruction illegal */

Definition at line 107 of file i386-opc.h.

#define None   0xffff /* If no extension_opcode is possible. */

Definition at line 44 of file i386-opc.h.

#define NoRex64   0x20000000 /* instruction don't need Rex64 prefix. */

Definition at line 113 of file i386-opc.h.

#define Opcode_D
Value:
0x2 /* Direction bit:
                            set if Reg --> Regmem;
                            unset if Regmem --> Reg. */

Definition at line 35 of file i386-opc.h.

#define Opcode_FloatD   0x400 /* Direction bit for float insns. */

Definition at line 37 of file i386-opc.h.

#define Opcode_FloatR   0x8 /* Bit to swap src/dest for float insns. */

Definition at line 36 of file i386-opc.h.

#define Reg   (Reg8|Reg16|Reg32|Reg64) /* gen'l register */

Definition at line 173 of file i386-opc.h.

#define Reg16   0x2 /* 16 bit reg */

Definition at line 126 of file i386-opc.h.

#define Reg32   0x4 /* 32 bit reg */

Definition at line 127 of file i386-opc.h.

#define Reg64   0x8 /* 64 bit reg */

Definition at line 128 of file i386-opc.h.

#define Reg8   0x1 /* 8 bit reg */

Definition at line 125 of file i386-opc.h.

#define regKludge   0x4000000 /* fake an extra reg operand for clr, imul */

Definition at line 110 of file i386-opc.h.

#define RegMem   0x80000000

Definition at line 171 of file i386-opc.h.

#define RegMMX   0x10000000 /* MMX register */

Definition at line 162 of file i386-opc.h.

#define REGNAM_AL   1

Definition at line 209 of file i386-opc.h.

#define REGNAM_AX   25

Definition at line 210 of file i386-opc.h.

#define REGNAM_EAX   41

Definition at line 211 of file i386-opc.h.

#define RegRex   0x1 /* Extended register. */

Definition at line 202 of file i386-opc.h.

#define RegRex64   0x2 /* Extended 8 bit register. */

Definition at line 203 of file i386-opc.h.

#define RegXMM   0x20000000 /* XMM registers in PIII */

Definition at line 163 of file i386-opc.h.

#define Rex64   0x40000000 /* instruction require Rex64 prefix. */

Definition at line 114 of file i386-opc.h.

#define ShiftCount   0x40000 /* register to hold shift count = cl */

Definition at line 152 of file i386-opc.h.

#define ShortForm   0x10 /* register is in low 3 bits of opcode */

Definition at line 89 of file i386-opc.h.

#define ShortMem   AnyMem /* 16 bit memory ref */

Definition at line 188 of file i386-opc.h.

#define Size16   0x2000 /* needs size prefix if in 32-bit mode */

Definition at line 97 of file i386-opc.h.

#define Size32   0x4000 /* needs size prefix if in 16-bit mode */

Definition at line 98 of file i386-opc.h.

#define Size64   0x8000 /* needs size prefix if in 64-bit mode */

Definition at line 99 of file i386-opc.h.

#define SReg2   0x1000000 /* 2 bit segment register */

Definition at line 158 of file i386-opc.h.

#define SReg3   0x2000000 /* 3 bit segment register */

Definition at line 159 of file i386-opc.h.

#define Test   0x200000 /* Test register */

Definition at line 155 of file i386-opc.h.

#define Ugh   0x80000000 /* deprecated fp insn, gets a warning */

Definition at line 115 of file i386-opc.h.

#define W
Value:
0x2    /* set if operands can be words or dwords
                               encoded the canonical way */

Definition at line 87 of file i386-opc.h.

#define WordMem   AnyMem /* 16, 32 or 64 bit memory ref */

Definition at line 189 of file i386-opc.h.

#define WordReg   (Reg16|Reg32|Reg64)

Definition at line 174 of file i386-opc.h.


Typedef Documentation


Variable Documentation

Definition at line 1667 of file i386-opc.c.

Definition at line 11 of file intel.d.

Definition at line 11 of file intel.d.

Definition at line 307 of file spu-insns.h.

Definition at line 9 of file gotpc.d.

Definition at line 1652 of file i386-opc.c.

Definition at line 1664 of file i386-opc.c.

Definition at line 25 of file i386-opc.c.

Definition at line 1475 of file i386-opc.c.

Definition at line 1650 of file i386-opc.c.

Definition at line 11 of file intel.d.