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cell-binutils  2.17cvs20070401
i386-opc.c
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00001 /* Intel 80386 opcode table
00002    Copyright 2007
00003    Free Software Foundation, Inc.
00004 
00005    This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
00006 
00007    This program is free software; you can redistribute it and/or modify
00008    it under the terms of the GNU General Public License as published by
00009    the Free Software Foundation; either version 2 of the License, or
00010    (at your option) any later version.
00011 
00012    This program is distributed in the hope that it will be useful,
00013    but WITHOUT ANY WARRANTY; without even the implied warranty of
00014    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015    GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with this program; if not, write to the Free Software
00019    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00020 
00021 #include "sysdep.h"
00022 #include "libiberty.h"
00023 #include "i386-opc.h"
00024 
00025 const template i386_optab[] =
00026 {
00027 
00028 #define X None
00029 #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
00030 #define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
00031 #define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf)
00032 #define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf)
00033 #define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf)
00034 #define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf)
00035 #define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf)
00036 #define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf)
00037 #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf)
00038 #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
00039 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
00040 #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
00041 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
00042 #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
00043 #define bwlq_Suf (No_sSuf|No_xSuf)
00044 #define FP (NoSuf)
00045 #define l_FP (l_Suf)
00046 #define q_FP (q_Suf|NoRex64)
00047 #define x_FP (x_Suf|FloatMF)
00048 #define sl_FP (sl_Suf|FloatMF)
00049 
00050 /* Move instructions.  */
00051 /* We put the 64bit displacement first and we only mark constants
00052    larger than 32bit as Disp64.  */
00053 { "mov",   2, 0xa0, X, Cpu64,  bwlq_Suf|D|W,                   { Disp64, Acc, 0 } },
00054 { "mov",   2, 0xa0, X, CpuNo64,bwl_Suf|D|W,                    { Disp16|Disp32, Acc, 0 } },
00055 { "mov",   2, 0x88, X, 0,    bwlq_Suf|D|W|Modrm,        { Reg, Reg|AnyMem, 0} },
00056 /* In the 64bit mode the short form mov immediate is redefined to have
00057    64bit value.  */
00058 { "mov",   2, 0xb0, X, 0,    bwl_Suf|W|ShortForm,              { EncImm, Reg8|Reg16|Reg32, 0 } },
00059 { "mov",   2, 0xc6, 0, 0,    bwlq_Suf|W|Modrm,          { EncImm, Reg|AnyMem, 0 } },
00060 { "mov",   2, 0xb0, X, Cpu64,       q_Suf|W|ShortForm,         { Imm64, Reg64, 0 } },
00061 /* The segment register moves accept WordReg so that a segment register
00062    can be copied to a 32 bit register, and vice versa, without using a
00063    size prefix.  When moving to a 32 bit register, the upper 16 bits
00064    are set to an implementation defined value (on the Pentium Pro,
00065    the implementation defined value is zero).  */
00066 { "mov",   2, 0x8c, X, 0,    wl_Suf|Modrm,                     { SReg2, WordReg|RegMem, 0 } },
00067 { "mov",   2, 0x8c, X, 0,    w_Suf|Modrm|IgnoreSize,    { SReg2, WordMem, 0 } },
00068 { "mov",   2, 0x8c, X, Cpu386, wl_Suf|Modrm,                   { SReg3, WordReg|RegMem, 0 } },
00069 { "mov",   2, 0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize,  { SReg3, WordMem, 0 } },
00070 { "mov",   2, 0x8e, X, 0,    wl_Suf|Modrm|IgnoreSize,   { WordReg, SReg2, 0 } },
00071 { "mov",   2, 0x8e, X, 0,    w_Suf|Modrm|IgnoreSize,    { WordMem, SReg2, 0 } },
00072 { "mov",   2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg3, 0 } },
00073 { "mov",   2, 0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize,  { WordMem, SReg3, 0 } },
00074 /* Move to/from control debug registers.  In the 16 or 32bit modes they are 32bit.  In the 64bit
00075    mode they are 64bit.*/
00076 { "mov",   2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|RegMem, 0} },
00077 { "mov",   2, 0x0f20, X, Cpu64,     q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|RegMem, 0} },
00078 { "mov",   2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|RegMem, 0} },
00079 { "mov",   2, 0x0f21, X, Cpu64,     q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|RegMem, 0} },
00080 { "mov",   2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,    { Test, Reg32|RegMem, 0} },
00081 { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W,                    { Disp64, Acc, 0 } },
00082 { "movabs",2, 0xb0, X, Cpu64,      q_Suf|W|ShortForm,          { Imm64, Reg64, 0 } },
00083 
00084 /* Move with sign extend.  */
00085 /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid
00086    conflict with the "movs" string move instruction.  */
00087 {"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm,                  { Reg8|ByteMem, Reg32, 0} },
00088 {"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm,                  { Reg8|ByteMem, Reg16, 0} },
00089 {"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm,                  { Reg16|ShortMem,Reg32, 0} },
00090 {"movsbq", 2, 0x0fbe, X, Cpu64,  NoSuf|Modrm|Rex64,            { Reg8|ByteMem, Reg64, 0} },
00091 {"movswq", 2, 0x0fbf, X, Cpu64,  NoSuf|Modrm|Rex64,            { Reg16|ShortMem,Reg64, 0} },
00092 {"movslq", 2,   0x63, X, Cpu64,  NoSuf|Modrm|Rex64,            { Reg32|WordMem, Reg64, 0} },
00093 /* Intel Syntax next 3 insns */
00094 {"movsx",  2, 0x0fbe, X, Cpu386, b_Suf|Modrm,                  { Reg8|ByteMem, WordReg, 0} },
00095 {"movsx",  2, 0x0fbf, X, Cpu386, w_Suf|Modrm,                  { Reg16|ShortMem, Reg32|Reg64, 0} },
00096 {"movsx",  2,   0x63, X, Cpu64,  l_Suf|Modrm|Rex64,            { Reg32|WordMem, Reg64, 0} },
00097 
00098 /* Move with zero extend.  We can't remove "movzb" since existing
00099    assembly codes may use it.  */
00100 {"movzb",  2, 0x0fb6, X, Cpu386, wl_Suf|Modrm,                 { Reg8|ByteMem, WordReg, 0} },
00101 /* "movzbl" & "movzbw" should not be unified into "movzb" for
00102    consistency with the sign extending moves above.  */
00103 {"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,                  { Reg8|ByteMem, Reg32, 0} },
00104 {"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm,                  { Reg8|ByteMem, Reg16, 0} },
00105 {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm,                  { Reg16|ShortMem, Reg32, 0} },
00106 /* These instructions are not particulary useful, since the zero extend
00107    32->64 is implicit, but we can encode them.  */
00108 {"movzbq", 2, 0x0fb6, X, Cpu64,  NoSuf|Modrm|Rex64,            { Reg8|ByteMem,   Reg64, 0} },
00109 {"movzwq", 2, 0x0fb7, X, Cpu64,  NoSuf|Modrm|Rex64,            { Reg16|ShortMem, Reg64, 0} },
00110 /* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful,
00111    since the zero extend 32->64 is implicit, but we can encode them).  */
00112 {"movzx",  2, 0x0fb6, X, Cpu386, b_Suf|Modrm,                  { Reg8|ByteMem, WordReg, 0} },
00113 {"movzx",  2, 0x0fb7, X, Cpu386, w_Suf|Modrm,                  { Reg16|ShortMem, Reg32|Reg64, 0} },
00114 
00115 /* Push instructions.  */
00116 {"push",   1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize,  { WordReg, 0, 0 } },
00117 {"push",   1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize,      { WordReg|WordMem, 0, 0 } },
00118 {"push",   1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,     { Imm8S, 0, 0} },
00119 {"push",   1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,     { Imm16|Imm32, 0, 0} },
00120 {"push",   1, 0x06, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { SReg2, 0, 0 } },
00121 {"push",   1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|ShortForm|DefaultSize, { SReg3, 0, 0 } },
00122 /* In 64bit mode, the operand size is implicitly 64bit.  */
00123 {"push",   1, 0x50, X, Cpu64,      wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } },
00124 {"push",   1, 0xff, 6, Cpu64,      wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
00125 {"push",   1, 0x6a, X, Cpu64,      wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
00126 {"push",   1, 0x68, X, Cpu64,      wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
00127 {"push",   1, 0x0fa0, X, Cpu64,    wq_Suf|ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
00128 
00129 {"pusha",  0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,     { 0, 0, 0 } },
00130 
00131 /* Pop instructions.  */
00132 {"pop",          1,  0x58, X, CpuNo64,     wl_Suf|ShortForm|DefaultSize,     { WordReg, 0, 0 } },
00133 {"pop",          1,  0x8f, 0, CpuNo64,     wl_Suf|Modrm|DefaultSize,  { WordReg|WordMem, 0, 0 } },
00134 {"pop",          1,  0x07, X, CpuNo64,     wl_Suf|ShortForm|DefaultSize,     { SReg2, 0, 0 } },
00135 {"pop",          1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|ShortForm|DefaultSize, { SReg3, 0, 0 } },
00136 /* In 64bit mode, the operand size is implicitly 64bit.  */
00137 {"pop",          1,  0x58, X, Cpu64,       wq_Suf|ShortForm|DefaultSize|NoRex64,    { Reg16|Reg64, 0, 0 } },
00138 {"pop",          1,  0x8f, 0, Cpu64,       wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } },
00139 {"pop",          1, 0x0fa1, X, Cpu64,  wq_Suf|ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
00140 
00141 {"popa",   0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,            { 0, 0, 0 } },
00142 
00143 /* Exchange instructions.
00144    xchg commutes:  we allow both operand orders.
00145  
00146    In the 64bit code, xchg rax, rax is reused for new nop instruction.  */
00147 {"xchg",   2, 0x90, X, 0,   wlq_Suf|ShortForm,   { WordReg, Acc, 0 } },
00148 {"xchg",   2, 0x90, X, 0,   wlq_Suf|ShortForm,   { Acc, WordReg, 0 } },
00149 {"xchg",   2, 0x86, X, 0,   bwlq_Suf|W|Modrm,    { Reg, Reg|AnyMem, 0 } },
00150 {"xchg",   2, 0x86, X, 0,   bwlq_Suf|W|Modrm,    { Reg|AnyMem, Reg, 0 } },
00151 
00152 /* In/out from ports.  */
00153 /* XXX should reject %rax */
00154 {"in",    2,  0xe4, X, 0,    bwl_Suf|W,          { Imm8, Acc, 0 } },
00155 {"in",    2,  0xec, X, 0,    bwl_Suf|W,          { InOutPortReg, Acc, 0 } },
00156 {"in",    1,  0xe4, X, 0,    bwl_Suf|W,          { Imm8, 0, 0 } },
00157 {"in",    1,  0xec, X, 0,    bwl_Suf|W,          { InOutPortReg, 0, 0 } },
00158 {"out",          2,  0xe6, X, 0,    bwl_Suf|W,          { Acc, Imm8, 0 } },
00159 {"out",          2,  0xee, X, 0,    bwl_Suf|W,          { Acc, InOutPortReg, 0 } },
00160 {"out",          1,  0xe6, X, 0,    bwl_Suf|W,          { Imm8, 0, 0 } },
00161 {"out",          1,  0xee, X, 0,    bwl_Suf|W,          { InOutPortReg, 0, 0 } },
00162 
00163 /* Load effective address.  */
00164 {"lea",          2, 0x8d,   X, 0,   wlq_Suf|Modrm,             { WordMem, WordReg, 0 } },
00165 
00166 /* Load segment registers from memory.  */
00167 {"lds",          2,  0xc5, X, CpuNo64, wl_Suf|Modrm,    { WordMem, WordReg, 0} },
00168 {"les",          2,  0xc4, X, CpuNo64, wl_Suf|Modrm,    { WordMem, WordReg, 0} },
00169 {"lfs",          2, 0x0fb4, X, Cpu386, wl_Suf|Modrm,           { WordMem, WordReg, 0} },
00170 {"lgs",          2, 0x0fb5, X, Cpu386, wl_Suf|Modrm,           { WordMem, WordReg, 0} },
00171 {"lss",          2, 0x0fb2, X, Cpu386, wl_Suf|Modrm,           { WordMem, WordReg, 0} },
00172 
00173 /* Flags register instructions.  */
00174 {"clc",          0,  0xf8, X, 0,    NoSuf,                     { 0, 0, 0} },
00175 {"cld",          0,  0xfc, X, 0,    NoSuf,                     { 0, 0, 0} },
00176 {"cli",          0,  0xfa, X, 0,    NoSuf,                     { 0, 0, 0} },
00177 {"clts",   0, 0x0f06, X, Cpu286, NoSuf,                 { 0, 0, 0} },
00178 {"cmc",          0,  0xf5, X, 0,    NoSuf,                     { 0, 0, 0} },
00179 {"lahf",   0, 0x9f, X, 0,    NoSuf,                     { 0, 0, 0} },
00180 {"sahf",   0, 0x9e, X, 0,    NoSuf,                     { 0, 0, 0} },
00181 {"pushf",  0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize,      { 0, 0, 0} },
00182 {"pushf",  0, 0x9c, X, Cpu64,       wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
00183 {"popf",   0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize,      { 0, 0, 0} },
00184 {"popf",   0, 0x9d, X, Cpu64,       wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
00185 {"stc",          0,  0xf9, X, 0,    NoSuf,                     { 0, 0, 0} },
00186 {"std",          0,  0xfd, X, 0,    NoSuf,                     { 0, 0, 0} },
00187 {"sti",          0,  0xfb, X, 0,    NoSuf,                     { 0, 0, 0} },
00188 
00189 /* Arithmetic.  */
00190 {"add",          2,  0x00, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00191 {"add",          2,  0x83, 0, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00192 {"add",          2,  0x04, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00193 {"add",          2,  0x80, 0, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00194 
00195 {"inc",          1,  0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} },
00196 {"inc",          1,  0xfe, 0, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00197 
00198 {"sub",          2,  0x28, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00199 {"sub",          2,  0x83, 5, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00200 {"sub",          2,  0x2c, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00201 {"sub",          2,  0x80, 5, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00202 
00203 {"dec",          1,  0x48, X, CpuNo64, wl_Suf|ShortForm,       { WordReg, 0, 0} },
00204 {"dec",          1,  0xfe, 1, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00205 
00206 {"sbb",          2,  0x18, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00207 {"sbb",          2,  0x83, 3, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00208 {"sbb",          2,  0x1c, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00209 {"sbb",          2,  0x80, 3, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00210 
00211 {"cmp",          2,  0x38, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00212 {"cmp",          2,  0x83, 7, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00213 {"cmp",          2,  0x3c, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00214 {"cmp",          2,  0x80, 7, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00215 
00216 {"test",   2, 0x84, X, 0,    bwlq_Suf|W|Modrm,   { Reg, Reg|AnyMem, 0} },
00217 {"test",   2, 0x84, X, 0,    bwlq_Suf|W|Modrm,   { AnyMem, Reg, 0} },
00218 {"test",   2, 0xa8, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00219 {"test",   2, 0xf6, 0, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00220 
00221 {"and",          2,  0x20, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00222 {"and",          2,  0x83, 4, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00223 {"and",          2,  0x24, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00224 {"and",          2,  0x80, 4, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00225 
00226 {"or",    2,  0x08, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00227 {"or",    2,  0x83, 1, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00228 {"or",    2,  0x0c, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00229 {"or",    2,  0x80, 1, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00230 
00231 {"xor",          2,  0x30, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00232 {"xor",          2,  0x83, 6, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00233 {"xor",          2,  0x34, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00234 {"xor",          2,  0x80, 6, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00235 
00236 /* clr with 1 operand is really xor with 2 operands.  */
00237 {"clr",          1,  0x30, X, 0,    bwlq_Suf|W|Modrm|regKludge,       { Reg, 0, 0 } },
00238 
00239 {"adc",          2,  0x10, X, 0,    bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} },
00240 {"adc",          2,  0x83, 2, 0,    wlq_Suf|Modrm,             { Imm8S, WordReg|WordMem, 0} },
00241 {"adc",          2,  0x14, X, 0,    bwlq_Suf|W,         { EncImm, Acc, 0} },
00242 {"adc",          2,  0x80, 2, 0,    bwlq_Suf|W|Modrm,   { EncImm, Reg|AnyMem, 0} },
00243 
00244 {"neg",          1,  0xf6, 3, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00245 {"not",          1,  0xf6, 2, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00246 
00247 {"aaa",          0,  0x37, X, CpuNo64,     NoSuf,                     { 0, 0, 0} },
00248 {"aas",          0,  0x3f, X, CpuNo64,    NoSuf,               { 0, 0, 0} },
00249 {"daa",          0,  0x27, X, CpuNo64,    NoSuf,               { 0, 0, 0} },
00250 {"das",          0,  0x2f, X, CpuNo64,    NoSuf,               { 0, 0, 0} },
00251 {"aad",          0, 0xd50a, X, CpuNo64,   NoSuf,               { 0, 0, 0} },
00252 {"aad",          1,   0xd5, X, CpuNo64,   NoSuf,               { Imm8, 0, 0} },
00253 {"aam",          0, 0xd40a, X, CpuNo64,   NoSuf,               { 0, 0, 0} },
00254 {"aam",          1,   0xd4, X, CpuNo64,   NoSuf,               { Imm8, 0, 0} },
00255 
00256 /* Conversion insns.  */
00257 /* Intel naming */
00258 {"cbw",          0,  0x98, X, 0,    NoSuf|Size16,              { 0, 0, 0} },
00259 {"cdqe",   0, 0x98, X, Cpu64,       NoSuf|Size64,              { 0, 0, 0} },
00260 {"cwde",   0, 0x98, X, 0,    NoSuf|Size32,              { 0, 0, 0} },
00261 {"cwd",          0,  0x99, X, 0,    NoSuf|Size16,              { 0, 0, 0} },
00262 {"cdq",          0,  0x99, X, 0,    NoSuf|Size32,              { 0, 0, 0} },
00263 {"cqo",          0,  0x99, X, Cpu64,       NoSuf|Size64,              { 0, 0, 0} },
00264 /* AT&T naming */
00265 {"cbtw",   0, 0x98, X, 0,    NoSuf|Size16,              { 0, 0, 0} },
00266 {"cltq",   0, 0x98, X, Cpu64,       NoSuf|Size64,              { 0, 0, 0} },
00267 {"cwtl",   0, 0x98, X, 0,    NoSuf|Size32,              { 0, 0, 0} },
00268 {"cwtd",   0, 0x99, X, 0,    NoSuf|Size16,              { 0, 0, 0} },
00269 {"cltd",   0, 0x99, X, 0,    NoSuf|Size32,              { 0, 0, 0} },
00270 {"cqto",   0, 0x99, X, Cpu64,       NoSuf|Size64,              { 0, 0, 0} },
00271 
00272 /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand!  They are
00273    expanding 64-bit multiplies, and *cannot* be selected to accomplish
00274    'imul %ebx, %eax' (opcode 0x0faf must be used in this case)
00275    These multiplies can only be selected with single operand forms.  */
00276 {"mul",          1,  0xf6, 4, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00277 {"imul",   1, 0xf6, 5, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00278 {"imul",   2, 0x0faf, X, Cpu386, wlq_Suf|Modrm,         { WordReg|WordMem, WordReg, 0} },
00279 {"imul",   3, 0x6b, X, Cpu186, wlq_Suf|Modrm,           { Imm8S, WordReg|WordMem, WordReg} },
00280 {"imul",   3, 0x69, X, Cpu186, wlq_Suf|Modrm,           { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} },
00281 /* imul with 2 operands mimics imul with 3 by putting the register in
00282    both i.rm.reg & i.rm.regmem fields.  regKludge enables this
00283    transformation.  */
00284 {"imul",   2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} },
00285 {"imul",   2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} },
00286 
00287 {"div",          1,  0xf6, 6, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00288 {"div",          2,  0xf6, 6, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, Acc, 0} },
00289 {"idiv",   1, 0xf6, 7, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00290 {"idiv",   2, 0xf6, 7, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, Acc, 0} },
00291 
00292 {"rol",          2,  0xd0, 0, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00293 {"rol",          2,  0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00294 {"rol",          2,  0xd2, 0, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00295 {"rol",          1,  0xd0, 0, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00296 
00297 {"ror",          2,  0xd0, 1, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00298 {"ror",          2,  0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00299 {"ror",          2,  0xd2, 1, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00300 {"ror",          1,  0xd0, 1, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00301 
00302 {"rcl",          2,  0xd0, 2, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00303 {"rcl",          2,  0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00304 {"rcl",          2,  0xd2, 2, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00305 {"rcl",          1,  0xd0, 2, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00306 
00307 {"rcr",          2,  0xd0, 3, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00308 {"rcr",          2,  0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00309 {"rcr",          2,  0xd2, 3, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00310 {"rcr",          1,  0xd0, 3, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00311 
00312 {"sal",          2,  0xd0, 4, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00313 {"sal",          2,  0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00314 {"sal",          2,  0xd2, 4, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00315 {"sal",          1,  0xd0, 4, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00316 
00317 {"shl",          2,  0xd0, 4, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00318 {"shl",          2,  0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00319 {"shl",          2,  0xd2, 4, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00320 {"shl",          1,  0xd0, 4, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00321 
00322 {"shr",          2,  0xd0, 5, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00323 {"shr",          2,  0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00324 {"shr",          2,  0xd2, 5, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00325 {"shr",          1,  0xd0, 5, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00326 
00327 {"sar",          2,  0xd0, 7, 0,    bwlq_Suf|W|Modrm,   { Imm1, Reg|AnyMem, 0} },
00328 {"sar",          2,  0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} },
00329 {"sar",          2,  0xd2, 7, 0,    bwlq_Suf|W|Modrm,   { ShiftCount, Reg|AnyMem, 0} },
00330 {"sar",          1,  0xd0, 7, 0,    bwlq_Suf|W|Modrm,   { Reg|AnyMem, 0, 0} },
00331 
00332 {"shld",   3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg, WordReg|WordMem} },
00333 {"shld",   3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm,         { ShiftCount, WordReg, WordReg|WordMem} },
00334 {"shld",   2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
00335 
00336 {"shrd",   3, 0x0fac, X, Cpu386, wlq_Suf|Modrm,         { Imm8, WordReg, WordReg|WordMem} },
00337 {"shrd",   3, 0x0fad, X, Cpu386, wlq_Suf|Modrm,         { ShiftCount, WordReg, WordReg|WordMem} },
00338 {"shrd",   2, 0x0fad, X, Cpu386, wlq_Suf|Modrm,         { WordReg, WordReg|WordMem, 0} },
00339 
00340 /* Control transfer instructions.  */
00341 {"call",   1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize,  { Disp16|Disp32, 0, 0} },
00342 {"call",   1, 0xe8, X, Cpu64,       wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} },
00343 {"call",   1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize,      { WordReg|WordMem|JumpAbsolute, 0, 0} },
00344 {"call",   1, 0xff, 2, Cpu64,       wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} },
00345 /* Intel Syntax */
00346 {"call",   2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
00347 /* Intel Syntax */
00348 {"call",   1, 0xff, 3, 0,    x_Suf|Modrm|DefaultSize,   {WordMem|JumpAbsolute, 0, 0} },
00349 {"lcall",  2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} },
00350 {"lcall",  1, 0xff, 3, 0,    wl_Suf|Modrm|DefaultSize,  {WordMem|JumpAbsolute, 0, 0} },
00351 
00352 {"jmp",          1,  0xeb, X, 0,    NoSuf|Jump,         { Disp,0, 0} },
00353 {"jmp",          1,  0xff, 4, CpuNo64, wl_Suf|Modrm,           { WordReg|WordMem|JumpAbsolute, 0, 0} },
00354 {"jmp",          1,  0xff, 4, Cpu64,       wq_Suf|Modrm|NoRex64,      { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} },
00355 /* Intel Syntax.  */
00356 {"jmp",    2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
00357 /* Intel Syntax.  */
00358 {"jmp",    1, 0xff, 5, 0,    x_Suf|Modrm,        { WordMem|JumpAbsolute, 0, 0} },
00359 {"ljmp",   2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
00360 {"ljmp",   1, 0xff, 5, 0,    wl_Suf|Modrm,              { WordMem|JumpAbsolute, 0, 0} },
00361 
00362 {"ret",          0,  0xc3, X, CpuNo64,wl_Suf|DefaultSize,      { 0, 0, 0} },
00363 {"ret",          1,  0xc2, X, CpuNo64,wl_Suf|DefaultSize,      { Imm16, 0, 0} },
00364 {"ret",          0,  0xc3, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
00365 {"ret",          1,  0xc2, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} },
00366 {"lret",   0, 0xcb, X, 0,    wlq_Suf|DefaultSize,       { 0, 0, 0} },
00367 {"lret",   1, 0xca, X, 0,    wlq_Suf|DefaultSize,       { Imm16, 0, 0} },
00368 {"enter",  2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,     { Imm16, Imm8, 0} },
00369 {"enter",  2, 0xc8, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,     { Imm16, Imm8, 0} },
00370 {"leave",  0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,     { 0, 0, 0} },
00371 {"leave",  0, 0xc9, X, Cpu64,  wq_Suf|DefaultSize|NoRex64,     { 0, 0, 0} },
00372 
00373 /* Conditional jumps.  */
00374 {"jo",    1,  0x70, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00375 {"jno",          1,  0x71, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00376 {"jb",    1,  0x72, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00377 {"jc",    1,  0x72, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00378 {"jnae",   1, 0x72, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00379 {"jnb",          1,  0x73, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00380 {"jnc",          1,  0x73, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00381 {"jae",          1,  0x73, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00382 {"je",    1,  0x74, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00383 {"jz",    1,  0x74, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00384 {"jne",          1,  0x75, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00385 {"jnz",          1,  0x75, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00386 {"jbe",          1,  0x76, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00387 {"jna",          1,  0x76, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00388 {"jnbe",   1, 0x77, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00389 {"ja",    1,  0x77, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00390 {"js",    1,  0x78, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00391 {"jns",          1,  0x79, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00392 {"jp",    1,  0x7a, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00393 {"jpe",          1,  0x7a, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00394 {"jnp",          1,  0x7b, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00395 {"jpo",          1,  0x7b, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00396 {"jl",    1,  0x7c, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00397 {"jnge",   1, 0x7c, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00398 {"jnl",          1,  0x7d, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00399 {"jge",          1,  0x7d, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00400 {"jle",          1,  0x7e, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00401 {"jng",          1,  0x7e, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00402 {"jnle",   1, 0x7f, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00403 {"jg",    1,  0x7f, X, 0,    NoSuf|Jump,         { Disp, 0, 0} },
00404 
00405 /* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
00406 {"jcxz",  1,  0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} },
00407 {"jecxz",  1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
00408 {"jecxz",  1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
00409 {"jrcxz",  1, 0xe3, X, Cpu64,  NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} },
00410 
00411 /* The loop instructions also use the address size prefix to select
00412    %cx rather than %ecx for the loop count, so the `w' form of these
00413    instructions emit an address size prefix rather than a data size
00414    prefix.  */
00415 {"loop",   1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
00416 {"loop",   1, 0xe2, X, Cpu64,       lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
00417 {"loopz",  1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
00418 {"loopz",  1, 0xe1, X, Cpu64,       lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
00419 {"loope",  1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
00420 {"loope",  1, 0xe1, X, Cpu64,       lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
00421 {"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
00422 {"loopnz", 1, 0xe0, X, Cpu64,       lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
00423 {"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
00424 {"loopne", 1, 0xe0, X, Cpu64,       lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
00425 
00426 /* Set byte on flag instructions.  */
00427 {"seto",   1, 0x0f90, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00428 {"setno",  1, 0x0f91, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00429 {"setb",   1, 0x0f92, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00430 {"setc",   1, 0x0f92, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00431 {"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00432 {"setnb",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00433 {"setnc",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00434 {"setae",  1, 0x0f93, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00435 {"sete",   1, 0x0f94, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00436 {"setz",   1, 0x0f94, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00437 {"setne",  1, 0x0f95, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00438 {"setnz",  1, 0x0f95, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00439 {"setbe",  1, 0x0f96, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00440 {"setna",  1, 0x0f96, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00441 {"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00442 {"seta",   1, 0x0f97, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00443 {"sets",   1, 0x0f98, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00444 {"setns",  1, 0x0f99, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00445 {"setp",   1, 0x0f9a, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00446 {"setpe",  1, 0x0f9a, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00447 {"setnp",  1, 0x0f9b, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00448 {"setpo",  1, 0x0f9b, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00449 {"setl",   1, 0x0f9c, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00450 {"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00451 {"setnl",  1, 0x0f9d, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00452 {"setge",  1, 0x0f9d, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00453 {"setle",  1, 0x0f9e, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00454 {"setng",  1, 0x0f9e, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00455 {"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00456 {"setg",   1, 0x0f9f, 0, Cpu386, b_Suf|Modrm,           { Reg8|ByteMem, 0, 0} },
00457 
00458 /* String manipulation.  */
00459 {"cmps",   0, 0xa6, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00460 {"cmps",   2, 0xa6, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, AnyMem, 0} },
00461 {"scmp",   0, 0xa6, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00462 {"scmp",   2, 0xa6, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, AnyMem, 0} },
00463 {"ins",          0,  0x6c, X, Cpu186, bwl_Suf|W|IsString,      { 0, 0, 0} },
00464 {"ins",          2,  0x6c, X, Cpu186, bwl_Suf|W|IsString,      { InOutPortReg, AnyMem|EsSeg, 0} },
00465 {"outs",   0, 0x6e, X, Cpu186, bwl_Suf|W|IsString,      { 0, 0, 0} },
00466 {"outs",   2, 0x6e, X, Cpu186, bwl_Suf|W|IsString,      { AnyMem, InOutPortReg, 0} },
00467 {"lods",   0, 0xac, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00468 {"lods",   1, 0xac, X, 0,    bwlq_Suf|W|IsString,       { AnyMem, 0, 0} },
00469 {"lods",   2, 0xac, X, 0,    bwlq_Suf|W|IsString,       { AnyMem, Acc, 0} },
00470 {"slod",   0, 0xac, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00471 {"slod",   1, 0xac, X, 0,    bwlq_Suf|W|IsString,       { AnyMem, 0, 0} },
00472 {"slod",   2, 0xac, X, 0,    bwlq_Suf|W|IsString,       { AnyMem, Acc, 0} },
00473 {"movs",   0, 0xa4, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00474 {"movs",   2, 0xa4, X, 0,    bwlq_Suf|W|IsString,       { AnyMem, AnyMem|EsSeg, 0} },
00475 {"smov",   0, 0xa4, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00476 {"smov",   2, 0xa4, X, 0,    bwlq_Suf|W|IsString,       { AnyMem, AnyMem|EsSeg, 0} },
00477 {"scas",   0, 0xae, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00478 {"scas",   1, 0xae, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, 0, 0} },
00479 {"scas",   2, 0xae, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, Acc, 0} },
00480 {"ssca",   0, 0xae, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00481 {"ssca",   1, 0xae, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, 0, 0} },
00482 {"ssca",   2, 0xae, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, Acc, 0} },
00483 {"stos",   0, 0xaa, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00484 {"stos",   1, 0xaa, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, 0, 0} },
00485 {"stos",   2, 0xaa, X, 0,    bwlq_Suf|W|IsString,       { Acc, AnyMem|EsSeg, 0} },
00486 {"ssto",   0, 0xaa, X, 0,    bwlq_Suf|W|IsString,       { 0, 0, 0} },
00487 {"ssto",   1, 0xaa, X, 0,    bwlq_Suf|W|IsString,       { AnyMem|EsSeg, 0, 0} },
00488 {"ssto",   2, 0xaa, X, 0,    bwlq_Suf|W|IsString,       { Acc, AnyMem|EsSeg, 0} },
00489 {"xlat",   0, 0xd7, X, 0,    b_Suf|IsString,     { 0, 0, 0} },
00490 {"xlat",   1, 0xd7, X, 0,    b_Suf|IsString,     { AnyMem, 0, 0} },
00491 
00492 /* Bit manipulation.  */
00493 {"bsf",          2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
00494 {"bsr",          2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
00495 {"bt",    2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm,          { WordReg, WordReg|WordMem, 0} },
00496 {"bt",    2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm,          { Imm8, WordReg|WordMem, 0} },
00497 {"btc",          2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm,          { WordReg, WordReg|WordMem, 0} },
00498 {"btc",          2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm,          { Imm8, WordReg|WordMem, 0} },
00499 {"btr",          2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm,          { WordReg, WordReg|WordMem, 0} },
00500 {"btr",          2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm,          { Imm8, WordReg|WordMem, 0} },
00501 {"bts",          2, 0x0fab, X, Cpu386, wlq_Suf|Modrm,          { WordReg, WordReg|WordMem, 0} },
00502 {"bts",          2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm,          { Imm8, WordReg|WordMem, 0} },
00503 
00504 /* Interrupts & op. sys insns.  */
00505 /* See gas/config/tc-i386.c for conversion of 'int $3' into the special
00506    int 3 insn.  */
00507 {"int",          1,  0xcd, X, 0,    NoSuf,                     { Imm8, 0, 0} },
00508 {"int3",   0, 0xcc, X, 0,    NoSuf,                     { 0, 0, 0} },
00509 {"into",   0, 0xce, X, CpuNo64,     NoSuf,                     { 0, 0, 0} },
00510 {"iret",   0, 0xcf, X, 0,    wlq_Suf|DefaultSize,       { 0, 0, 0} },
00511 /* i386sl, i486sl, later 486, and Pentium.  */
00512 {"rsm",          0, 0x0faa, X, Cpu386, NoSuf,                  { 0, 0, 0} },
00513 
00514 {"bound",  2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm,           { WordReg, WordMem, 0} },
00515 
00516 {"hlt",          0,  0xf4, X, 0,    NoSuf,                     { 0, 0, 0} },
00517 
00518 {"nop",    1, 0x0f1f, 0, Cpu686, wlq_Suf|Modrm,         { WordReg|WordMem, 0, 0} },
00519 
00520 /* nop is actually "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
00521    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
00522 {"nop",          0,  0x90, X, 0,    NoSuf,                     { 0, 0, 0} },
00523 
00524 /* Protection control.  */
00525 {"arpl",   2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} },
00526 {"lar",          2, 0x0f02, X, Cpu286, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
00527 {"lgdt",   1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm,         { WordMem, 0, 0} },
00528 {"lgdt",   1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64,           { LLongMem, 0, 0} },
00529 {"lidt",   1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm,         { WordMem, 0, 0} },
00530 {"lidt",   1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64,           { LLongMem, 0, 0} },
00531 {"lldt",   1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
00532 {"lmsw",   1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
00533 {"lsl",          2, 0x0f03, X, Cpu286, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
00534 {"ltr",          1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
00535 
00536 {"sgdt",   1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm,         { WordMem, 0, 0} },
00537 {"sgdt",   1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64,           { LLongMem, 0, 0} },
00538 {"sidt",   1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm,         { WordMem, 0, 0} },
00539 {"sidt",   1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64,           { LLongMem, 0, 0} },
00540 {"sldt",   1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm,         { WordReg, 0, 0} },
00541 {"sldt",   1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
00542 {"smsw",   1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm,         { WordReg, 0, 0} },
00543 {"smsw",   1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
00544 {"str",          1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm,          { WordReg, 0, 0} },
00545 {"str",          1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} },
00546 
00547 {"verr",   1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
00548 {"verw",   1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} },
00549 
00550 /* Floating point instructions.  */
00551 
00552 /* load */
00553 {"fld",          1, 0xd9c0, X, 0,   FP|ShortForm,              { FloatReg, 0, 0} },
00554 {"fld",          1,  0xd9, 0, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00555 {"fld",          1, 0xd9c0, X, 0,   l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
00556 /* Intel Syntax */
00557 {"fld",    1, 0xdb, 5, 0,    x_FP|Modrm,         { LLongMem, 0, 0} },
00558 {"fild",   1, 0xdf, 0, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00559 {"fild",   1, 0xdf, 5, 0,    q_FP|Modrm,         { LLongMem, 0, 0} },
00560 {"fildll", 1, 0xdf, 5, 0,    FP|Modrm,           { LLongMem, 0, 0} },
00561 {"fldt",   1, 0xdb, 5, 0,    FP|Modrm,           { LLongMem, 0, 0} },
00562 {"fbld",   1, 0xdf, 4, 0,    x_Suf|Modrm,        { LLongMem, 0, 0} },
00563 
00564 /* store (no pop) */
00565 {"fst",          1, 0xddd0, X, 0,   FP|ShortForm,              { FloatReg, 0, 0} },
00566 {"fst",          1,  0xd9, 2, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00567 {"fst",          1, 0xddd0, X, 0,   l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
00568 {"fist",   1, 0xdf, 2, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00569 
00570 /* store (with pop) */
00571 {"fstp",   1, 0xddd8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00572 {"fstp",   1, 0xd9, 3, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00573 {"fstp",   1, 0xddd8, X, 0,  l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
00574 /* Intel Syntax */
00575 {"fstp",   1, 0xdb, 7, 0,    x_FP|Modrm,         { LLongMem, 0, 0} },
00576 {"fistp",  1, 0xdf, 3, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00577 {"fistp",  1, 0xdf, 7, 0,    q_FP|Modrm,         { LLongMem, 0, 0} },
00578 {"fistpll",1, 0xdf, 7, 0,    FP|Modrm,           { LLongMem, 0, 0} },
00579 {"fstpt",  1, 0xdb, 7, 0,    FP|Modrm,           { LLongMem, 0, 0} },
00580 {"fbstp",  1, 0xdf, 6, 0,    x_Suf|Modrm,        { LLongMem, 0, 0} },
00581 
00582 /* exchange %st<n> with %st0 */
00583 {"fxch",   1, 0xd9c8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00584 /* alias for fxch %st(1) */
00585 {"fxch",   0, 0xd9c9, X, 0,  FP,                 { 0, 0, 0} },
00586 
00587 /* comparison (without pop) */
00588 {"fcom",   1, 0xd8d0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00589 /* alias for fcom %st(1) */
00590 {"fcom",   0, 0xd8d1, X, 0,  FP,                 { 0, 0, 0} },
00591 {"fcom",   1, 0xd8, 2, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00592 {"fcom",   1, 0xd8d0, X, 0,  l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
00593 {"ficom",  1, 0xde, 2, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00594 
00595 /* comparison (with pop) */
00596 {"fcomp",  1, 0xd8d8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00597 /* alias for fcomp %st(1) */
00598 {"fcomp",  0, 0xd8d9, X, 0,  FP,                 { 0, 0, 0} },
00599 {"fcomp",  1, 0xd8, 3, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00600 {"fcomp",  1, 0xd8d8, X, 0,  l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} },
00601 {"ficomp", 1, 0xde, 3, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00602 {"fcompp", 0, 0xded9, X, 0,  FP,                 { 0, 0, 0} },
00603 
00604 /* unordered comparison (with pop) */
00605 {"fucom",  1, 0xdde0, X, Cpu286, FP|ShortForm,          { FloatReg, 0, 0} },
00606 /* alias for fucom %st(1) */
00607 {"fucom",  0, 0xdde1, X, Cpu286, FP,                    { 0, 0, 0} },
00608 {"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm,          { FloatReg, 0, 0} },
00609 /* alias for fucomp %st(1) */
00610 {"fucomp", 0, 0xdde9, X, Cpu286, FP,                    { 0, 0, 0} },
00611 {"fucompp",0, 0xdae9, X, Cpu286, FP,                    { 0, 0, 0} },
00612 
00613 {"ftst",   0, 0xd9e4, X, 0,  FP,                 { 0, 0, 0} },
00614 {"fxam",   0, 0xd9e5, X, 0,  FP,                 { 0, 0, 0} },
00615 
00616 /* load constants into %st0 */
00617 {"fld1",   0, 0xd9e8, X, 0,  FP,                 { 0, 0, 0} },
00618 {"fldl2t", 0, 0xd9e9, X, 0,  FP,                 { 0, 0, 0} },
00619 {"fldl2e", 0, 0xd9ea, X, 0,  FP,                 { 0, 0, 0} },
00620 {"fldpi",  0, 0xd9eb, X, 0,  FP,                 { 0, 0, 0} },
00621 {"fldlg2", 0, 0xd9ec, X, 0,  FP,                 { 0, 0, 0} },
00622 {"fldln2", 0, 0xd9ed, X, 0,  FP,                 { 0, 0, 0} },
00623 {"fldz",   0, 0xd9ee, X, 0,  FP,                 { 0, 0, 0} },
00624 
00625 /* Arithmetic.  */
00626 
00627 /* add */
00628 {"fadd",   2, 0xd8c0, X, 0,  FP|ShortForm|FloatD,       { FloatReg, FloatAcc, 0} },
00629 /* alias for fadd %st(i), %st */
00630 {"fadd",   1, 0xd8c0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00631 #if SYSV386_COMPAT
00632 /* alias for faddp */
00633 {"fadd",   0, 0xdec1, X, 0,  FP|Ugh,             { 0, 0, 0} },
00634 #endif
00635 {"fadd",   1, 0xd8, 0, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00636 {"fiadd",  1, 0xde, 0, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00637 
00638 {"faddp",  2, 0xdec0, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00639 {"faddp",  1, 0xdec0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00640 /* alias for faddp %st, %st(1) */
00641 {"faddp",  0, 0xdec1, X, 0,  FP,                 { 0, 0, 0} },
00642 {"faddp",  2, 0xdec0, X, 0,  FP|ShortForm|Ugh,   { FloatReg, FloatAcc, 0} },
00643 
00644 /* subtract */
00645 {"fsub",   1, 0xd8e0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00646 #if SYSV386_COMPAT
00647 {"fsub",   2, 0xd8e0, X, 0,  FP|ShortForm|FloatD,       { FloatReg, FloatAcc, 0} },
00648 /* alias for fsubp */
00649 {"fsub",   0, 0xdee1, X, 0,  FP|Ugh,             { 0, 0, 0} },
00650 #else
00651 {"fsub",   2, 0xd8e0, X, 0,  FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
00652 #endif
00653 {"fsub",   1, 0xd8, 4, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00654 {"fisub",  1, 0xde, 4, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00655 
00656 #if SYSV386_COMPAT
00657 {"fsubp",  2, 0xdee0, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00658 {"fsubp",  1, 0xdee0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00659 {"fsubp",  0, 0xdee1, X, 0,  FP,                 { 0, 0, 0} },
00660 #if OLDGCC_COMPAT
00661 {"fsubp",  2, 0xdee0, X, 0,  FP|ShortForm|Ugh,   { FloatReg, FloatAcc, 0} },
00662 #endif
00663 #else
00664 {"fsubp",  2, 0xdee8, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00665 {"fsubp",  1, 0xdee8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00666 {"fsubp",  0, 0xdee9, X, 0,  FP,                 { 0, 0, 0} },
00667 #endif
00668 
00669 /* subtract reverse */
00670 {"fsubr",  1, 0xd8e8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00671 #if SYSV386_COMPAT
00672 {"fsubr",  2, 0xd8e8, X, 0,  FP|ShortForm|FloatD,       { FloatReg, FloatAcc, 0} },
00673 /* alias for fsubrp */
00674 {"fsubr",  0, 0xdee9, X, 0,  FP|Ugh,             { 0, 0, 0} },
00675 #else
00676 {"fsubr",  2, 0xd8e8, X, 0,  FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
00677 #endif
00678 {"fsubr",  1, 0xd8, 5, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00679 {"fisubr", 1, 0xde, 5, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00680 
00681 #if SYSV386_COMPAT
00682 {"fsubrp", 2, 0xdee8, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00683 {"fsubrp", 1, 0xdee8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00684 {"fsubrp", 0, 0xdee9, X, 0,  FP,                 { 0, 0, 0} },
00685 #if OLDGCC_COMPAT
00686 {"fsubrp", 2, 0xdee8, X, 0,  FP|ShortForm|Ugh,   { FloatReg, FloatAcc, 0} },
00687 #endif
00688 #else
00689 {"fsubrp", 2, 0xdee0, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00690 {"fsubrp", 1, 0xdee0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00691 {"fsubrp", 0, 0xdee1, X, 0,  FP,                 { 0, 0, 0} },
00692 #endif
00693 
00694 /* multiply */
00695 {"fmul",   2, 0xd8c8, X, 0,  FP|ShortForm|FloatD,       { FloatReg, FloatAcc, 0} },
00696 {"fmul",   1, 0xd8c8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00697 #if SYSV386_COMPAT
00698 /* alias for fmulp */
00699 {"fmul",   0, 0xdec9, X, 0,  FP|Ugh,             { 0, 0, 0} },
00700 #endif
00701 {"fmul",   1, 0xd8, 1, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00702 {"fimul",  1, 0xde, 1, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00703 
00704 {"fmulp",  2, 0xdec8, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00705 {"fmulp",  1, 0xdec8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00706 {"fmulp",  0, 0xdec9, X, 0,  FP,                 { 0, 0, 0} },
00707 {"fmulp",  2, 0xdec8, X, 0,  FP|ShortForm|Ugh,   { FloatReg, FloatAcc, 0} },
00708 
00709 /* divide */
00710 {"fdiv",   1, 0xd8f0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00711 #if SYSV386_COMPAT
00712 {"fdiv",   2, 0xd8f0, X, 0,  FP|ShortForm|FloatD,       { FloatReg, FloatAcc, 0} },
00713 /* alias for fdivp */
00714 {"fdiv",   0, 0xdef1, X, 0,  FP|Ugh,             { 0, 0, 0} },
00715 #else
00716 {"fdiv",   2, 0xd8f0, X, 0,  FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
00717 #endif
00718 {"fdiv",   1, 0xd8, 6, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00719 {"fidiv",  1, 0xde, 6, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00720 
00721 #if SYSV386_COMPAT
00722 {"fdivp",  2, 0xdef0, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00723 {"fdivp",  1, 0xdef0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00724 {"fdivp",  0, 0xdef1, X, 0,  FP,                 { 0, 0, 0} },
00725 #if OLDGCC_COMPAT
00726 {"fdivp",  2, 0xdef0, X, 0,  FP|ShortForm|Ugh,   { FloatReg, FloatAcc, 0} },
00727 #endif
00728 #else
00729 {"fdivp",  2, 0xdef8, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00730 {"fdivp",  1, 0xdef8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00731 {"fdivp",  0, 0xdef9, X, 0,  FP,                 { 0, 0, 0} },
00732 #endif
00733 
00734 /* divide reverse */
00735 {"fdivr",  1, 0xd8f8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00736 #if SYSV386_COMPAT
00737 {"fdivr",  2, 0xd8f8, X, 0,  FP|ShortForm|FloatD,       { FloatReg, FloatAcc, 0} },
00738 /* alias for fdivrp */
00739 {"fdivr",  0, 0xdef9, X, 0,  FP|Ugh,             { 0, 0, 0} },
00740 #else
00741 {"fdivr",  2, 0xd8f8, X, 0,  FP|ShortForm|FloatD|FloatR, { FloatReg, FloatAcc, 0} },
00742 #endif
00743 {"fdivr",  1, 0xd8, 7, 0,    sl_FP|Modrm,        { LongMem|LLongMem, 0, 0} },
00744 {"fidivr", 1, 0xde, 7, 0,    sl_FP|Modrm,        { ShortMem|LongMem, 0, 0} },
00745 
00746 #if SYSV386_COMPAT
00747 {"fdivrp", 2, 0xdef8, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00748 {"fdivrp", 1, 0xdef8, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00749 {"fdivrp", 0, 0xdef9, X, 0,  FP,                 { 0, 0, 0} },
00750 #if OLDGCC_COMPAT
00751 {"fdivrp", 2, 0xdef8, X, 0,  FP|ShortForm|Ugh,   { FloatReg, FloatAcc, 0} },
00752 #endif
00753 #else
00754 {"fdivrp", 2, 0xdef0, X, 0,  FP|ShortForm,              { FloatAcc, FloatReg, 0} },
00755 {"fdivrp", 1, 0xdef0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00756 {"fdivrp", 0, 0xdef1, X, 0,  FP,                 { 0, 0, 0} },
00757 #endif
00758 
00759 {"f2xm1",  0, 0xd9f0, X, 0,  FP,                 { 0, 0, 0} },
00760 {"fyl2x",  0, 0xd9f1, X, 0,  FP,                 { 0, 0, 0} },
00761 {"fptan",  0, 0xd9f2, X, 0,  FP,                 { 0, 0, 0} },
00762 {"fpatan", 0, 0xd9f3, X, 0,  FP,                 { 0, 0, 0} },
00763 {"fxtract",0, 0xd9f4, X, 0,  FP,                 { 0, 0, 0} },
00764 {"fprem1", 0, 0xd9f5, X, Cpu286, FP,                    { 0, 0, 0} },
00765 {"fdecstp",0, 0xd9f6, X, 0,  FP,                 { 0, 0, 0} },
00766 {"fincstp",0, 0xd9f7, X, 0,  FP,                 { 0, 0, 0} },
00767 {"fprem",  0, 0xd9f8, X, 0,  FP,                 { 0, 0, 0} },
00768 {"fyl2xp1",0, 0xd9f9, X, 0,  FP,                 { 0, 0, 0} },
00769 {"fsqrt",  0, 0xd9fa, X, 0,  FP,                 { 0, 0, 0} },
00770 {"fsincos",0, 0xd9fb, X, Cpu286, FP,                    { 0, 0, 0} },
00771 {"frndint",0, 0xd9fc, X, 0,  FP,                 { 0, 0, 0} },
00772 {"fscale", 0, 0xd9fd, X, 0,  FP,                 { 0, 0, 0} },
00773 {"fsin",   0, 0xd9fe, X, Cpu286, FP,                    { 0, 0, 0} },
00774 {"fcos",   0, 0xd9ff, X, Cpu286, FP,                    { 0, 0, 0} },
00775 {"fchs",   0, 0xd9e0, X, 0,  FP,                 { 0, 0, 0} },
00776 {"fabs",   0, 0xd9e1, X, 0,  FP,                 { 0, 0, 0} },
00777 
00778 /* processor control */
00779 {"fninit", 0, 0xdbe3, X, 0,  FP,                 { 0, 0, 0} },
00780 {"finit",  0, 0xdbe3, X, 0,  FP|FWait,           { 0, 0, 0} },
00781 {"fldcw",  1, 0xd9, 5, 0,    w_Suf|FloatMF|Modrm,       { ShortMem, 0, 0} },
00782 {"fnstcw", 1, 0xd9, 7, 0,    w_Suf|FloatMF|Modrm,       { ShortMem, 0, 0} },
00783 {"fstcw",  1, 0xd9, 7, 0,    w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
00784 /* XXX should reject %al, %eax, and %rax */
00785 {"fnstsw", 1, 0xdfe0, X, 0,  FP|IgnoreSize,             { Acc, 0, 0} },
00786 {"fnstsw", 1, 0xdd, 7, 0,    w_Suf|FloatMF|Modrm,       { ShortMem, 0, 0} },
00787 {"fnstsw", 0, 0xdfe0, X, 0,  FP,                 { 0, 0, 0} },
00788 /* XXX should reject %al, %eax, and %rax */
00789 {"fstsw",  1, 0xdfe0, X, 0,  FP|FWait|IgnoreSize,       { Acc, 0, 0} },
00790 {"fstsw",  1, 0xdd, 7, 0,    w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} },
00791 {"fstsw",  0, 0xdfe0, X, 0,  FP|FWait,           { 0, 0, 0} },
00792 {"fnclex", 0, 0xdbe2, X, 0,  FP,                 { 0, 0, 0} },
00793 {"fclex",  0, 0xdbe2, X, 0,  FP|FWait,           { 0, 0, 0} },
00794 /* Short forms of fldenv, fstenv use data size prefix.  */
00795 {"fnstenv",1, 0xd9, 6, 0,    sl_Suf|Modrm|DefaultSize,         { LLongMem, 0, 0} },
00796 {"fstenv", 1, 0xd9, 6, 0,    sl_Suf|FWait|Modrm|DefaultSize,   { LLongMem, 0, 0} },
00797 {"fldenv", 1, 0xd9, 4, 0,    sl_Suf|Modrm|DefaultSize,         { LLongMem, 0, 0} },
00798 {"fnsave", 1, 0xdd, 6, 0,    sl_Suf|Modrm|DefaultSize,         { LLongMem, 0, 0} },
00799 {"fsave",  1, 0xdd, 6, 0,    sl_Suf|FWait|Modrm|DefaultSize,   { LLongMem, 0, 0} },
00800 {"frstor", 1, 0xdd, 4, 0,    sl_Suf|Modrm|DefaultSize,         { LLongMem, 0, 0} },
00801 
00802 {"ffree",  1, 0xddc0, X, 0,  FP|ShortForm,              { FloatReg, 0, 0} },
00803 /* P6:free st(i), pop st */
00804 {"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm,          { FloatReg, 0, 0} },
00805 {"fnop",   0, 0xd9d0, X, 0,  FP,                 { 0, 0, 0} },
00806 {"fwait",  0, 0x9b, X, 0,    FP,                 { 0, 0, 0} },
00807 
00808 /* Opcode prefixes; we allow them as separate insns too.  */
00809 
00810 {"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize,     { 0, 0, 0} },
00811 {"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
00812 {"aword",  0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize,      { 0, 0, 0} },
00813 {"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize,       { 0, 0, 0} },
00814 {"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
00815 {"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize,      { 0, 0, 0} },
00816 {"word",   0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize,       { 0, 0, 0} },
00817 {"dword",  0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize,      { 0, 0, 0} },
00818 {"lock",   0, 0xf0, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00819 {"wait",   0,   0x9b, X, 0,  NoSuf|IsPrefix,     { 0, 0, 0} },
00820 {"cs",    0,  0x2e, X, 0,   NoSuf|IsPrefix,      { 0, 0, 0} },
00821 {"ds",    0,  0x3e, X, 0,   NoSuf|IsPrefix,      { 0, 0, 0} },
00822 {"es",    0,  0x26, X, CpuNo64,    NoSuf|IsPrefix,      { 0, 0, 0} },
00823 {"fs",    0,  0x64, X, Cpu386, NoSuf|IsPrefix,   { 0, 0, 0} },
00824 {"gs",    0,  0x65, X, Cpu386, NoSuf|IsPrefix,   { 0, 0, 0} },
00825 {"ss",    0,  0x36, X, CpuNo64,    NoSuf|IsPrefix,      { 0, 0, 0} },
00826 {"rep",          0,  0xf3, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00827 {"repe",   0, 0xf3, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00828 {"repz",   0, 0xf3, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00829 {"repne",  0, 0xf2, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00830 {"repnz",  0, 0xf2, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00831 {"ht",    0,  0x3e, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00832 {"hnt",          0,  0x2e, X, 0,    NoSuf|IsPrefix,     { 0, 0, 0} },
00833 {"rex",    0, 0x40, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00834 {"rexz",   0, 0x41, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00835 {"rexy",   0, 0x42, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00836 {"rexyz",  0, 0x43, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00837 {"rexx",   0, 0x44, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00838 {"rexxz",  0, 0x45, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00839 {"rexxy",  0, 0x46, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00840 {"rexxyz", 0, 0x47, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00841 {"rex64",  0, 0x48, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00842 {"rex64z", 0, 0x49, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00843 {"rex64y", 0, 0x4a, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00844 {"rex64yz",0, 0x4b, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00845 {"rex64x", 0, 0x4c, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00846 {"rex64xz",0, 0x4d, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00847 {"rex64xy",0, 0x4e, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00848 {"rex64xyz",0,       0x4f, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00849 {"rex.b",  0, 0x41, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00850 {"rex.x",  0, 0x42, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00851 {"rex.xb", 0, 0x43, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00852 {"rex.r",  0, 0x44, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00853 {"rex.rb", 0, 0x45, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00854 {"rex.rx", 0, 0x46, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00855 {"rex.rxb",0, 0x47, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00856 {"rex.w",  0, 0x48, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00857 {"rex.wb", 0, 0x49, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00858 {"rex.wx", 0, 0x4a, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00859 {"rex.wxb",0, 0x4b, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00860 {"rex.wr", 0, 0x4c, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00861 {"rex.wrb",0, 0x4d, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00862 {"rex.wrx",0, 0x4e, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00863 {"rex.wrxb",0,       0x4f, X, Cpu64,       NoSuf|IsPrefix,     { 0, 0, 0} },
00864 
00865 /* 486 extensions.  */
00866 
00867 {"bswap",   1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm,     { Reg32|Reg64, 0, 0 } },
00868 {"xadd",    2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm,     { Reg, Reg|AnyMem, 0 } },
00869 {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm,     { Reg, Reg|AnyMem, 0 } },
00870 {"invd",    0, 0x0f08, X, Cpu486, NoSuf,         { 0, 0, 0} },
00871 {"wbinvd",  0, 0x0f09, X, Cpu486, NoSuf,         { 0, 0, 0} },
00872 {"invlpg",  1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} },
00873 
00874 /* 586 and late 486 extensions.  */
00875 {"cpuid",   0, 0x0fa2, X, Cpu486, NoSuf,         { 0, 0, 0} },
00876 
00877 /* Pentium extensions.  */
00878 {"wrmsr",   0, 0x0f30, X, Cpu586, NoSuf,         { 0, 0, 0} },
00879 {"rdtsc",   0, 0x0f31, X, Cpu586, NoSuf,         { 0, 0, 0} },
00880 {"rdmsr",   0, 0x0f32, X, Cpu586, NoSuf,         { 0, 0, 0} },
00881 {"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm,          { LLongMem, 0, 0} },
00882 
00883 /* Pentium II/Pentium Pro extensions.  */
00884 {"sysenter",0, 0x0f34, X, Cpu686, NoSuf,         { 0, 0, 0} },
00885 {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf,         { 0, 0, 0} },
00886 {"fxsave",  1, 0x0fae, 0, Cpu686, q_Suf|Modrm,          { LLongMem, 0, 0} },
00887 {"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm,          { LLongMem, 0, 0} },
00888 {"rdpmc",   0, 0x0f33, X, Cpu686, NoSuf,         { 0, 0, 0} },
00889 /* official undefined instr. */
00890 {"ud2",           0, 0x0f0b, X, Cpu686, NoSuf,          { 0, 0, 0} },
00891 /* alias for ud2 */
00892 {"ud2a",    0, 0x0f0b, X, Cpu686, NoSuf,         { 0, 0, 0} },
00893 /* 2nd. official undefined instr. */
00894 {"ud2b",    0, 0x0fb9, X, Cpu686, NoSuf,         { 0, 0, 0} },
00895 
00896 {"cmovo",   2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00897 {"cmovno",  2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00898 {"cmovb",   2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00899 {"cmovc",   2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00900 {"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00901 {"cmovae",  2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00902 {"cmovnc",  2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00903 {"cmovnb",  2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00904 {"cmove",   2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00905 {"cmovz",   2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00906 {"cmovne",  2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00907 {"cmovnz",  2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00908 {"cmovbe",  2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00909 {"cmovna",  2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00910 {"cmova",   2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00911 {"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00912 {"cmovs",   2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00913 {"cmovns",  2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00914 {"cmovp",   2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00915 {"cmovnp",  2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00916 {"cmovl",   2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00917 {"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00918 {"cmovge",  2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00919 {"cmovnl",  2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00920 {"cmovle",  2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00921 {"cmovng",  2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00922 {"cmovg",   2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00923 {"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} },
00924 
00925 {"fcmovb",  2, 0xdac0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00926 {"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00927 {"fcmove",  2, 0xdac8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00928 {"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00929 {"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00930 {"fcmovu",  2, 0xdad8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00931 {"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00932 {"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00933 {"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00934 {"fcmova",  2, 0xdbd0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00935 {"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00936 {"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00937 
00938 {"fcomi",   2, 0xdbf0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00939 {"fcomi",   0, 0xdbf1, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
00940 {"fcomi",   1, 0xdbf0, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
00941 {"fucomi",  2, 0xdbe8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00942 {"fucomi",  0, 0xdbe9, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
00943 {"fucomi",  1, 0xdbe8, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
00944 {"fcomip",  2, 0xdff0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00945 {"fcompi",  2, 0xdff0, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00946 {"fcompi",  0, 0xdff1, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
00947 {"fcompi",  1, 0xdff0, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
00948 {"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00949 {"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm,         { FloatReg, FloatAcc, 0} },
00950 {"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm,         { 0, 0, 0} },
00951 {"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm,         { FloatReg, 0, 0} },
00952 
00953 /* Pentium4 extensions.  */
00954 
00955 {"movnti",   2, 0x0fc3,    X, CpuP4, wlq_Suf|Modrm,            { WordReg, WordMem, 0 } },
00956 {"clflush",  1, 0x0fae,    7, CpuP4, NoSuf|Modrm|IgnoreSize,   { ByteMem, 0, 0 } },
00957 {"lfence",   0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt,             { 0, 0, 0 } },
00958 {"mfence",   0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt,             { 0, 0, 0 } },
00959 {"pause",    0, 0xf390,    X, CpuP4, NoSuf,             { 0, 0, 0 } },
00960 
00961 /* MMX/SSE2 instructions.  */
00962 
00963 {"emms",     0, 0x0f77, X, CpuMMX, NoSuf,               { 0, 0, 0 } },
00964 /* These really shouldn't allow for Reg64 (movq is the right mnemonic for
00965    copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's
00966    spec). AMD's spec, having been in existence for much longer, failed to
00967    recognize that and specified movd for 32- and 64-bit operations.  */
00968 {"movd",     2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } },
00969 {"movd",     2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } },
00970 {"movd",     2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegXMM, 0 } },
00971 {"movd",     2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LongMem, 0 } },
00972 /* In the 64bit mode the short form mov immediate is redefined to have
00973    64bit displacement value.  */
00974 {"movq",     2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX|LLongMem, RegMMX, 0 } },
00975 {"movq",     2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX, RegMMX|LLongMem, 0 } },
00976 {"movq",     2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } },
00977 {"movq",     2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } },
00978 {"movq",     2, 0x0f6e, X, Cpu64,  NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegMMX, 0 } },
00979 {"movq",     2, 0x0f7e, X, Cpu64,  NoSuf|IgnoreSize|Modrm, { RegMMX, Reg64|LLongMem, 0 } },
00980 {"movq",     2, 0x660f6e,X,Cpu64,  NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegXMM, 0 } },
00981 {"movq",     2, 0x660f7e,X,Cpu64,  NoSuf|IgnoreSize|Modrm, { RegXMM, Reg64|LLongMem, 0 } },
00982 /* We put the 64bit displacement first and we only mark constants
00983    larger than 32bit as Disp64.  */
00984 {"movq",   2,   0xa0, X, Cpu64,  NoSuf|D|W|Size64, { Disp64, Acc, 0 } },
00985 {"movq",   2, 0x88, X, Cpu64,       NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
00986 {"movq",   2, 0xc6, 0, Cpu64,       NoSuf|W|Modrm|Size64,      { Imm32S, Reg64|WordMem, 0 } },
00987 {"movq",   2, 0xb0, X, Cpu64,       NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
00988 /* The segment register moves accept Reg64 so that a segment register
00989    can be copied to a 64 bit register, and vice versa.  */
00990 {"movq",   2, 0x8c, X, Cpu64,  NoSuf|Modrm|Size64,      { SReg2|SReg3, Reg64|RegMem, 0 } },
00991 {"movq",   2, 0x8e, X, Cpu64,       NoSuf|Modrm|Size64, { Reg64, SReg2|SReg3, 0 } },
00992 /* Move to/from control debug registers.  In the 16 or 32bit modes they are 32bit.  In the 64bit
00993    mode they are 64bit.*/
00994 {"movq",   2, 0x0f20, X, Cpu64,     NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|RegMem, 0} },
00995 {"movq",   2, 0x0f21, X, Cpu64,     NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|RegMem, 0} },
00996 /* Real MMX instructions.  */
00997 {"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } },
00998 {"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
00999 {"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01000 {"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01001 {"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01002 {"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01003 {"paddb",    2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01004 {"paddb",    2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01005 {"paddw",    2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01006 {"paddw",    2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01007 {"paddd",    2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01008 {"paddd",    2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01009 {"paddq",    2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegMMX|LLongMem, RegMMX, 0 } },
01010 {"paddq",    2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01011 {"paddsb",   2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01012 {"paddsb",   2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01013 {"paddsw",   2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01014 {"paddsw",   2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01015 {"paddusb",  2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01016 {"paddusb",  2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01017 {"paddusw",  2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01018 {"paddusw",  2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01019 {"pand",     2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01020 {"pand",     2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01021 {"pandn",    2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01022 {"pandn",    2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01023 {"pcmpeqb",  2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01024 {"pcmpeqb",  2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01025 {"pcmpeqw",  2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01026 {"pcmpeqw",  2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01027 {"pcmpeqd",  2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01028 {"pcmpeqd",  2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01029 {"pcmpgtb",  2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01030 {"pcmpgtb",  2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01031 {"pcmpgtw",  2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01032 {"pcmpgtw",  2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01033 {"pcmpgtd",  2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01034 {"pcmpgtd",  2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01035 {"pmaddwd",  2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01036 {"pmaddwd",  2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01037 {"pmulhw",   2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01038 {"pmulhw",   2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01039 {"pmullw",   2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01040 {"pmullw",   2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01041 {"por",            2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm,             { RegMMX|LongMem, RegMMX, 0 } },
01042 {"por",            2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,             { RegXMM|LLongMem, RegXMM, 0 } },
01043 {"psllw",    2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01044 {"psllw",    2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01045 {"psllw",    2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01046 {"psllw",    2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01047 {"pslld",    2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01048 {"pslld",    2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01049 {"pslld",    2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01050 {"pslld",    2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01051 {"psllq",    2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01052 {"psllq",    2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01053 {"psllq",    2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01054 {"psllq",    2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01055 {"psraw",    2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01056 {"psraw",    2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01057 {"psraw",    2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01058 {"psraw",    2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01059 {"psrad",    2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01060 {"psrad",    2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01061 {"psrad",    2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01062 {"psrad",    2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01063 {"psrlw",    2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01064 {"psrlw",    2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01065 {"psrlw",    2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01066 {"psrlw",    2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01067 {"psrld",    2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01068 {"psrld",    2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01069 {"psrld",    2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01070 {"psrld",    2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01071 {"psrlq",    2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01072 {"psrlq",    2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01073 {"psrlq",    2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm,            { Imm8, RegMMX, 0 } },
01074 {"psrlq",    2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { Imm8, RegXMM, 0 } },
01075 {"psubb",    2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01076 {"psubb",    2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01077 {"psubw",    2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01078 {"psubw",    2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01079 {"psubd",    2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01080 {"psubd",    2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01081 {"psubq",    2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegMMX|LLongMem, RegMMX, 0 } },
01082 {"psubq",    2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01083 {"psubsb",   2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01084 {"psubsb",   2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01085 {"psubsw",   2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01086 {"psubsw",   2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01087 {"psubusb",  2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01088 {"psubusb",  2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01089 {"psubusw",  2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01090 {"psubusw",  2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01091 {"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01092 {"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01093 {"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01094 {"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01095 {"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01096 {"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01097 {"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01098 {"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01099 {"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01100 {"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01101 {"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01102 {"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01103 {"pxor",     2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm,            { RegMMX|LongMem, RegMMX, 0 } },
01104 {"pxor",     2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm,            { RegXMM|LLongMem, RegXMM, 0 } },
01105 
01106 /* PIII Katmai New Instructions / SIMD instructions.  */
01107 
01108 {"addps",     2, 0x0f58,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01109 {"addss",     2, 0xf30f58,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01110 {"andnps",    2, 0x0f55,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01111 {"andps",     2, 0x0f54,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01112 {"cmpeqps",   2, 0x0fc2,    0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01113 {"cmpeqss",   2, 0xf30fc2,  0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01114 {"cmpleps",   2, 0x0fc2,    2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01115 {"cmpless",   2, 0xf30fc2,  2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01116 {"cmpltps",   2, 0x0fc2,    1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01117 {"cmpltss",   2, 0xf30fc2,  1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01118 {"cmpneqps",  2, 0x0fc2,    4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01119 {"cmpneqss",  2, 0xf30fc2,  4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01120 {"cmpnleps",  2, 0x0fc2,    6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01121 {"cmpnless",  2, 0xf30fc2,  6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01122 {"cmpnltps",  2, 0x0fc2,    5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01123 {"cmpnltss",  2, 0xf30fc2,  5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01124 {"cmpordps",  2, 0x0fc2,    7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01125 {"cmpordss",  2, 0xf30fc2,  7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01126 {"cmpunordps",2, 0x0fc2,    3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } },
01127 {"cmpunordss",2, 0xf30fc2,  3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } },
01128 {"cmpps",     3, 0x0fc2,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
01129 {"cmpss",     3, 0xf30fc2,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } },
01130 {"comiss",    2, 0x0f2f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01131 {"cvtpi2ps",  2, 0x0f2a,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } },
01132 {"cvtps2pi",  2, 0x0f2d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
01133 {"cvtsi2ss",  2, 0xf30f2a,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
01134 {"cvtss2si",  2, 0xf30f2d,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
01135 {"cvttps2pi", 2, 0x0f2c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } },
01136 {"cvttss2si", 2, 0xf30f2c,  X, CpuSSE, lq_Suf|IgnoreSize|Modrm,       { RegXMM|WordMem, Reg32|Reg64, 0 } },
01137 {"divps",     2, 0x0f5e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01138 {"divss",     2, 0xf30f5e,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01139 {"ldmxcsr",   1, 0x0fae,    2, CpuSSE, NoSuf|IgnoreSize|Modrm,        { WordMem, 0, 0 } },
01140 {"maskmovq",  2, 0x0ff7,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX, 0 } },
01141 {"maxps",     2, 0x0f5f,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01142 {"maxss",     2, 0xf30f5f,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01143 {"minps",     2, 0x0f5d,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01144 {"minss",     2, 0xf30f5d,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01145 {"movaps",    2, 0x0f28,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01146 {"movaps",    2, 0x0f29,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
01147 {"movhlps",   2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } },
01148 {"movhps",    2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
01149 {"movhps",    2, 0x0f17,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
01150 {"movlhps",   2, 0x0f16,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM, 0 } },
01151 {"movlps",    2, 0x0f12,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } },
01152 {"movlps",    2, 0x0f13,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } },
01153 {"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,       { RegXMM, Reg32|Reg64, 0 } },
01154 {"movntps",   2, 0x0f2b,    X, CpuSSE, NoSuf|IgnoreSize|Modrm,        { RegXMM, LLongMem, 0 } },
01155 {"movntq",    2, 0x0fe7,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm,        { RegMMX, LLongMem, 0 } },
01156 {"movntdq",   2, 0x660fe7,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm,        { RegXMM, LLongMem, 0 } },
01157 {"movss",     2, 0xf30f10,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01158 {"movss",     2, 0xf30f11,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } },
01159 {"movups",    2, 0x0f10,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01160 {"movups",    2, 0x0f11,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } },
01161 {"mulps",     2, 0x0f59,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01162 {"mulss",     2, 0xf30f59,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01163 {"orps",      2, 0x0f56,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01164 {"pavgb",     2, 0x0fe0,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01165 {"pavgb",     2, 0x660fe0,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01166 {"pavgw",     2, 0x0fe3,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01167 {"pavgw",     2, 0x660fe3,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01168 {"pextrw",    3, 0x0fc5,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm,       { Imm8, RegMMX, Reg32|Reg64 } },
01169 {"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,       { Imm8, RegXMM, Reg32|Reg64 } },
01170 {"pinsrw",    3, 0x0fc4,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm,       { Imm8, Reg32|Reg64|ShortMem, RegMMX } },
01171 {"pinsrw",    3, 0x660fc4,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,       { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
01172 {"pmaxsw",    2, 0x0fee,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01173 {"pmaxsw",    2, 0x660fee,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01174 {"pmaxub",    2, 0x0fde,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01175 {"pmaxub",    2, 0x660fde,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01176 {"pminsw",    2, 0x0fea,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01177 {"pminsw",    2, 0x660fea,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01178 {"pminub",    2, 0x0fda,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01179 {"pminub",    2, 0x660fda,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01180 {"pmovmskb",  2, 0x0fd7,    X, CpuMMX2,lq_Suf|IgnoreSize|Modrm,       { RegMMX, Reg32|Reg64, 0 } },
01181 {"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,       { RegXMM, Reg32|Reg64, 0 } },
01182 {"pmulhuw",   2, 0x0fe4,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01183 {"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01184 {"prefetchnta", 1, 0x0f18,  0, CpuMMX2,NoSuf|IgnoreSize|Modrm,        { LLongMem, 0, 0 } },
01185 {"prefetcht0",  1, 0x0f18,  1, CpuMMX2,NoSuf|IgnoreSize|Modrm,        { LLongMem, 0, 0 } },
01186 {"prefetcht1",  1, 0x0f18,  2, CpuMMX2,NoSuf|IgnoreSize|Modrm,        { LLongMem, 0, 0 } },
01187 {"prefetcht2",  1, 0x0f18,  3, CpuMMX2,NoSuf|IgnoreSize|Modrm,        { LLongMem, 0, 0 } },
01188 {"psadbw",    2, 0x0ff6,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
01189 {"psadbw",    2, 0x660ff6,  X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01190 {"pshufw",    3, 0x0f70,    X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } },
01191 {"rcpps",     2, 0x0f53,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01192 {"rcpss",     2, 0xf30f53,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01193 {"rsqrtps",   2, 0x0f52,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01194 {"rsqrtss",   2, 0xf30f52,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01195 {"sfence",    0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt,       { 0, 0, 0 } },
01196 {"shufps",    3, 0x0fc6,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } },
01197 {"sqrtps",    2, 0x0f51,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01198 {"sqrtss",    2, 0xf30f51,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01199 {"stmxcsr",   1, 0x0fae,    3, CpuSSE, NoSuf|IgnoreSize|Modrm,        { WordMem, 0, 0 } },
01200 {"subps",     2, 0x0f5c,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01201 {"subss",     2, 0xf30f5c,  X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01202 {"ucomiss",   2, 0x0f2e,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } },
01203 {"unpckhps",  2, 0x0f15,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01204 {"unpcklps",  2, 0x0f14,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01205 {"xorps",     2, 0x0f57,    X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
01206 
01207 /* SSE-2 instructions.  */
01208 
01209 {"addpd",     2, 0x660f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01210 {"addsd",     2, 0xf20f58,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01211 {"andnpd",    2, 0x660f55,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01212 {"andpd",     2, 0x660f54,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|WordMem, RegXMM, 0 } },
01213 {"cmpeqpd",   2, 0x660fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01214 {"cmpeqsd",   2, 0xf20fc2,  0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01215 {"cmplepd",   2, 0x660fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01216 {"cmplesd",   2, 0xf20fc2,  2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01217 {"cmpltpd",   2, 0x660fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01218 {"cmpltsd",   2, 0xf20fc2,  1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01219 {"cmpneqpd",  2, 0x660fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01220 {"cmpneqsd",  2, 0xf20fc2,  4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01221 {"cmpnlepd",  2, 0x660fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01222 {"cmpnlesd",  2, 0xf20fc2,  6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01223 {"cmpnltpd",  2, 0x660fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01224 {"cmpnltsd",  2, 0xf20fc2,  5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01225 {"cmpordpd",  2, 0x660fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01226 {"cmpordsd",  2, 0xf20fc2,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01227 {"cmpunordpd",2, 0x660fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } },
01228 {"cmpunordsd",2, 0xf20fc2,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } },
01229 {"cmppd",     3, 0x660fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
01230 /* Intel mode string compare.  */
01231 {"cmpsd",     0, 0xa7,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
01232 {"cmpsd",     2, 0xa7,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
01233 {"cmpsd",     3, 0xf20fc2,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM|LongMem, RegXMM } },
01234 {"comisd",    2, 0x660f2f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01235 {"cvtpi2pd",  2, 0x660f2a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegMMX|LLongMem, RegXMM, 0 } },
01236 {"cvtsi2sd",  2, 0xf20f2a,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } },
01237 {"divpd",     2, 0x660f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01238 {"divsd",     2, 0xf20f5e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01239 {"maxpd",     2, 0x660f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01240 {"maxsd",     2, 0xf20f5f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01241 {"minpd",     2, 0x660f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01242 {"minsd",     2, 0xf20f5d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01243 {"movapd",    2, 0x660f28,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01244 {"movapd",    2, 0x660f29,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },
01245 {"movhpd",    2, 0x660f16,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { LLongMem, RegXMM, 0 } },
01246 {"movhpd",    2, 0x660f17,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, LLongMem, 0 } },
01247 {"movlpd",    2, 0x660f12,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { LLongMem, RegXMM, 0 } },
01248 {"movlpd",    2, 0x660f13,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, LLongMem, 0 } },
01249 {"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64, 0 } },
01250 {"movntpd",   2, 0x660f2b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, LLongMem, 0 } },
01251 /* Intel mode string move.  */
01252 {"movsd",     0, 0xa5,      X, 0, NoSuf|Size32|IsString, { 0, 0, 0} },
01253 {"movsd",     2, 0xa5,      X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} },
01254 {"movsd",     2, 0xf20f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01255 {"movsd",     2, 0xf20f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, RegXMM|LongMem, 0 } },
01256 {"movupd",    2, 0x660f10,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01257 {"movupd",    2, 0x660f11,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },
01258 {"mulpd",     2, 0x660f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01259 {"mulsd",     2, 0xf20f59,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01260 {"orpd",      2, 0x660f56,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01261 {"shufpd",    3, 0x660fc6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
01262 {"sqrtpd",    2, 0x660f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01263 {"sqrtsd",    2, 0xf20f51,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01264 {"subpd",     2, 0x660f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01265 {"subsd",     2, 0xf20f5c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01266 {"ucomisd",   2, 0x660f2e,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01267 {"unpckhpd",  2, 0x660f15,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01268 {"unpcklpd",  2, 0x660f14,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01269 {"xorpd",     2, 0x660f57,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01270 {"cvtdq2pd",  2, 0xf30fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01271 {"cvtpd2dq",  2, 0xf20fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01272 {"cvtdq2ps",  2, 0x0f5b,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01273 {"cvtpd2pi",  2, 0x660f2d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegMMX, 0 } },
01274 {"cvtpd2ps",  2, 0x660f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01275 {"cvtps2pd",  2, 0x0f5a,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01276 {"cvtps2dq",  2, 0x660f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01277 {"cvtsd2si",  2, 0xf20f2d,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } },
01278 {"cvtsd2ss",  2, 0xf20f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01279 {"cvtss2sd",  2, 0xf30f5a,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01280 {"cvttpd2pi", 2, 0x660f2c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegMMX, 0 } },
01281 {"cvttsd2si", 2, 0xf20f2c,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } },
01282 {"cvttpd2dq", 2, 0x660fe6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01283 {"cvttps2dq", 2, 0xf30f5b,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01284 {"maskmovdqu",2, 0x660ff7,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, RegXMM, 0 } },
01285 {"movdqa",    2, 0x660f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01286 {"movdqa",    2, 0x660f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },
01287 {"movdqu",    2, 0xf30f6f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01288 {"movdqu",    2, 0xf30f7f,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM, RegXMM|LLongMem, 0 } },
01289 {"movdq2q",    2, 0xf20fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,      { RegXMM, RegMMX, 0 } },
01290 {"movq2dq",   2, 0xf30fd6,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegMMX, RegXMM, 0 } },
01291 {"pmuludq",   2, 0x0ff4,    X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegMMX|LongMem, RegMMX, 0 } },
01292 {"pmuludq",   2, 0x660ff4,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LongMem, RegXMM, 0 } },
01293 {"pshufd",    3, 0x660f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
01294 {"pshufhw",   3, 0xf30f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
01295 {"pshuflw",   3, 0xf20f70,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM|LLongMem, RegXMM } },
01296 {"pslldq",    2, 0x660f73,  7, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM, 0 } },
01297 {"psrldq",    2, 0x660f73,  3, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { Imm8, RegXMM, 0 } },
01298 {"punpckhqdq",2, 0x660f6d,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01299 {"punpcklqdq",2, 0x660f6c,  X, CpuSSE2, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01300 
01301 /* SSE-3 instructions.  */
01302 
01303 {"addsubpd",  2, 0x660fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01304 {"addsubps",  2, 0xf20fd0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01305 {"cmpxchg16b",1, 0x0fc7,    1, CpuSSE3|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} },
01306 {"fisttp",    1, 0xdf,      1, CpuSSE3, sl_FP|Modrm,    { ShortMem|LongMem, 0, 0} },
01307 {"fisttp",    1, 0xdd,      1, CpuSSE3, q_FP|Modrm,     { LLongMem, 0, 0} },
01308 {"fisttpll",  1, 0xdd,      1, CpuSSE3, FP|Modrm,       { LLongMem, 0, 0} },
01309 {"haddpd",    2, 0x660f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01310 {"haddps",    2, 0xf20f7c,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01311 {"hsubpd",    2, 0x660f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01312 {"hsubps",    2, 0xf20f7d,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01313 {"lddqu",     2, 0xf20ff0,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { LLongMem, RegXMM, 0 } },
01314 {"monitor",   0, 0x0f01, 0xc8, CpuSSE3, NoSuf|ImmExt,   { 0, 0, 0} },
01315 /* monitor is very special. CX and DX are always 64bits with zero upper
01316    32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The
01317    address size override prefix can be used to overrride the AX size in
01318    all modes.  */
01319 /* Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. */
01320 {"monitor",   3, 0x0f01, 0xc8, CpuSSE3|CpuNo64, NoSuf|ImmExt,  { Reg16|Reg32, Reg32, Reg32 } },
01321 /* Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. */
01322 {"monitor",   3, 0x0f01, 0xc8, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,   { Reg32|Reg64, Reg64, Reg64 } },
01323 {"movddup",   2, 0xf20f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01324 {"movshdup",  2, 0xf30f16,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01325 {"movsldup",  2, 0xf30f12,  X, CpuSSE3, NoSuf|IgnoreSize|Modrm,       { RegXMM|LLongMem, RegXMM, 0 } },
01326 {"mwait",     0, 0x0f01, 0xc9, CpuSSE3, NoSuf|ImmExt,   { 0, 0, 0} },
01327 /* mwait is very special. AX and CX are always 64bits with zero upper
01328    32bits in 64bit mode, and 32bits in 16bit and 32bit modes.  */
01329 /* Need to ensure only "mwait %eax,%ecx" is accepted.  */
01330 {"mwait",     2, 0x0f01, 0xc9, CpuSSE3|CpuNo64, NoSuf|ImmExt,  { Reg32, Reg32, 0} },
01331 /* Need to ensure only "mwait %rax,%rcx" is accepted.  */
01332 {"mwait",     2, 0x0f01, 0xc9, CpuSSE3|Cpu64, NoSuf|ImmExt|NoRex64,   { Reg64, Reg64, 0} },
01333 
01334 /* VMX instructions.  */
01335 {"vmcall",    0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
01336 {"vmclear",   1, 0x660fc7,  6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,       { LLongMem, 0, 0} },
01337 {"vmlaunch",  0, 0x0f01, 0xc2, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
01338 {"vmresume",  0, 0x0f01, 0xc3, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
01339 {"vmptrld",   1, 0x0fc7,    6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,       { LLongMem, 0, 0} },
01340 {"vmptrst",   1, 0x0fc7,    7, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,       { LLongMem, 0, 0} },
01341 {"vmread",    2, 0x0f78,    X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32, Reg32|LongMem, 0} },
01342 {"vmread",    2, 0x0f78,    X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64, Reg64|LLongMem, 0} },
01343 {"vmwrite",   2, 0x0f79,    X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32|LongMem, Reg32, 0} },
01344 {"vmwrite",   2, 0x0f79,    X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64|LLongMem, Reg64, 0} },
01345 {"vmxoff",    0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt,    { 0, 0, 0} },
01346 {"vmxon",     1, 0xf30fc7,  6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64,       { LLongMem, 0, 0} },
01347 
01348 /* Supplemental Streaming SIMD extensions 3 Instructions.  */
01349 
01350 {"phaddw",    2,   0x0f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01351 {"phaddw",    2, 0x660f3801,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01352 {"phaddd",    2,   0x0f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01353 {"phaddd",    2, 0x660f3802,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01354 {"phaddsw",   2,   0x0f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01355 {"phaddsw",   2, 0x660f3803,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01356 {"phsubw",    2,   0x0f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01357 {"phsubw",    2, 0x660f3805,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01358 {"phsubd",    2,   0x0f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01359 {"phsubd",    2, 0x660f3806,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01360 {"phsubsw",   2,   0x0f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01361 {"phsubsw",   2, 0x660f3807,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01362 {"pmaddubsw", 2,   0x0f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01363 {"pmaddubsw", 2, 0x660f3804,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01364 {"pmulhrsw", 2,    0x0f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01365 {"pmulhrsw", 2,  0x660f380b,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01366 {"pshufb",   2,    0x0f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01367 {"pshufb",   2,  0x660f3800,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01368 {"psignb",   2,    0x0f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01369 {"psignb",   2,  0x660f3808,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01370 {"psignw",   2,    0x0f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01371 {"psignw",   2,  0x660f3809,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01372 {"psignd",   2,    0x0f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01373 {"psignd",   2,  0x660f380a,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01374 {"palignr",  3,    0x0f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { Imm8, RegMMX|LongMem, RegMMX } },
01375 {"palignr",  3,  0x660f3a0f,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { Imm8, RegXMM|LLongMem, RegXMM } },
01376 {"pabsb",    2,    0x0f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01377 {"pabsb",    2,  0x660f381c,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01378 {"pabsw",    2,    0x0f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01379 {"pabsw",    2,  0x660f381d,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01380 {"pabsd",    2,    0x0f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegMMX|LongMem, RegMMX, 0 } },
01381 {"pabsd",    2,  0x660f381e,X, CpuSSSE3, NoSuf|IgnoreSize|Modrm,      { RegXMM|LLongMem, RegXMM, 0 } },
01382 
01383 /* AMD 3DNow! instructions.  */
01384 
01385 {"prefetch", 1, 0x0f0d,        0, Cpu3dnow, NoSuf|IgnoreSize|Modrm,   { ByteMem, 0, 0 } },
01386 {"prefetchw",1, 0x0f0d,        1, Cpu3dnow, NoSuf|IgnoreSize|Modrm,   { ByteMem, 0, 0 } },
01387 {"femms",    0, 0x0f0e,        X, Cpu3dnow, NoSuf,                    { 0, 0, 0 } },
01388 {"pavgusb",  2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01389 {"pf2id",    2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01390 {"pf2iw",    2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01391 {"pfacc",    2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01392 {"pfadd",    2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01393 {"pfcmpeq",  2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01394 {"pfcmpge",  2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01395 {"pfcmpgt",  2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01396 {"pfmax",    2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01397 {"pfmin",    2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01398 {"pfmul",    2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01399 {"pfnacc",   2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01400 {"pfpnacc",  2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01401 {"pfrcp",    2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01402 {"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01403 {"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01404 {"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01405 {"pfrsqrt",  2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01406 {"pfsub",    2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01407 {"pfsubr",   2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01408 {"pi2fd",    2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01409 {"pi2fw",    2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01410 {"pmulhrw",  2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01411 {"pswapd",   2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt,       { RegMMX|LongMem, RegMMX, 0 } },
01412 
01413 /* AMD extensions. */
01414 {"syscall",  0, 0x0f05,    X, CpuK6,      NoSuf,               { 0, 0, 0} },
01415 {"sysret",   0, 0x0f07,    X, CpuK6,      lq_Suf|DefaultSize,  { 0, 0, 0} },
01416 {"swapgs",   0, 0x0f01, 0xf8, Cpu64,      NoSuf|ImmExt,        { 0, 0, 0} },
01417 {"rdtscp",   0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt,    { 0, 0, 0} },
01418 
01419 /* AMD Pacifica additions.  */
01420 {"clgi",     0, 0x0f01, 0xdd, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01421 {"invlpga",  0, 0x0f01, 0xdf, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01422 /* Need to ensure only "invlpga ...,%ecx" is accepted.  */
01423 {"invlpga",  2, 0x0f01, 0xdf, CpuSVME,    NoSuf|ImmExt,        { AnyMem, Reg32, 0 } },
01424 {"skinit",   0, 0x0f01, 0xde, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01425 {"skinit",   1, 0x0f01, 0xde, CpuSVME,    NoSuf|ImmExt,        { AnyMem, 0, 0 } },
01426 {"stgi",     0, 0x0f01, 0xdc, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01427 {"vmload",   0, 0x0f01, 0xda, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01428 {"vmload",   1, 0x0f01, 0xda, CpuSVME,    NoSuf|ImmExt,        { AnyMem, 0, 0 } },
01429 {"vmmcall",  0, 0x0f01, 0xd9, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01430 {"vmrun",    0, 0x0f01, 0xd8, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01431 {"vmrun",    1, 0x0f01, 0xd8, CpuSVME,    NoSuf|ImmExt,        { AnyMem, 0, 0 } },
01432 {"vmsave",   0, 0x0f01, 0xdb, CpuSVME,    NoSuf|ImmExt,        { 0, 0, 0 } },
01433 {"vmsave",   1, 0x0f01, 0xdb, CpuSVME,    NoSuf|ImmExt,        { AnyMem, 0, 0 } },
01434 
01435 
01436 /* SSE4a instructions */
01437 {"movntsd",  2, 0xf20f2b,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, LongMem, 0 } },
01438 {"movntss",  2, 0xf30f2b,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, WordMem, 0 } },
01439 {"extrq",    3, 0x660f78,  0, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { Imm8, Imm8, RegXMM } },
01440 {"extrq",    2, 0x660f79,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM} },
01441 {"insertq",  2, 0xf20f79,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM} },
01442 {"insertq",  4, 0xf20f78,  X, CpuSSE4a, NoSuf|IgnoreSize|Modrm, { Imm8, Imm8, RegXMM, RegXMM} },
01443 
01444 /* ABM instructions */
01445 {"popcnt",   2, 0xf30fb8,  X, CpuABM, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
01446 {"lzcnt",    2, 0xf30fbd,  X, CpuABM, wlq_Suf|Modrm,          { WordReg|WordMem, WordReg, 0} },
01447 
01448 
01449 /* VIA PadLock extensions.  */
01450 {"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01451 {"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01452 {"xcrypt-cbc",0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01453 {"xcrypt-ctr",0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01454 {"xcrypt-cfb",0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01455 {"xcrypt-ofb",0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01456 {"montmul",   0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01457 {"xsha1",     0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01458 {"xsha256",   0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01459 /* Aliases without hyphens.  */
01460 {"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01461 {"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01462 {"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01463 {"xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01464 {"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01465 {"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01466 /* Alias for xstore-rng.  */
01467 {"xstore",    0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} },
01468 
01469 /* sentinel */
01470 {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} }
01471 };
01472 
01473 /* 386 register table.  */
01474 
01475 const reg_entry i386_regtab[] =
01476 {
01477   /* Make %st first as we test for it.  */
01478   {"st", FloatReg|FloatAcc, 0, 0},
01479   /* 8 bit regs */
01480   {"al", Reg8|Acc, 0, 0},
01481   {"cl", Reg8|ShiftCount, 0, 1},
01482   {"dl", Reg8, 0, 2},
01483   {"bl", Reg8, 0, 3},
01484   {"ah", Reg8, 0, 4},
01485   {"ch", Reg8, 0, 5},
01486   {"dh", Reg8, 0, 6},
01487   {"bh", Reg8, 0, 7},
01488   {"axl", Reg8|Acc, RegRex64, 0},  /* Must be in the "al + 8" slot.  */
01489   {"cxl", Reg8, RegRex64, 1},
01490   {"dxl", Reg8, RegRex64, 2},
01491   {"bxl", Reg8, RegRex64, 3},
01492   {"spl", Reg8, RegRex64, 4},
01493   {"bpl", Reg8, RegRex64, 5},
01494   {"sil", Reg8, RegRex64, 6},
01495   {"dil", Reg8, RegRex64, 7},
01496   {"r8b", Reg8, RegRex64|RegRex, 0},
01497   {"r9b", Reg8, RegRex64|RegRex, 1},
01498   {"r10b", Reg8, RegRex64|RegRex, 2},
01499   {"r11b", Reg8, RegRex64|RegRex, 3},
01500   {"r12b", Reg8, RegRex64|RegRex, 4},
01501   {"r13b", Reg8, RegRex64|RegRex, 5},
01502   {"r14b", Reg8, RegRex64|RegRex, 6},
01503   {"r15b", Reg8, RegRex64|RegRex, 7},
01504   /* 16 bit regs */
01505   {"ax", Reg16|Acc, 0, 0},
01506   {"cx", Reg16, 0, 1},
01507   {"dx", Reg16|InOutPortReg, 0, 2},
01508   {"bx", Reg16|BaseIndex, 0, 3},
01509   {"sp", Reg16, 0, 4},
01510   {"bp", Reg16|BaseIndex, 0, 5},
01511   {"si", Reg16|BaseIndex, 0, 6},
01512   {"di", Reg16|BaseIndex, 0, 7},
01513   {"r8w", Reg16, RegRex, 0},
01514   {"r9w", Reg16, RegRex, 1},
01515   {"r10w", Reg16, RegRex, 2},
01516   {"r11w", Reg16, RegRex, 3},
01517   {"r12w", Reg16, RegRex, 4},
01518   {"r13w", Reg16, RegRex, 5},
01519   {"r14w", Reg16, RegRex, 6},
01520   {"r15w", Reg16, RegRex, 7},
01521   /* 32 bit regs */
01522   {"eax", Reg32|BaseIndex|Acc, 0, 0},  /* Must be in ax + 16 slot.  */
01523   {"ecx", Reg32|BaseIndex, 0, 1},
01524   {"edx", Reg32|BaseIndex, 0, 2},
01525   {"ebx", Reg32|BaseIndex, 0, 3},
01526   {"esp", Reg32, 0, 4},
01527   {"ebp", Reg32|BaseIndex, 0, 5},
01528   {"esi", Reg32|BaseIndex, 0, 6},
01529   {"edi", Reg32|BaseIndex, 0, 7},
01530   {"r8d", Reg32|BaseIndex, RegRex, 0},
01531   {"r9d", Reg32|BaseIndex, RegRex, 1},
01532   {"r10d", Reg32|BaseIndex, RegRex, 2},
01533   {"r11d", Reg32|BaseIndex, RegRex, 3},
01534   {"r12d", Reg32|BaseIndex, RegRex, 4},
01535   {"r13d", Reg32|BaseIndex, RegRex, 5},
01536   {"r14d", Reg32|BaseIndex, RegRex, 6},
01537   {"r15d", Reg32|BaseIndex, RegRex, 7},
01538   {"rax", Reg64|BaseIndex|Acc, 0, 0},
01539   {"rcx", Reg64|BaseIndex, 0, 1},
01540   {"rdx", Reg64|BaseIndex, 0, 2},
01541   {"rbx", Reg64|BaseIndex, 0, 3},
01542   {"rsp", Reg64, 0, 4},
01543   {"rbp", Reg64|BaseIndex, 0, 5},
01544   {"rsi", Reg64|BaseIndex, 0, 6},
01545   {"rdi", Reg64|BaseIndex, 0, 7},
01546   {"r8", Reg64|BaseIndex, RegRex, 0},
01547   {"r9", Reg64|BaseIndex, RegRex, 1},
01548   {"r10", Reg64|BaseIndex, RegRex, 2},
01549   {"r11", Reg64|BaseIndex, RegRex, 3},
01550   {"r12", Reg64|BaseIndex, RegRex, 4},
01551   {"r13", Reg64|BaseIndex, RegRex, 5},
01552   {"r14", Reg64|BaseIndex, RegRex, 6},
01553   {"r15", Reg64|BaseIndex, RegRex, 7},
01554   /* Segment registers.  */
01555   {"es", SReg2, 0, 0},
01556   {"cs", SReg2, 0, 1},
01557   {"ss", SReg2, 0, 2},
01558   {"ds", SReg2, 0, 3},
01559   {"fs", SReg3, 0, 4},
01560   {"gs", SReg3, 0, 5},
01561   /* Control registers.  */
01562   {"cr0", Control, 0, 0},
01563   {"cr1", Control, 0, 1},
01564   {"cr2", Control, 0, 2},
01565   {"cr3", Control, 0, 3},
01566   {"cr4", Control, 0, 4},
01567   {"cr5", Control, 0, 5},
01568   {"cr6", Control, 0, 6},
01569   {"cr7", Control, 0, 7},
01570   {"cr8", Control, RegRex, 0},
01571   {"cr9", Control, RegRex, 1},
01572   {"cr10", Control, RegRex, 2},
01573   {"cr11", Control, RegRex, 3},
01574   {"cr12", Control, RegRex, 4},
01575   {"cr13", Control, RegRex, 5},
01576   {"cr14", Control, RegRex, 6},
01577   {"cr15", Control, RegRex, 7},
01578   /* Debug registers.  */
01579   {"db0", Debug, 0, 0},
01580   {"db1", Debug, 0, 1},
01581   {"db2", Debug, 0, 2},
01582   {"db3", Debug, 0, 3},
01583   {"db4", Debug, 0, 4},
01584   {"db5", Debug, 0, 5},
01585   {"db6", Debug, 0, 6},
01586   {"db7", Debug, 0, 7},
01587   {"db8", Debug, RegRex, 0},
01588   {"db9", Debug, RegRex, 1},
01589   {"db10", Debug, RegRex, 2},
01590   {"db11", Debug, RegRex, 3},
01591   {"db12", Debug, RegRex, 4},
01592   {"db13", Debug, RegRex, 5},
01593   {"db14", Debug, RegRex, 6},
01594   {"db15", Debug, RegRex, 7},
01595   {"dr0", Debug, 0, 0},
01596   {"dr1", Debug, 0, 1},
01597   {"dr2", Debug, 0, 2},
01598   {"dr3", Debug, 0, 3},
01599   {"dr4", Debug, 0, 4},
01600   {"dr5", Debug, 0, 5},
01601   {"dr6", Debug, 0, 6},
01602   {"dr7", Debug, 0, 7},
01603   {"dr8", Debug, RegRex, 0},
01604   {"dr9", Debug, RegRex, 1},
01605   {"dr10", Debug, RegRex, 2},
01606   {"dr11", Debug, RegRex, 3},
01607   {"dr12", Debug, RegRex, 4},
01608   {"dr13", Debug, RegRex, 5},
01609   {"dr14", Debug, RegRex, 6},
01610   {"dr15", Debug, RegRex, 7},
01611   /* Test registers.  */
01612   {"tr0", Test, 0, 0},
01613   {"tr1", Test, 0, 1},
01614   {"tr2", Test, 0, 2},
01615   {"tr3", Test, 0, 3},
01616   {"tr4", Test, 0, 4},
01617   {"tr5", Test, 0, 5},
01618   {"tr6", Test, 0, 6},
01619   {"tr7", Test, 0, 7},
01620   /* MMX and simd registers.  */
01621   {"mm0", RegMMX, 0, 0},
01622   {"mm1", RegMMX, 0, 1},
01623   {"mm2", RegMMX, 0, 2},
01624   {"mm3", RegMMX, 0, 3},
01625   {"mm4", RegMMX, 0, 4},
01626   {"mm5", RegMMX, 0, 5},
01627   {"mm6", RegMMX, 0, 6},
01628   {"mm7", RegMMX, 0, 7},
01629   {"xmm0", RegXMM, 0, 0},
01630   {"xmm1", RegXMM, 0, 1},
01631   {"xmm2", RegXMM, 0, 2},
01632   {"xmm3", RegXMM, 0, 3},
01633   {"xmm4", RegXMM, 0, 4},
01634   {"xmm5", RegXMM, 0, 5},
01635   {"xmm6", RegXMM, 0, 6},
01636   {"xmm7", RegXMM, 0, 7},
01637   {"xmm8", RegXMM, RegRex, 0},
01638   {"xmm9", RegXMM, RegRex, 1},
01639   {"xmm10", RegXMM, RegRex, 2},
01640   {"xmm11", RegXMM, RegRex, 3},
01641   {"xmm12", RegXMM, RegRex, 4},
01642   {"xmm13", RegXMM, RegRex, 5},
01643   {"xmm14", RegXMM, RegRex, 6},
01644   {"xmm15", RegXMM, RegRex, 7},
01645   /* No type will make this register rejected for all purposes except
01646      for addressing.  This saves creating one extra type for RIP.  */
01647   {"rip", BaseIndex, 0, 0},
01648 };
01649 
01650 const unsigned int i386_regtab_size = ARRAY_SIZE (i386_regtab);
01651 
01652 const reg_entry i386_float_regtab[] =
01653 {
01654   {"st(0)", FloatReg|FloatAcc, 0, 0},
01655   {"st(1)", FloatReg, 0, 1},
01656   {"st(2)", FloatReg, 0, 2},
01657   {"st(3)", FloatReg, 0, 3},
01658   {"st(4)", FloatReg, 0, 4},
01659   {"st(5)", FloatReg, 0, 5},
01660   {"st(6)", FloatReg, 0, 6},
01661   {"st(7)", FloatReg, 0, 7}
01662 };
01663 
01664 const unsigned int i386_float_regtab_size = ARRAY_SIZE (i386_float_regtab);
01665 
01666 /* Segment stuff.  */
01667 const seg_entry cs = { "cs", 0x2e };
01668 const seg_entry ds = { "ds", 0x3e };
01669 const seg_entry ss = { "ss", 0x36 };
01670 const seg_entry es = { "es", 0x26 };
01671 const seg_entry fs = { "fs", 0x64 };
01672 const seg_entry gs = { "gs", 0x65 };