Back to index

cell-binutils  2.17cvs20070401
i370-opc.c
Go to the documentation of this file.
00001 /* i370-opc.c -- Instruction 370 (ESA/390) architecture opcode list
00002    Copyright 1994, 1999, 2000, 2001, 2003, 2005 Free Software Foundation, Inc.
00003    PowerPC version written by Ian Lance Taylor, Cygnus Support
00004    Rewritten for i370 ESA/390 support by Linas Vepstas <linas@linas.org> 1998, 1999
00005 
00006    This file is part of GDB, GAS, and the GNU binutils.
00007 
00008    GDB, GAS, and the GNU binutils are free software; you can redistribute
00009    them and/or modify them under the terms of the GNU General Public
00010    License as published by the Free Software Foundation; either version
00011    2, or (at your option) any later version.
00012 
00013    GDB, GAS, and the GNU binutils are distributed in the hope that they
00014    will be useful, but WITHOUT ANY WARRANTY; without even the implied
00015    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00016    the GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with this file; see the file COPYING.  If not, write to the Free
00020    Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00021    02110-1301, USA.  */
00022 
00023 #include <stdio.h>
00024 #include "sysdep.h"
00025 #include "opcode/i370.h"
00026 
00027 /* This file holds the i370 opcode table.  The opcode table
00028    includes almost all of the extended instruction mnemonics.  This
00029    permits the disassembler to use them, and simplifies the assembler
00030    logic, at the cost of increasing the table size.  The table is
00031    strictly constant data, so the compiler should be able to put it in
00032    the .text section.
00033 
00034    This file also holds the operand table.  All knowledge about
00035    inserting operands into instructions and vice-versa is kept in this
00036    file.  */
00037 
00038 /* The functions used to insert and extract complicated operands.  */
00039 
00040 static i370_insn_t
00041 insert_ss_b2 (i370_insn_t insn, long value,
00042              const char **errmsg ATTRIBUTE_UNUSED)
00043 {
00044   insn.i[1] |= (value & 0xf) << 28;
00045   return insn;
00046 }
00047 
00048 static i370_insn_t
00049 insert_ss_d2 (i370_insn_t insn, long value,
00050              const char **errmsg ATTRIBUTE_UNUSED)
00051 {
00052   insn.i[1] |= (value & 0xfff) << 16;
00053   return insn;
00054 }
00055 
00056 static i370_insn_t
00057 insert_rxf_r3 (i370_insn_t insn, long value,
00058               const char **errmsg ATTRIBUTE_UNUSED)
00059 {
00060   insn.i[1] |= (value & 0xf) << 28;
00061   return insn;
00062 }
00063 
00064 static long
00065 extract_ss_b2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
00066 {
00067   return (insn.i[1] >>28) & 0xf;
00068 }
00069 
00070 static long
00071 extract_ss_d2 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
00072 {
00073   return (insn.i[1] >>16) & 0xfff;
00074 }
00075 
00076 static long
00077 extract_rxf_r3 (i370_insn_t insn, int *invalid ATTRIBUTE_UNUSED)
00078 {
00079   return (insn.i[1] >>28) & 0xf;
00080 }
00081 
00082 /* The operands table.
00083    The fields are bits, shift, insert, extract, flags, name.
00084    The types:
00085    I370_OPERAND_GPR register, must name a register, must be present
00086    I370_OPERAND_RELATIVE displacement or legnth field, must be present
00087    I370_OPERAND_BASE base register; if present, must name a register
00088                       if absent, should take value of zero
00089    I370_OPERAND_INDEX index register; if present, must name a register
00090                       if absent, should take value of zero
00091    I370_OPERAND_OPTIONAL other optional operand (usuall reg?).  */
00092 
00093 const struct i370_operand i370_operands[] =
00094 {
00095   /* The zero index is used to indicate the end of the list of
00096      operands.  */
00097 #define UNUSED 0
00098   { 0, 0, 0, 0, 0, "unused" },
00099 
00100   /* The R1 register field in an RR form instruction.  */
00101 #define RR_R1 (UNUSED + 1)
00102 #define RR_R1_MASK (0xf << 4)
00103   { 4, 4, 0, 0, I370_OPERAND_GPR, "RR R1" },
00104 
00105   /* The R2 register field in an RR form instruction.  */
00106 #define RR_R2 (RR_R1 + 1)
00107 #define RR_R2_MASK (0xf)
00108   { 4, 0, 0, 0, I370_OPERAND_GPR, "RR R2" },
00109 
00110   /* The I field in an RR form SVC-style instruction.  */
00111 #define RR_I (RR_R2 + 1)
00112 #define RR_I_MASK (0xff)
00113   { 8, 0, 0, 0, I370_OPERAND_RELATIVE, "RR I (svc)" },
00114 
00115   /* The R1 register field in an RRE form instruction.  */
00116 #define RRE_R1 (RR_I + 1)
00117 #define RRE_R1_MASK (0xf << 4)
00118   { 4, 4, 0, 0, I370_OPERAND_GPR, "RRE R1" },
00119 
00120   /* The R2 register field in an RRE form instruction.  */
00121 #define RRE_R2 (RRE_R1 + 1)
00122 #define RRE_R2_MASK (0xf)
00123   { 4, 0, 0, 0, I370_OPERAND_GPR, "RRE R2" },
00124 
00125   /* The R1 register field in an RRF form instruction.  */
00126 #define RRF_R1 (RRE_R2 + 1)
00127 #define RRF_R1_MASK (0xf << 4)
00128   { 4, 4, 0, 0, I370_OPERAND_GPR, "RRF R1" },
00129 
00130   /* The R2 register field in an RRF form instruction.  */
00131 #define RRF_R2 (RRF_R1 + 1)
00132 #define RRF_R2_MASK (0xf)
00133   { 4, 0, 0, 0, I370_OPERAND_GPR, "RRF R2" },
00134 
00135   /* The R3 register field in an RRF form instruction.  */
00136 #define RRF_R3 (RRF_R2 + 1)
00137 #define RRF_R3_MASK (0xf << 12)
00138   { 4, 12, 0, 0, I370_OPERAND_GPR, "RRF R3" },
00139 
00140   /* The R1 register field in an RX or RS form instruction.  */
00141 #define RX_R1 (RRF_R3 + 1)
00142 #define RX_R1_MASK (0xf << 20)
00143   { 4, 20, 0, 0, I370_OPERAND_GPR, "RX R1" },
00144 
00145   /* The X2 index field in an RX form instruction.  */
00146 #define RX_X2 (RX_R1 + 1)
00147 #define RX_X2_MASK (0xf << 16)
00148   { 4, 16, 0, 0, I370_OPERAND_GPR | I370_OPERAND_INDEX, "RX X2"},
00149 
00150   /* The B2 base field in an RX form instruction.  */
00151 #define RX_B2 (RX_X2 + 1)
00152 #define RX_B2_MASK (0xf << 12)
00153   { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE, "RX B2"},
00154 
00155   /* The D2 displacement field in an RX form instruction.  */
00156 #define RX_D2 (RX_B2 + 1)
00157 #define RX_D2_MASK (0xfff)
00158   { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RX D2"},
00159 
00160  /* The R3 register field in an RXF form instruction.  */
00161 #define RXF_R3 (RX_D2 + 1)
00162 #define RXF_R3_MASK (0xf << 12)
00163   { 4, 12, insert_rxf_r3, extract_rxf_r3, I370_OPERAND_GPR, "RXF R3" },
00164 
00165   /* The D2 displacement field in an RS form instruction.  */
00166 #define RS_D2 (RXF_R3 + 1)
00167 #define RS_D2_MASK (0xfff)
00168   { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "RS D2"},
00169 
00170   /* The R3 register field in an RS form instruction.  */
00171 #define RS_R3 (RS_D2 + 1)
00172 #define RS_R3_MASK (0xf << 16)
00173   { 4, 16, 0, 0, I370_OPERAND_GPR, "RS R3" },
00174 
00175   /* The B2 base field in an RS form instruction.  */
00176 #define RS_B2 (RS_R3 + 1)
00177 #define RS_B2_MASK (0xf << 12)
00178   { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "RS B2"},
00179 
00180   /* The optional B2 base field in an RS form instruction.  */
00181   /* Note that this field will almost always be absent */
00182 #define RS_B2_OPT (RS_B2 + 1)
00183 #define RS_B2_OPT_MASK (0xf << 12)
00184   { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_OPTIONAL, "RS B2 OPT"},
00185 
00186   /* The R1 register field in an RSI form instruction.  */
00187 #define RSI_R1 (RS_B2_OPT + 1)
00188 #define RSI_R1_MASK (0xf << 20)
00189   { 4, 20, 0, 0, I370_OPERAND_GPR, "RSI R1" },
00190 
00191   /* The R3 register field in an RSI form instruction.  */
00192 #define RSI_R3 (RSI_R1 + 1)
00193 #define RSI_R3_MASK (0xf << 16)
00194   { 4, 16, 0, 0, I370_OPERAND_GPR, "RSI R3" },
00195 
00196   /* The I2 immediate field in an RSI form instruction.  */
00197 #define RSI_I2 (RSI_R3 + 1)
00198 #define RSI_I2_MASK (0xffff)
00199   { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RSI I2" },
00200 
00201   /* The R1 register field in an RI form instruction.  */
00202 #define RI_R1 (RSI_I2 + 1)
00203 #define RI_R1_MASK (0xf << 20)
00204   { 4, 20, 0, 0, I370_OPERAND_GPR, "RI R1" },
00205 
00206   /* The I2 immediate field in an RI form instruction.  */
00207 #define RI_I2 (RI_R1 + 1)
00208 #define RI_I2_MASK (0xffff)
00209   { 16, 0, 0, 0, I370_OPERAND_RELATIVE, "RI I2" },
00210 
00211  /* The I2 index field in an SI form instruction.  */
00212 #define SI_I2 (RI_I2 + 1)
00213 #define SI_I2_MASK (0xff << 16)
00214   { 8, 16, 0, 0, I370_OPERAND_RELATIVE, "SI I2"},
00215 
00216  /* The B1 base register field in an SI form instruction.  */
00217 #define SI_B1 (SI_I2 + 1)
00218 #define SI_B1_MASK (0xf << 12)
00219   { 4, 12, 0, 0, I370_OPERAND_GPR, "SI B1" },
00220 
00221   /* The D1 displacement field in an SI form instruction.  */
00222 #define SI_D1 (SI_B1 + 1)
00223 #define SI_D1_MASK (0xfff)
00224   { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SI D1" },
00225 
00226  /* The B2 base register field in an S form instruction.  */
00227 #define S_B2 (SI_D1 + 1)
00228 #define S_B2_MASK (0xf << 12)
00229   { 4, 12, 0, 0, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "S B2" },
00230 
00231   /* The D2 displacement field in an S form instruction.  */
00232 #define S_D2 (S_B2 + 1)
00233 #define S_D2_MASK (0xfff)
00234   { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "S D2" },
00235 
00236   /* The L length field in an SS form instruction.  */
00237 #define SS_L (S_D2 + 1)
00238 #define SS_L_MASK (0xffff<<16)
00239   { 8, 16, 0, 0, I370_OPERAND_RELATIVE | I370_OPERAND_LENGTH, "SS L" },
00240 
00241  /* The B1 base register field in an SS form instruction.  */
00242 #define SS_B1 (SS_L + 1)
00243 #define SS_B1_MASK (0xf << 12)
00244   { 4, 12, 0, 0, I370_OPERAND_GPR, "SS B1" },
00245 
00246   /* The D1 displacement field in an SS form instruction.  */
00247 #define SS_D1 (SS_B1 + 1)
00248 #define SS_D1_MASK (0xfff)
00249   { 12, 0, 0, 0, I370_OPERAND_RELATIVE, "SS D1" },
00250 
00251  /* The B2 base register field in an SS form instruction.  */
00252 #define SS_B2 (SS_D1 + 1)
00253 #define SS_B2_MASK (0xf << 12)
00254   { 4, 12, insert_ss_b2, extract_ss_b2, I370_OPERAND_GPR | I370_OPERAND_BASE | I370_OPERAND_SBASE, "SS B2" },
00255 
00256   /* The D2 displacement field in an SS form instruction.  */
00257 #define SS_D2 (SS_B2 + 1)
00258 #define SS_D2_MASK (0xfff)
00259   { 12, 0, insert_ss_d2, extract_ss_d2, I370_OPERAND_RELATIVE, "SS D2" },
00260   
00261 };
00262 
00263 
00264 /* Macros used to form opcodes.  */
00265 
00266 /* The short-instruction opcode.  */
00267 #define OPS(x) ((((unsigned short) (x)) & 0xff) << 8)
00268 #define OPS_MASK OPS (0xff)
00269 
00270 /* the extended instruction opcode */
00271 #define XOPS(x) ((((unsigned short) (x)) & 0xff) << 24)
00272 #define XOPS_MASK XOPS (0xff)
00273 
00274 /* the S instruction opcode */
00275 #define SOPS(x) ((((unsigned short) (x)) & 0xffff) << 16)
00276 #define SOPS_MASK SOPS (0xffff)
00277 
00278 /* the E instruction opcode */
00279 #define EOPS(x) (((unsigned short) (x)) & 0xffff)
00280 #define EOPS_MASK EOPS (0xffff)
00281 
00282 /* the RI instruction opcode */
00283 #define ROPS(x) (((((unsigned short) (x)) & 0xff0) << 20) | \
00284                  ((((unsigned short) (x)) & 0x00f) << 16))
00285 #define ROPS_MASK ROPS (0xfff)
00286 
00287 
00288 /* An E form instruction.  */
00289 #define E(op)  (EOPS (op))
00290 #define E_MASK E (0xffff)
00291 
00292 /* An RR form instruction.  */
00293 #define RR(op, r1, r2) \
00294   (OPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) |   \
00295               ((((unsigned short) (r2)) & 0xf) ))
00296 
00297 #define RR_MASK RR (0xff, 0x0, 0x0)
00298 
00299 /* An SVC-style instruction.  */
00300 #define SVC(op, i) \
00301   (OPS (op) | (((unsigned short) (i)) & 0xff))
00302 
00303 #define SVC_MASK SVC (0xff, 0x0)
00304 
00305 /* An RRE form instruction.  */
00306 #define RRE(op, r1, r2) \
00307   (SOPS (op) | ((((unsigned short) (r1)) & 0xf) << 4) |   \
00308                ((((unsigned short) (r2)) & 0xf) ))
00309 
00310 #define RRE_MASK RRE (0xffff, 0x0, 0x0)
00311 
00312 /* An RRF form instruction.  */
00313 #define RRF(op, r3, r1, r2) \
00314   (SOPS (op) | ((((unsigned short) (r3)) & 0xf) << 12) |   \
00315                ((((unsigned short) (r1)) & 0xf) << 4)  |   \
00316                ((((unsigned short) (r2)) & 0xf) ))
00317 
00318 #define RRF_MASK RRF (0xffff, 0x0, 0x0, 0x0)
00319 
00320 /* An RX form instruction.  */
00321 #define RX(op, r1, x2, b2, d2) \
00322   (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
00323               ((((unsigned short) (x2)) & 0xf) << 16) |  \
00324               ((((unsigned short) (b2)) & 0xf) << 12) |  \
00325               ((((unsigned short) (d2)) & 0xfff)))
00326 
00327 #define RX_MASK RX (0xff, 0x0, 0x0, 0x0, 0x0)
00328 
00329 /* An RXE form instruction high word.  */
00330 #define RXEH(op, r1, x2, b2, d2) \
00331   (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
00332               ((((unsigned short) (x2)) & 0xf) << 16) |  \
00333               ((((unsigned short) (b2)) & 0xf) << 12) |  \
00334               ((((unsigned short) (d2)) & 0xfff)))
00335 
00336 #define RXEH_MASK RXEH (0xff, 0, 0, 0, 0)
00337 
00338 /* An RXE form instruction low word.  */
00339 #define RXEL(op) \
00340               ((((unsigned short) (op)) & 0xff) << 16 )
00341 
00342 #define RXEL_MASK RXEL (0xff)
00343 
00344 /* An RXF form instruction high word.  */
00345 #define RXFH(op, r1, x2, b2, d2) \
00346   (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
00347               ((((unsigned short) (x2)) & 0xf) << 16) |  \
00348               ((((unsigned short) (b2)) & 0xf) << 12) |  \
00349               ((((unsigned short) (d2)) & 0xfff)))
00350 
00351 #define RXFH_MASK RXFH (0xff, 0, 0, 0, 0)
00352 
00353 /* An RXF form instruction low word.  */
00354 #define RXFL(op, r3) \
00355               (((((unsigned short) (r3)) & 0xf)  << 28 ) | \
00356                ((((unsigned short) (op)) & 0xff) << 16 ))
00357 
00358 #define RXFL_MASK RXFL (0xff, 0)
00359 
00360 /* An RS form instruction.  */
00361 #define RS(op, r1, b3, b2, d2) \
00362   (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
00363               ((((unsigned short) (b3)) & 0xf) << 16) |  \
00364               ((((unsigned short) (b2)) & 0xf) << 12) |  \
00365               ((((unsigned short) (d2)) & 0xfff)))
00366 
00367 #define RS_MASK RS (0xff, 0x0, 0x0, 0x0, 0x0)
00368 
00369 /* An RSI form instruction.  */
00370 #define RSI(op, r1, r3, i2) \
00371   (XOPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
00372               ((((unsigned short) (r3)) & 0xf) << 16) |  \
00373               ((((unsigned short) (i2)) & 0xffff)))
00374 
00375 #define RSI_MASK RSI (0xff, 0x0, 0x0, 0x0)
00376 
00377 /* An RI form instruction.  */
00378 #define RI(op, r1, i2) \
00379   (ROPS(op) | ((((unsigned short) (r1)) & 0xf) << 20) |  \
00380               ((((unsigned short) (i2)) & 0xffff)))
00381 
00382 #define RI_MASK RI (0xfff, 0x0, 0x0)
00383 
00384 /* An SI form instruction.  */
00385 #define SI(op, i2, b1, d1) \
00386   (XOPS(op) | ((((unsigned short) (i2)) & 0xff) << 16) |  \
00387               ((((unsigned short) (b1)) & 0xf)  << 12) |  \
00388               ((((unsigned short) (d1)) & 0xfff)))
00389 
00390 #define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
00391 
00392 /* An S form instruction.  */
00393 #define S(op, b2, d2) \
00394   (SOPS(op) | ((((unsigned short)(b2)) & 0xf) << 12) |  \
00395               ((((unsigned short)(d2)) & 0xfff)))
00396 
00397 #define S_MASK S (0xffff, 0x0, 0x0)
00398 
00399 /* An SS form instruction high word.  */
00400 #define SSH(op, l, b1, d1) \
00401   (XOPS(op) | ((((unsigned short) (l)) & 0xff) << 16) |  \
00402               ((((unsigned short) (b1)) & 0xf)  << 12) |  \
00403               ((((unsigned short) (d1)) & 0xfff)))
00404 
00405 /* An SS form instruction low word.  */
00406 #define SSL(b2, d2) \
00407             ( ((((unsigned short) (b1)) & 0xf)   << 28) |  \
00408               ((((unsigned short) (d1)) & 0xfff) << 16 ))
00409 
00410 #define SS_MASK SSH (0xff, 0x0, 0x0, 0x0)
00411 
00412 /* An SSE form instruction high word.  */
00413 #define SSEH(op, b1, d1) \
00414   (SOPS(op) | ((((unsigned short) (b1)) & 0xf)  << 12) |  \
00415               ((((unsigned short) (d1)) & 0xfff)))
00416 
00417 /* An SSE form instruction low word.  */
00418 #define SSEL(b2, d2) \
00419             ( ((((unsigned short) (b1)) & 0xf)   << 28) |  \
00420               ((((unsigned short) (d1)) & 0xfff) << 16 ))
00421 
00422 #define SSE_MASK SSEH (0xffff, 0x0, 0x0)
00423 
00424 
00425 /* Smaller names for the flags so each entry in the opcodes table will
00426    fit on a single line.  These flags are set up so that e.g. IXA means
00427    the insn is supported on the 370/XA or newer architecture.
00428    Note that 370 or older obsolete insn's are not supported ...  */
00429 #define       IBF    I370_OPCODE_ESA390_BF
00430 #define       IBS    I370_OPCODE_ESA390_BS
00431 #define       ICK    I370_OPCODE_ESA390_CK
00432 #define       ICM    I370_OPCODE_ESA390_CM
00433 #define       IFX    I370_OPCODE_ESA390_FX
00434 #define       IHX    I370_OPCODE_ESA390_HX
00435 #define       IIR    I370_OPCODE_ESA390_IR
00436 #define       IMI    I370_OPCODE_ESA390_MI
00437 #define       IPC    I370_OPCODE_ESA390_PC
00438 #define       IPL    I370_OPCODE_ESA390_PL
00439 #define       IQR    I370_OPCODE_ESA390_QR
00440 #define       IRP    I370_OPCODE_ESA390_RP
00441 #define       ISA    I370_OPCODE_ESA390_SA
00442 #define       ISG    I370_OPCODE_ESA390_SG
00443 #define       ISR    I370_OPCODE_ESA390_SR
00444 #define       ITR    I370_OPCODE_ESA390_SR
00445 #define       I390   IBF  | IBS | ICK | ICM | IIR | IFX | IHX | IMI | IPC | IPL | IQR | IRP | ISA | ISG | ISR | ITR | I370_OPCODE_ESA390
00446 #define       IESA   I390 | I370_OPCODE_ESA370
00447 #define IXA   IESA | I370_OPCODE_370_XA
00448 #define       I370   IXA  | I370_OPCODE_370
00449 #define I360  I370 | I370_OPCODE_360
00450 
00451 
00452 /* The opcode table.
00453 
00454    The format of the opcode table is:
00455 
00456    NAME           LEN  OPCODE_HI  OPCODE_LO      MASK_HI MASK_LO      FLAGS         { OPERANDS }
00457 
00458    NAME is the name of the instruction.
00459    OPCODE is the instruction opcode.
00460    MASK is the opcode mask; this is used to tell the disassembler
00461      which bits in the actual opcode must match OPCODE.
00462    FLAGS are flags indicated what processors support the instruction.
00463    OPERANDS is the list of operands.
00464 
00465    The disassembler reads the table in order and prints the first
00466    instruction which matches, so this table is sorted to put more
00467    specific instructions before more general instructions.  It is also
00468    sorted by major opcode.  */
00469 
00470 const struct i370_opcode i370_opcodes[] =
00471 {
00472 /* E form instructions */
00473 { "pr",     2, {{E(0x0101),    0}}, {{E_MASK,  0}}, IESA,  {0} },
00474 
00475 { "trap2",  2, {{E(0x01FF),    0}}, {{E_MASK,  0}}, ITR,   {0} },
00476 { "upt",    2, {{E(0x0102),    0}}, {{E_MASK,  0}}, IXA,   {0} },
00477 
00478 /* RR form instructions */
00479 { "ar",     2, {{RR(0x1a,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00480 { "adr",    2, {{RR(0x2a,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00481 { "aer",    2, {{RR(0x3a,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00482 { "alr",    2, {{RR(0x1e,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00483 { "aur",    2, {{RR(0x2e,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00484 { "awr",    2, {{RR(0x3e,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00485 { "axr",    2, {{RR(0x36,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00486 { "balr",   2, {{RR(0x05,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00487 { "basr",   2, {{RR(0x0d,0,0), 0}}, {{RR_MASK, 0}}, IXA,   {RR_R1, RR_R2} },
00488 { "bassm",  2, {{RR(0x0c,0,0), 0}}, {{RR_MASK, 0}}, IXA,   {RR_R1, RR_R2} },
00489 { "bsm",    2, {{RR(0x0b,0,0), 0}}, {{RR_MASK, 0}}, IXA,   {RR_R1, RR_R2} },
00490 { "bcr",    2, {{RR(0x07,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00491 { "bctr",   2, {{RR(0x06,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00492 { "cdr",    2, {{RR(0x29,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00493 { "cer",    2, {{RR(0x39,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00494 { "clr",    2, {{RR(0x15,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00495 { "clcl",   2, {{RR(0x0f,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00496 { "cr",     2, {{RR(0x19,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00497 { "ddr",    2, {{RR(0x2d,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00498 { "der",    2, {{RR(0x3d,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00499 { "dr",     2, {{RR(0x1d,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00500 { "hdr",    2, {{RR(0x24,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00501 { "her",    2, {{RR(0x34,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00502 { "lcdr",   2, {{RR(0x23,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00503 { "lcer",   2, {{RR(0x33,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00504 { "lcr",    2, {{RR(0x13,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00505 { "ldr",    2, {{RR(0x28,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00506 { "ler",    2, {{RR(0x38,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00507 { "lndr",   2, {{RR(0x21,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00508 { "lner",   2, {{RR(0x31,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00509 { "lnr",    2, {{RR(0x11,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00510 { "lpdr",   2, {{RR(0x20,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00511 { "lper",   2, {{RR(0x30,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00512 { "lpr",    2, {{RR(0x10,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00513 { "lr",     2, {{RR(0x18,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00514 { "lrdr",   2, {{RR(0x25,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00515 { "lrer",   2, {{RR(0x35,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00516 { "ltdr",   2, {{RR(0x22,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00517 { "lter",   2, {{RR(0x32,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00518 { "ltr",    2, {{RR(0x12,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00519 { "mdr",    2, {{RR(0x2c,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00520 { "mer",    2, {{RR(0x3c,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00521 { "mr",     2, {{RR(0x1c,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00522 { "mvcl",   2, {{RR(0x0e,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00523 { "mxdr",   2, {{RR(0x27,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00524 { "mxr",    2, {{RR(0x26,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00525 { "nr",     2, {{RR(0x14,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00526 { "or",     2, {{RR(0x16,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00527 { "sdr",    2, {{RR(0x2b,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00528 { "ser",    2, {{RR(0x3b,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00529 { "slr",    2, {{RR(0x1f,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00530 { "spm",    2, {{RR(0x04,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1} },
00531 { "sr",     2, {{RR(0x1b,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00532 { "sur",    2, {{RR(0x3f,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00533 { "swr",    2, {{RR(0x2f,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00534 { "sxr",    2, {{RR(0x37,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00535 { "xr",     2, {{RR(0x17,0,0), 0}}, {{RR_MASK, 0}}, I370,  {RR_R1, RR_R2} },
00536 
00537 /* Unusual RR formats.  */
00538 { "svc",    2, {{SVC(0x0a,0), 0}},  {{SVC_MASK, 0}}, I370,  {RR_I} },
00539 
00540 /* RRE form instructions.  */
00541 { "adbr",   4, {{RRE(0xb31a,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00542 { "aebr",   4, {{RRE(0xb30a,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00543 { "axbr",   4, {{RRE(0xb34a,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00544 { "bakr",   4, {{RRE(0xb240,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00545 { "bsa",    4, {{RRE(0xb25a,0,0),   0}}, {{RRE_MASK, 0}}, IBS,  {RRE_R1, RRE_R2} },
00546 { "bsg",    4, {{RRE(0xb258,0,0),   0}}, {{RRE_MASK, 0}}, ISG,  {RRE_R1, RRE_R2} },
00547 { "cdbr",   4, {{RRE(0xb319,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00548 { "cdfbr",  4, {{RRE(0xb395,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00549 { "cdfr",   4, {{RRE(0xb3b5,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00550 { "cebr",   4, {{RRE(0xb309,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00551 { "cefbr",  4, {{RRE(0xb394,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00552 { "cefr",   4, {{RRE(0xb3b4,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00553 { "cksm",   4, {{RRE(0xb241,0,0),   0}}, {{RRE_MASK, 0}}, ICK,  {RRE_R1, RRE_R2} },
00554 { "clst",   4, {{RRE(0xb25d,0,0),   0}}, {{RRE_MASK, 0}}, ISR,  {RRE_R1, RRE_R2} },
00555 { "cpya",   4, {{RRE(0xb24d,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00556 { "cuse",   4, {{RRE(0xb257,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00557 { "cxbr",   4, {{RRE(0xb349,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00558 { "cxfbr",  4, {{RRE(0xb396,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00559 { "cxfr",   4, {{RRE(0xb3b6,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00560 { "cxr",    4, {{RRE(0xb369,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00561 { "ddbr",   4, {{RRE(0xb31d,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00562 { "debr",   4, {{RRE(0xb30d,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00563 { "dxbr",   4, {{RRE(0xb34d,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00564 { "dxr",    4, {{RRE(0xb22d,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00565 { "ear",    4, {{RRE(0xb24f,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00566 { "efpc",   4, {{RRE(0xb38c,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00567 { "epar",   4, {{RRE(0xb226,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1} },
00568 { "ereg",   4, {{RRE(0xb249,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00569 { "esar",   4, {{RRE(0xb227,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1} },
00570 { "esta",   4, {{RRE(0xb24a,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00571 { "fidr",   4, {{RRE(0xb37f,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00572 { "fier",   4, {{RRE(0xb377,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00573 { "fixr",   4, {{RRE(0xb367,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00574 { "iac",    4, {{RRE(0xb224,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1} },
00575 { "ipm",    4, {{RRE(0xb222,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1} },
00576 { "ipte",   4, {{RRE(0xb221,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00577 { "iske",   4, {{RRE(0xb229,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00578 { "ivsk",   4, {{RRE(0xb223,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00579 { "kdbr",   4, {{RRE(0xb318,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00580 { "kebr",   4, {{RRE(0xb308,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00581 { "kxbr",   4, {{RRE(0xb348,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00582 { "lcdbr",  4, {{RRE(0xb313,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00583 { "lcebr",  4, {{RRE(0xb303,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00584 { "lcxbr",  4, {{RRE(0xb343,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00585 { "lcxr",   4, {{RRE(0xb363,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00586 { "lder",   4, {{RRE(0xb324,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00587 { "ldxbr",  4, {{RRE(0xb345,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00588 { "ledbr",  4, {{RRE(0xb344,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00589 { "lexbr",  4, {{RRE(0xb346,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00590 { "lexr",   4, {{RRE(0xb366,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00591 { "lndbr",  4, {{RRE(0xb311,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00592 { "lnebr",  4, {{RRE(0xb301,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00593 { "lnxbr",  4, {{RRE(0xb341,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00594 { "lnxr",   4, {{RRE(0xb361,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00595 { "lpdbr",  4, {{RRE(0xb310,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00596 { "lpebr",  4, {{RRE(0xb300,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00597 { "lpxbr",  4, {{RRE(0xb340,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00598 { "lpxr",   4, {{RRE(0xb360,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00599 { "ltdbr",  4, {{RRE(0xb312,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00600 { "ltebr",  4, {{RRE(0xb302,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00601 { "ltxbr",  4, {{RRE(0xb342,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00602 { "ltxr",   4, {{RRE(0xb362,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00603 { "lura",   4, {{RRE(0xb24b,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00604 { "lxdr",   4, {{RRE(0xb325,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00605 { "lxer",   4, {{RRE(0xb326,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00606 { "lxr",    4, {{RRE(0xb365,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
00607 { "lzdr",   4, {{RRE(0xb375,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
00608 { "lzer",   4, {{RRE(0xb374,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
00609 { "lzxr",   4, {{RRE(0xb376,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
00610 { "mdbr",   4, {{RRE(0xb31c,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00611 { "mdebr",  4, {{RRE(0xb30c,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00612 { "meebr",  4, {{RRE(0xb317,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00613 { "meer",   4, {{RRE(0xb337,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00614 { "msr",    4, {{RRE(0xb252,0,0),   0}}, {{RRE_MASK, 0}}, IIR,  {RRE_R1, RRE_R2} },
00615 { "msta",   4, {{RRE(0xb247,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1} },
00616 { "mvpg",   4, {{RRE(0xb254,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00617 { "mvst",   4, {{RRE(0xb255,0,0),   0}}, {{RRE_MASK, 0}}, ISR,  {RRE_R1, RRE_R2} },
00618 { "mxbr",   4, {{RRE(0xb34c,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00619 { "mxdbr",  4, {{RRE(0xb307,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00620 { "palb",   4, {{RRE(0xb248,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {0} },
00621 { "prbe",   4, {{RRE(0xb22a,0,0),   0}}, {{RRE_MASK, 0}}, I370, {RRE_R1, RRE_R2} },
00622 { "pt",     4, {{RRE(0xb228,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00623 { "rrbe",   4, {{RRE(0xb22a,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00624 { "sar",    4, {{RRE(0xb24e,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00625 { "sdbr",   4, {{RRE(0xb31b,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00626 { "sebr",   4, {{RRE(0xb30b,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00627 { "servc",  4, {{RRE(0xb220,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00628 { "sfpc",   4, {{RRE(0xb384,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00629 { "sqdbr",  4, {{RRE(0xb315,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00630 { "sqdr",   4, {{RRE(0xb244,0,0),   0}}, {{RRE_MASK, 0}}, IQR,  {RRE_R1, RRE_R2} },
00631 { "sqebr",  4, {{RRE(0xb314,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00632 { "sqer",   4, {{RRE(0xb245,0,0),   0}}, {{RRE_MASK, 0}}, IQR,  {RRE_R1, RRE_R2} },
00633 { "sqxbr",  4, {{RRE(0xb316,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00634 { "sqxr",   4, {{RRE(0xb336,0,0),   0}}, {{RRE_MASK, 0}}, IHX,  {RRE_R1, RRE_R2} },
00635 { "srst",   4, {{RRE(0xb25e,0,0),   0}}, {{RRE_MASK, 0}}, ISR,  {RRE_R1, RRE_R2} },
00636 { "ssar",   4, {{RRE(0xb225,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1} },
00637 { "sske",   4, {{RRE(0xb22b,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00638 { "stura",  4, {{RRE(0xb246,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00639 { "sxbr",   4, {{RRE(0xb34b,0,0),   0}}, {{RRE_MASK, 0}}, IBF,  {RRE_R1, RRE_R2} },
00640 { "tar",    4, {{RRE(0xb24c,0,0),   0}}, {{RRE_MASK, 0}}, IESA, {RRE_R1, RRE_R2} },
00641 { "tb",     4, {{RRE(0xb22c,0,0),   0}}, {{RRE_MASK, 0}}, IXA,  {RRE_R1, RRE_R2} },
00642 { "thdr",   4, {{RRE(0xb359,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
00643 { "thder",  4, {{RRE(0xb359,0,0),   0}}, {{RRE_MASK, 0}}, IFX,  {RRE_R1, RRE_R2} },
00644 
00645 /* RRF form instructions.  */
00646 { "cfdbr",  4, {{RRF(0xb399,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00647 { "cfdr",   4, {{RRF(0xb3b9,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX,  {RRF_R1, RRF_R3, RRF_R2} },
00648 { "cfebr",  4, {{RRF(0xb398,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00649 { "cfer",   4, {{RRF(0xb3b8,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX,  {RRF_R1, RRF_R3, RRF_R2} },
00650 { "cfxbr",  4, {{RRF(0xb39a,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00651 { "cfxr",   4, {{RRF(0xb3ba,0,0,0), 0}}, {{RRF_MASK, 0}}, IHX,  {RRF_R1, RRF_R3, RRF_R2} },
00652 { "didbr",  4, {{RRF(0xb35b,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00653 { "diebr",  4, {{RRF(0xb353,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00654 { "fidbr",  4, {{RRF(0xb35f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00655 { "fiebr",  4, {{RRF(0xb357,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00656 { "fixbr",  4, {{RRF(0xb347,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00657 { "madbr",  4, {{RRF(0xb31e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00658 { "maebr",  4, {{RRF(0xb30e,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00659 { "msdbr",  4, {{RRF(0xb31f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00660 { "msebr",  4, {{RRF(0xb30f,0,0,0), 0}}, {{RRF_MASK, 0}}, IBF,  {RRF_R1, RRF_R3, RRF_R2} },
00661 { "tbdr",   4, {{RRF(0xb351,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX,  {RRF_R1, RRF_R3, RRF_R2} },
00662 { "tbedr",  4, {{RRF(0xb350,0,0,0), 0}}, {{RRF_MASK, 0}}, IFX,  {RRF_R1, RRF_R3, RRF_R2} },
00663 
00664 /* RX form instructions.  */
00665 { "a",      4, {{RX(0x5a,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00666 { "ad",     4, {{RX(0x6a,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00667 { "ae",     4, {{RX(0x7a,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00668 { "ah",     4, {{RX(0x4a,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00669 { "al",     4, {{RX(0x5e,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00670 { "au",     4, {{RX(0x7e,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00671 { "aw",     4, {{RX(0x6e,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00672 { "bal",    4, {{RX(0x45,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00673 { "bas",    4, {{RX(0x4d,0,0,0,0),  0}}, {{RX_MASK,  0}}, IXA,  {RX_R1, RX_D2, RX_X2, RX_B2} },
00674 { "bc",     4, {{RX(0x47,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00675 { "bct",    4, {{RX(0x46,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00676 { "c",      4, {{RX(0x59,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00677 { "cd",     4, {{RX(0x69,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00678 { "ce",     4, {{RX(0x79,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00679 { "ch",     4, {{RX(0x49,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00680 { "cl",     4, {{RX(0x55,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00681 { "cvb",    4, {{RX(0x4f,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00682 { "cvd",    4, {{RX(0x4e,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00683 { "d",      4, {{RX(0x5d,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00684 { "dd",     4, {{RX(0x6d,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00685 { "de",     4, {{RX(0x7d,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00686 { "ex",     4, {{RX(0x44,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00687 { "ic",     4, {{RX(0x43,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00688 { "l",      4, {{RX(0x58,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00689 { "la",     4, {{RX(0x41,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00690 { "lae",    4, {{RX(0x51,0,0,0,0),  0}}, {{RX_MASK,  0}}, IESA, {RX_R1, RX_D2, RX_X2, RX_B2} },
00691 { "ld",     4, {{RX(0x68,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00692 { "le",     4, {{RX(0x78,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00693 { "lh",     4, {{RX(0x48,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00694 { "lra",    4, {{RX(0xb1,0,0,0,0),  0}}, {{RX_MASK,  0}}, IXA,  {RX_R1, RX_D2, RX_X2, RX_B2} },
00695 { "m",      4, {{RX(0x5c,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00696 { "md",     4, {{RX(0x6c,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00697 { "me",     4, {{RX(0x7c,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00698 { "mh",     4, {{RX(0x4c,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00699 { "ms",     4, {{RX(0x71,0,0,0,0),  0}}, {{RX_MASK,  0}}, IIR,  {RX_R1, RX_D2, RX_X2, RX_B2} },
00700 { "mxd",    4, {{RX(0x67,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00701 { "n",      4, {{RX(0x54,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00702 { "o",      4, {{RX(0x56,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00703 { "s",      4, {{RX(0x5b,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00704 { "sd",     4, {{RX(0x6b,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00705 { "se",     4, {{RX(0x7b,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00706 { "sh",     4, {{RX(0x4b,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00707 { "sl",     4, {{RX(0x5f,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00708 { "st",     4, {{RX(0x50,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00709 { "stc",    4, {{RX(0x42,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00710 { "std",    4, {{RX(0x60,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00711 { "ste",    4, {{RX(0x70,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00712 { "sth",    4, {{RX(0x40,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00713 { "su",     4, {{RX(0x7f,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00714 { "sw",     4, {{RX(0x6f,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00715 { "x",      4, {{RX(0x57,0,0,0,0),  0}}, {{RX_MASK,  0}}, I370, {RX_R1, RX_D2, RX_X2, RX_B2} },
00716 
00717 /* RXE form instructions.  */
00718 { "adb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x1a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00719 { "aeb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x0a)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00720 { "cdb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x19)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00721 { "ceb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x09)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00722 { "ddb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x1d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00723 { "deb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x0d)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00724 { "kdb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x18)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00725 { "keb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x08)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00726 { "lde",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x24)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00727 { "ldeb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x04)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00728 { "lxd",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x25)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00729 { "lxdb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x05)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00730 { "lxe",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x26)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00731 { "lxeb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x06)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00732 { "mdb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x1c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00733 { "mdeb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x0c)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00734 { "mee",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x37)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
00735 { "meeb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x17)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00736 { "mxdb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x07)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00737 { "sqd",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x35)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
00738 { "sqdb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x15)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00739 { "sqe",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x34)}}, {{RXEH_MASK, RXEL_MASK}}, IHX, {RX_R1, RX_D2, RX_X2, RX_B2} },
00740 { "sqeb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x14)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00741 { "sdb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x1b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00742 { "seb",    6, {{RXEH(0xed,0,0,0,0), RXEL(0x0b)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00743 { "tcdb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x11)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00744 { "tceb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x10)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00745 { "tcxb",   6, {{RXEH(0xed,0,0,0,0), RXEL(0x12)}}, {{RXEH_MASK, RXEL_MASK}}, IBF, {RX_R1, RX_D2, RX_X2, RX_B2} },
00746 
00747 /* RXF form instructions.  */
00748 { "madb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x1e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
00749 { "maeb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x0e,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
00750 { "msdb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x1f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
00751 { "mseb",   6, {{RXFH(0xed,0,0,0,0), RXFL(0x0f,0)}}, {{RXFH_MASK, RXFL_MASK}}, IBF, {RX_R1, RXF_R3, RX_D2, RX_X2, RX_B2} },
00752 
00753 /* RS form instructions.  */
00754 { "bxh",    4, {{RS(0x86,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00755 { "bxle",   4, {{RS(0x87,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00756 { "cds",    4, {{RS(0xbb,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
00757 { "clcle",  4, {{RS(0xa9,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM,  {RX_R1, RS_R3, RS_D2, RS_B2} },
00758 { "clm",    4, {{RS(0xbd,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00759 { "cs",     4, {{RS(0xba,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
00760 { "icm",    4, {{RS(0xbf,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00761 { "lam",    4, {{RS(0x9a,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
00762 { "lctl",   4, {{RS(0xb7,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00763 { "lm",     4, {{RS(0x98,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00764 { "mvcle",  4, {{RS(0xa8,0,0,0,0), 0}}, {{RS_MASK, 0}}, ICM,  {RX_R1, RS_R3, RS_D2, RS_B2} },
00765 { "sigp",   4, {{RS(0xae,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
00766 { "stam",   4, {{RS(0x9b,0,0,0,0), 0}}, {{RS_MASK, 0}}, IESA, {RX_R1, RS_R3, RS_D2, RS_B2} },
00767 { "stcm",   4, {{RS(0xbe,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00768 { "stctl",  4, {{RS(0xb6,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00769 { "stm",    4, {{RS(0x90,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_R3, RS_D2, RS_B2} },
00770 { "trace",  4, {{RS(0x99,0,0,0,0), 0}}, {{RS_MASK, 0}}, IXA,  {RX_R1, RS_R3, RS_D2, RS_B2} },
00771 
00772 /* RS form instructions with blank R3 and optional B2 (shift left/right).  */
00773 { "sla",    4, {{RS(0x8b,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00774 { "slda",   4, {{RS(0x8f,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00775 { "sldl",   4, {{RS(0x8d,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00776 { "sll",    4, {{RS(0x89,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00777 { "sra",    4, {{RS(0x8a,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00778 { "srda",   4, {{RS(0x8e,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00779 { "srdl",   4, {{RS(0x8c,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00780 { "srl",    4, {{RS(0x88,0,0,0,0), 0}}, {{RS_MASK, 0}}, I370, {RX_R1, RS_D2, RS_B2_OPT} },
00781 
00782 /* RSI form instructions.  */
00783 { "brxh",   4, {{RSI(0x84,0,0,0),  0}}, {{RSI_MASK, 0}}, IIR,  {RSI_R1, RSI_R3, RSI_I2} },
00784 { "brxle",  4, {{RSI(0x85,0,0,0),  0}}, {{RSI_MASK, 0}}, IIR,  {RSI_R1, RSI_R3, RSI_I2} },
00785 
00786 /* RI form instructions.  */
00787 { "ahi",    4, {{RI(0xa7a,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00788 { "bras",   4, {{RI(0xa75,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00789 { "brc",    4, {{RI(0xa74,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00790 { "brct",   4, {{RI(0xa76,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00791 { "chi",    4, {{RI(0xa7e,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00792 { "lhi",    4, {{RI(0xa78,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00793 { "mhi",    4, {{RI(0xa7c,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00794 { "tmh",    4, {{RI(0xa70,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00795 { "tml",    4, {{RI(0xa71,0,0),    0}}, {{RI_MASK,  0}}, IIR,  {RI_R1, RI_I2} },
00796 
00797 /* SI form instructions.  */
00798 { "cli",    4, {{SI(0x95,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
00799 { "mc",     4, {{SI(0xaf,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
00800 { "mvi",    4, {{SI(0x92,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
00801 { "ni",     4, {{SI(0x94,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
00802 { "oi",     4, {{SI(0x96,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
00803 { "stnsm",  4, {{SI(0xac,0,0,0),   0}}, {{SI_MASK,  0}}, IXA,  {SI_D1, SI_B1, SI_I2} },
00804 { "stosm",  4, {{SI(0xad,0,0,0),   0}}, {{SI_MASK,  0}}, IXA,  {SI_D1, SI_B1, SI_I2} },
00805 { "tm",     4, {{SI(0x91,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
00806 { "xi",     4, {{SI(0x97,0,0,0),   0}}, {{SI_MASK,  0}}, I370, {SI_D1, SI_B1, SI_I2} },
00807 
00808 /* S form instructions.  */
00809 { "cfc",    4, {{S(0xb21a,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00810 { "csch",   4, {{S(0xb230,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00811 { "hsch",   4, {{S(0xb231,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00812 { "ipk",    4, {{S(0xb20b,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00813 { "lfpc",   4, {{S(0xb29d,0,0),    0}}, {{S_MASK,        0}}, IBF,  {S_D2, S_B2} },
00814 { "lpsw",   4, {{S(0x8200,0,0),    0}}, {{S_MASK,        0}}, I370, {S_D2, S_B2} },
00815 { "msch",   4, {{S(0xb232,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00816 { "pc",     4, {{S(0xb218,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00817 { "pcf",    4, {{S(0xb218,0,0),    0}}, {{S_MASK,        0}}, IPC,  {S_D2, S_B2} },
00818 { "ptlb",   4, {{S(0xb20d,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00819 { "rchp",   4, {{S(0xb23b,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00820 { "rp",     4, {{S(0xb277,0,0),    0}}, {{S_MASK,        0}}, IRP,  {0} },
00821 { "rsch",   4, {{S(0xb238,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00822 { "sac",    4, {{S(0xb219,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00823 { "sacf",   4, {{S(0xb279,0,0),    0}}, {{S_MASK,        0}}, ISA,  {S_D2, S_B2} },
00824 { "sal",    4, {{S(0xb237,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00825 { "schm",   4, {{S(0xb23c,0,0),    0}}, {{S_MASK,        0}}, IXA,  {0} },
00826 { "sck",    4, {{S(0xb204,0,0),    0}}, {{S_MASK,        0}}, I370, {S_D2, S_B2} },
00827 { "sckc",   4, {{S(0xb206,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00828 { "spka",   4, {{S(0xb20a,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00829 { "spt",    4, {{S(0xb208,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00830 { "spx",    4, {{S(0xb210,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00831 { "srnm",   4, {{S(0xb299,0,0),    0}}, {{S_MASK,        0}}, IBF,  {S_D2, S_B2} },
00832 { "ssch",   4, {{S(0xb233,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00833 { "ssm",    4, {{S(0x8000,0,0),    0}}, {{S_MASK,        0}}, I370, {S_D2, S_B2} },
00834 { "stap",   4, {{S(0xb212,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00835 { "stck",   4, {{S(0xb205,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00836 { "stckc",  4, {{S(0xb207,0,0),    0}}, {{S_MASK,        0}}, I370, {S_D2, S_B2} },
00837 { "stcps",  4, {{S(0xb23a,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00838 { "stcrw",  4, {{S(0xb239,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00839 { "stfpc",  4, {{S(0xb29c,0,0),    0}}, {{S_MASK,        0}}, IBF,  {S_D2, S_B2} },
00840 { "stidp",  4, {{S(0xb202,0,0),    0}}, {{S_MASK,        0}}, I370, {S_D2, S_B2} },
00841 { "stpt",   4, {{S(0xb209,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00842 { "stpx",   4, {{S(0xb211,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00843 { "stsch",  4, {{S(0xb234,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00844 { "tpi",    4, {{S(0xb236,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00845 { "trap4",  4, {{S(0xb2ff,0,0),    0}}, {{S_MASK,        0}}, ITR,  {S_D2, S_B2} },
00846 { "ts",     4, {{S(0x9300,0,0),    0}}, {{S_MASK,        0}}, I370, {S_D2, S_B2} },
00847 { "tsch",   4, {{S(0xb235,0,0),    0}}, {{S_MASK,        0}}, IXA,  {S_D2, S_B2} },
00848 
00849 /* SS form instructions.  */
00850 { "ap",     6, {{SSH(0xfa,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00851 { "clc",    6, {{SSH(0xd5,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00852 { "cp",     6, {{SSH(0xf9,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00853 { "dp",     6, {{SSH(0xfd,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00854 { "ed",     6, {{SSH(0xde,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00855 { "edmk",   6, {{SSH(0xdf,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00856 { "mvc",    6, {{SSH(0xd2,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00857 { "mvcin",  6, {{SSH(0xe8,0,0,0),  0}}, {{SS_MASK,  0}}, IMI,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00858 { "mvck",   6, {{SSH(0xd9,0,0,0),  0}}, {{SS_MASK,  0}}, IXA,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00859 { "mvcp",   6, {{SSH(0xda,0,0,0),  0}}, {{SS_MASK,  0}}, IXA,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00860 { "mvcs",   6, {{SSH(0xdb,0,0,0),  0}}, {{SS_MASK,  0}}, IXA,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00861 { "mvn",    6, {{SSH(0xd1,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00862 { "mvo",    6, {{SSH(0xf1,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00863 { "mvz",    6, {{SSH(0xd3,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00864 { "nc",     6, {{SSH(0xd4,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00865 { "oc",     6, {{SSH(0xd6,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00866 { "pack",   6, {{SSH(0xf2,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00867 { "plo",    6, {{SSH(0xee,0,0,0),  0}}, {{SS_MASK,  0}}, IPL,  {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00868 { "sp",     6, {{SSH(0xfb,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00869 { "srp",    6, {{SSH(0xf0,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00870 { "tr",     6, {{SSH(0xdc,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00871 { "trt",    6, {{SSH(0xdd,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00872 { "unpk",   6, {{SSH(0xf3,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00873 { "xc",     6, {{SSH(0xd7,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00874 { "zap",    6, {{SSH(0xf8,0,0,0),  0}}, {{SS_MASK,  0}}, I370, {SS_D1,SS_L,SS_B1,SS_D2,SS_B2} },
00875 
00876 /* SSE form instructions.  */
00877 { "lasp",   6, {{SSEH(0xe500,0,0), 0}}, {{SSE_MASK, 0}}, IXA,  {SS_D1, SS_B1, SS_D2, SS_B2} },
00878 { "mvcdk",  6, {{SSEH(0xe50f,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
00879 { "mvcsk",  6, {{SSEH(0xe50e,0,0), 0}}, {{SSE_MASK, 0}}, IESA, {SS_D1, SS_B1, SS_D2, SS_B2} },
00880 { "tprot",  6, {{SSEH(0xe501,0,0), 0}}, {{SSE_MASK, 0}}, IXA,  {SS_D1, SS_B1, SS_D2, SS_B2} },
00881 
00882 /* */
00883 };
00884 
00885 const int i370_num_opcodes =
00886   sizeof (i370_opcodes) / sizeof (i370_opcodes[0]);
00887 
00888 /* The macro table.  This is only used by the assembler.  */
00889 
00890 const struct i370_macro i370_macros[] =
00891 {
00892 { "b",     1,   I370,       "bc  15,%0" },
00893 { "br",    1,   I370,       "bcr 15,%0" },
00894 
00895 { "nop",   1,   I370,       "bc  0,%0" },
00896 { "nopr",  1,   I370,       "bcr 0,%0" },
00897 
00898 { "bh",    1,   I370,       "bc  2,%0" },
00899 { "bhr",   1,   I370,       "bcr 2,%0" },
00900 { "bl",    1,   I370,       "bc  4,%0" },
00901 { "blr",   1,   I370,       "bcr 4,%0" },
00902 { "be",    1,   I370,       "bc  8,%0" },
00903 { "ber",   1,   I370,       "bcr 8,%0" },
00904 
00905 { "bnh",    1,   I370,      "bc  13,%0" },
00906 { "bnhr",   1,   I370,      "bcr 13,%0" },
00907 { "bnl",    1,   I370,      "bc  11,%0" },
00908 { "bnlr",   1,   I370,      "bcr 11,%0" },
00909 { "bne",    1,   I370,      "bc  7,%0" },
00910 { "bner",   1,   I370,      "bcr 7,%0" },
00911 
00912 { "bp",    1,   I370,       "bc  2,%0" },
00913 { "bpr",   1,   I370,       "bcr 2,%0" },
00914 { "bm",    1,   I370,       "bc  4,%0" },
00915 { "bmr",   1,   I370,       "bcr 4,%0" },
00916 { "bz",    1,   I370,       "bc  8,%0" },
00917 { "bzr",   1,   I370,       "bcr 8,%0" },
00918 { "bo",    1,   I370,       "bc  1,%0" },
00919 { "bor",   1,   I370,       "bcr 1,%0" },
00920 
00921 { "bnp",    1,   I370,      "bc  13,%0" },
00922 { "bnpr",   1,   I370,      "bcr 13,%0" },
00923 { "bnm",    1,   I370,      "bc  11,%0" },
00924 { "bnmr",   1,   I370,      "bcr 11,%0" },
00925 { "bnz",    1,   I370,      "bc  7,%0" },
00926 { "bnzr",   1,   I370,      "bcr 7,%0" },
00927 { "bno",    1,   I370,      "bc  14,%0" },
00928 { "bnor",   1,   I370,      "bcr 14,%0" },
00929 
00930 { "sync",   0,   I370,      "bcr 15,0" },
00931 
00932 };
00933 
00934 const int i370_num_macros =
00935   sizeof (i370_macros) / sizeof (i370_macros[0]);