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cell-binutils  2.17cvs20070401
Defines | Typedefs | Enumerations | Variables
frv-desc.h File Reference
#include "opcode/cgen-bitset.h"
#include "opcode/cgen.h"
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Defines

#define CGEN_ARCH   frv
#define CGEN_SYM(s)   frv_cgen_s
#define HAVE_CPU_FRVBF
#define CGEN_INSN_LSB0_P   1
#define CGEN_MIN_INSN_SIZE   4
#define CGEN_MAX_INSN_SIZE   4
#define CGEN_INT_INSN_P   1
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS   22
#define CGEN_MNEMONIC_OPERANDS
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS   10
#define MAX_ISAS   1
#define MAX_MACHS   ((int) MACH_MAX)
#define CGEN_IFLD_NBOOL_ATTRS   (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
#define MAX_IFLD   ((int) FRV_F_MAX)
#define CGEN_HW_NBOOL_ATTRS   (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
#define MAX_HW   ((int) HW_MAX)
#define CGEN_OPERAND_NBOOL_ATTRS   (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
#define MAX_OPERANDS   89
#define MAX_OPERAND_INSTANCES   8
#define CGEN_INSN_NBOOL_ATTRS   (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_UNIT_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_UNIT-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_FR400_MAJOR_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_FR400_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_FR450_MAJOR_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_FR450_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_FR500_MAJOR_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_FR500_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_FR550_MAJOR_VALUE(attrs)   ((attrs)->nonbool[CGEN_INSN_FR550_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
#define CGEN_ATTR_CGEN_INSN_PRIVILEGED_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_PRIVILEGED)) != 0)
#define CGEN_ATTR_CGEN_INSN_NON_EXCEPTING_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_NON_EXCEPTING)) != 0)
#define CGEN_ATTR_CGEN_INSN_CONDITIONAL_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_CONDITIONAL)) != 0)
#define CGEN_ATTR_CGEN_INSN_FR_ACCESS_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_FR_ACCESS)) != 0)
#define CGEN_ATTR_CGEN_INSN_PRESERVE_OVF_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_PRESERVE_OVF)) != 0)
#define CGEN_ATTR_CGEN_INSN_AUDIO_VALUE(attrs)   (((attrs)->bool & (1 << CGEN_INSN_AUDIO)) != 0)

Typedefs

typedef enum insn_op INSN_OP
typedef enum insn_ope1 INSN_OPE1
typedef enum insn_ope2 INSN_OPE2
typedef enum insn_ope3 INSN_OPE3
typedef enum insn_ope4 INSN_OPE4
typedef enum int_cc INT_CC
typedef enum flt_cc FLT_CC
typedef enum gr_names GR_NAMES
typedef enum fr_names FR_NAMES
typedef enum cpr_names CPR_NAMES
typedef enum spr_names SPR_NAMES
typedef enum accg_names ACCG_NAMES
typedef enum acc_names ACC_NAMES
typedef enum iacc0_names IACC0_NAMES
typedef enum iccr_names ICCR_NAMES
typedef enum fccr_names FCCR_NAMES
typedef enum cccr_names CCCR_NAMES
typedef enum mach_attr MACH_ATTR
typedef enum isa_attr ISA_ATTR
typedef enum unit_attr UNIT_ATTR
typedef enum fr400_major_attr FR400_MAJOR_ATTR
typedef enum fr450_major_attr FR450_MAJOR_ATTR
typedef enum fr500_major_attr FR500_MAJOR_ATTR
typedef enum fr550_major_attr FR550_MAJOR_ATTR
typedef enum cgen_ifld_attr CGEN_IFLD_ATTR
typedef enum ifield_type IFIELD_TYPE
typedef enum cgen_hw_attr CGEN_HW_ATTR
typedef enum cgen_hw_type CGEN_HW_TYPE
typedef enum cgen_operand_attr CGEN_OPERAND_ATTR
typedef enum cgen_operand_type CGEN_OPERAND_TYPE
typedef enum cgen_insn_attr CGEN_INSN_ATTR

Enumerations

enum  insn_op {
  OP_00, OP_01, OP_02, OP_03,
  OP_04, OP_05, OP_06, OP_07,
  OP_08, OP_09, OP_0A, OP_0B,
  OP_0C, OP_0D, OP_0E, OP_0F,
  OP_10, OP_11, OP_12, OP_13,
  OP_14, OP_15, OP_16, OP_17,
  OP_18, OP_19, OP_1A, OP_1B,
  OP_1C, OP_1D, OP_1E, OP_1F,
  OP_20, OP_21, OP_22, OP_23,
  OP_24, OP_25, OP_26, OP_27,
  OP_28, OP_29, OP_2A, OP_2B,
  OP_2C, OP_2D, OP_2E, OP_2F,
  OP_30, OP_31, OP_32, OP_33,
  OP_34, OP_35, OP_36, OP_37,
  OP_38, OP_39, OP_3A, OP_3B,
  OP_3C, OP_3D, OP_3E, OP_3F,
  OP_40, OP_41, OP_42, OP_43,
  OP_44, OP_45, OP_46, OP_47,
  OP_48, OP_49, OP_4A, OP_4B,
  OP_4C, OP_4D, OP_4E, OP_4F,
  OP_50, OP_51, OP_52, OP_53,
  OP_54, OP_55, OP_56, OP_57,
  OP_58, OP_59, OP_5A, OP_5B,
  OP_5C, OP_5D, OP_5E, OP_5F,
  OP_60, OP_61, OP_62, OP_63,
  OP_64, OP_65, OP_66, OP_67,
  OP_68, OP_69, OP_6A, OP_6B,
  OP_6C, OP_6D, OP_6E, OP_6F,
  OP_70, OP_71, OP_72, OP_73,
  OP_74, OP_75, OP_76, OP_77,
  OP_78, OP_79, OP_7A, OP_7B,
  OP_7C, OP_7D, OP_7E, OP_7F
}
enum  insn_ope1 {
  OPE1_00, OPE1_01, OPE1_02, OPE1_03,
  OPE1_04, OPE1_05, OPE1_06, OPE1_07,
  OPE1_08, OPE1_09, OPE1_0A, OPE1_0B,
  OPE1_0C, OPE1_0D, OPE1_0E, OPE1_0F,
  OPE1_10, OPE1_11, OPE1_12, OPE1_13,
  OPE1_14, OPE1_15, OPE1_16, OPE1_17,
  OPE1_18, OPE1_19, OPE1_1A, OPE1_1B,
  OPE1_1C, OPE1_1D, OPE1_1E, OPE1_1F,
  OPE1_20, OPE1_21, OPE1_22, OPE1_23,
  OPE1_24, OPE1_25, OPE1_26, OPE1_27,
  OPE1_28, OPE1_29, OPE1_2A, OPE1_2B,
  OPE1_2C, OPE1_2D, OPE1_2E, OPE1_2F,
  OPE1_30, OPE1_31, OPE1_32, OPE1_33,
  OPE1_34, OPE1_35, OPE1_36, OPE1_37,
  OPE1_38, OPE1_39, OPE1_3A, OPE1_3B,
  OPE1_3C, OPE1_3D, OPE1_3E, OPE1_3F
}
enum  insn_ope2 {
  OPE2_00, OPE2_01, OPE2_02, OPE2_03,
  OPE2_04, OPE2_05, OPE2_06, OPE2_07,
  OPE2_08, OPE2_09, OPE2_0A, OPE2_0B,
  OPE2_0C, OPE2_0D, OPE2_0E, OPE2_0F
}
enum  insn_ope3 {
  OPE3_00, OPE3_01, OPE3_02, OPE3_03,
  OPE3_04, OPE3_05, OPE3_06, OPE3_07
}
enum  insn_ope4 { OPE4_0, OPE4_1, OPE4_2, OPE4_3 }
enum  int_cc {
  ICC_NEV, ICC_C, ICC_V, ICC_LT,
  ICC_EQ, ICC_LS, ICC_N, ICC_LE,
  ICC_RA, ICC_NC, ICC_NV, ICC_GE,
  ICC_NE, ICC_HI, ICC_P, ICC_GT
}
enum  flt_cc {
  FCC_NEV, FCC_U, FCC_GT, FCC_UG,
  FCC_LT, FCC_UL, FCC_LG, FCC_NE,
  FCC_EQ, FCC_UE, FCC_GE, FCC_UGE,
  FCC_LE, FCC_ULE, FCC_O, FCC_RA
}
enum  gr_names {
  H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3,
  H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7,
  H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11,
  H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15,
  H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15, H_GR_SP = 1,
  H_GR_FP = 2, H_GR_GR0 = 0, H_GR_GR1 = 1, H_GR_GR2 = 2,
  H_GR_GR3 = 3, H_GR_GR4 = 4, H_GR_GR5 = 5, H_GR_GR6 = 6,
  H_GR_GR7 = 7, H_GR_GR8 = 8, H_GR_GR9 = 9, H_GR_GR10 = 10,
  H_GR_GR11 = 11, H_GR_GR12 = 12, H_GR_GR13 = 13, H_GR_GR14 = 14,
  H_GR_GR15 = 15, H_GR_GR16 = 16, H_GR_GR17 = 17, H_GR_GR18 = 18,
  H_GR_GR19 = 19, H_GR_GR20 = 20, H_GR_GR21 = 21, H_GR_GR22 = 22,
  H_GR_GR23 = 23, H_GR_GR24 = 24, H_GR_GR25 = 25, H_GR_GR26 = 26,
  H_GR_GR27 = 27, H_GR_GR28 = 28, H_GR_GR29 = 29, H_GR_GR30 = 30,
  H_GR_GR31 = 31, H_GR_GR32 = 32, H_GR_GR33 = 33, H_GR_GR34 = 34,
  H_GR_GR35 = 35, H_GR_GR36 = 36, H_GR_GR37 = 37, H_GR_GR38 = 38,
  H_GR_GR39 = 39, H_GR_GR40 = 40, H_GR_GR41 = 41, H_GR_GR42 = 42,
  H_GR_GR43 = 43, H_GR_GR44 = 44, H_GR_GR45 = 45, H_GR_GR46 = 46,
  H_GR_GR47 = 47, H_GR_GR48 = 48, H_GR_GR49 = 49, H_GR_GR50 = 50,
  H_GR_GR51 = 51, H_GR_GR52 = 52, H_GR_GR53 = 53, H_GR_GR54 = 54,
  H_GR_GR55 = 55, H_GR_GR56 = 56, H_GR_GR57 = 57, H_GR_GR58 = 58,
  H_GR_GR59 = 59, H_GR_GR60 = 60, H_GR_GR61 = 61, H_GR_GR62 = 62,
  H_GR_GR63 = 63, H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1,
  H_GR__1 = 1, H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3,
  H_GR__3 = 3, H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5,
  H_GR__5 = 5, H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7,
  H_GR__7 = 7, H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9,
  H_GR__9 = 9, H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11,
  H_GR__11 = 11, H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13,
  H_GR__13 = 13, H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15,
  H_GR__15 = 15, H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17,
  H_GR__17 = 17, H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19,
  H_GR__19 = 19, H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21,
  H_GR__21 = 21, H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23,
  H_GR__23 = 23, H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25,
  H_GR__25 = 25, H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27,
  H_GR__27 = 27, H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29,
  H_GR__29 = 29, H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31,
  H_GR__31 = 31, H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15,
  H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3,
  H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7,
  H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11,
  H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15,
  H_GR_R0, H_GR_R1, H_GR_R2, H_GR_R3,
  H_GR_R4, H_GR_R5, H_GR_R6, H_GR_R7,
  H_GR_R8, H_GR_R9, H_GR_R10, H_GR_R11,
  H_GR_R12, H_GR_R13, H_GR_R14, H_GR_R15,
  H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3,
  H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7,
  H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11,
  H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15,
  H_GR_PSW = 14, H_GR_SP = 15
}
enum  fr_names {
  H_FR_FR0, H_FR_FR1, H_FR_FR2, H_FR_FR3,
  H_FR_FR4, H_FR_FR5, H_FR_FR6, H_FR_FR7,
  H_FR_FR8, H_FR_FR9, H_FR_FR10, H_FR_FR11,
  H_FR_FR12, H_FR_FR13, H_FR_FR14, H_FR_FR15,
  H_FR_FR16, H_FR_FR17, H_FR_FR18, H_FR_FR19,
  H_FR_FR20, H_FR_FR21, H_FR_FR22, H_FR_FR23,
  H_FR_FR24, H_FR_FR25, H_FR_FR26, H_FR_FR27,
  H_FR_FR28, H_FR_FR29, H_FR_FR30, H_FR_FR31,
  H_FR_FR32, H_FR_FR33, H_FR_FR34, H_FR_FR35,
  H_FR_FR36, H_FR_FR37, H_FR_FR38, H_FR_FR39,
  H_FR_FR40, H_FR_FR41, H_FR_FR42, H_FR_FR43,
  H_FR_FR44, H_FR_FR45, H_FR_FR46, H_FR_FR47,
  H_FR_FR48, H_FR_FR49, H_FR_FR50, H_FR_FR51,
  H_FR_FR52, H_FR_FR53, H_FR_FR54, H_FR_FR55,
  H_FR_FR56, H_FR_FR57, H_FR_FR58, H_FR_FR59,
  H_FR_FR60, H_FR_FR61, H_FR_FR62, H_FR_FR63
}
enum  cpr_names {
  H_CPR_CPR0, H_CPR_CPR1, H_CPR_CPR2, H_CPR_CPR3,
  H_CPR_CPR4, H_CPR_CPR5, H_CPR_CPR6, H_CPR_CPR7,
  H_CPR_CPR8, H_CPR_CPR9, H_CPR_CPR10, H_CPR_CPR11,
  H_CPR_CPR12, H_CPR_CPR13, H_CPR_CPR14, H_CPR_CPR15,
  H_CPR_CPR16, H_CPR_CPR17, H_CPR_CPR18, H_CPR_CPR19,
  H_CPR_CPR20, H_CPR_CPR21, H_CPR_CPR22, H_CPR_CPR23,
  H_CPR_CPR24, H_CPR_CPR25, H_CPR_CPR26, H_CPR_CPR27,
  H_CPR_CPR28, H_CPR_CPR29, H_CPR_CPR30, H_CPR_CPR31,
  H_CPR_CPR32, H_CPR_CPR33, H_CPR_CPR34, H_CPR_CPR35,
  H_CPR_CPR36, H_CPR_CPR37, H_CPR_CPR38, H_CPR_CPR39,
  H_CPR_CPR40, H_CPR_CPR41, H_CPR_CPR42, H_CPR_CPR43,
  H_CPR_CPR44, H_CPR_CPR45, H_CPR_CPR46, H_CPR_CPR47,
  H_CPR_CPR48, H_CPR_CPR49, H_CPR_CPR50, H_CPR_CPR51,
  H_CPR_CPR52, H_CPR_CPR53, H_CPR_CPR54, H_CPR_CPR55,
  H_CPR_CPR56, H_CPR_CPR57, H_CPR_CPR58, H_CPR_CPR59,
  H_CPR_CPR60, H_CPR_CPR61, H_CPR_CPR62, H_CPR_CPR63
}
enum  spr_names {
  H_SPR_PSR = 0, H_SPR_PCSR = 1, H_SPR_BPCSR = 2, H_SPR_TBR = 3,
  H_SPR_BPSR = 4, H_SPR_HSR0 = 16, H_SPR_HSR1 = 17, H_SPR_HSR2 = 18,
  H_SPR_HSR3 = 19, H_SPR_HSR4 = 20, H_SPR_HSR5 = 21, H_SPR_HSR6 = 22,
  H_SPR_HSR7 = 23, H_SPR_HSR8 = 24, H_SPR_HSR9 = 25, H_SPR_HSR10 = 26,
  H_SPR_HSR11 = 27, H_SPR_HSR12 = 28, H_SPR_HSR13 = 29, H_SPR_HSR14 = 30,
  H_SPR_HSR15 = 31, H_SPR_HSR16 = 32, H_SPR_HSR17 = 33, H_SPR_HSR18 = 34,
  H_SPR_HSR19 = 35, H_SPR_HSR20 = 36, H_SPR_HSR21 = 37, H_SPR_HSR22 = 38,
  H_SPR_HSR23 = 39, H_SPR_HSR24 = 40, H_SPR_HSR25 = 41, H_SPR_HSR26 = 42,
  H_SPR_HSR27 = 43, H_SPR_HSR28 = 44, H_SPR_HSR29 = 45, H_SPR_HSR30 = 46,
  H_SPR_HSR31 = 47, H_SPR_HSR32 = 48, H_SPR_HSR33 = 49, H_SPR_HSR34 = 50,
  H_SPR_HSR35 = 51, H_SPR_HSR36 = 52, H_SPR_HSR37 = 53, H_SPR_HSR38 = 54,
  H_SPR_HSR39 = 55, H_SPR_HSR40 = 56, H_SPR_HSR41 = 57, H_SPR_HSR42 = 58,
  H_SPR_HSR43 = 59, H_SPR_HSR44 = 60, H_SPR_HSR45 = 61, H_SPR_HSR46 = 62,
  H_SPR_HSR47 = 63, H_SPR_HSR48 = 64, H_SPR_HSR49 = 65, H_SPR_HSR50 = 66,
  H_SPR_HSR51 = 67, H_SPR_HSR52 = 68, H_SPR_HSR53 = 69, H_SPR_HSR54 = 70,
  H_SPR_HSR55 = 71, H_SPR_HSR56 = 72, H_SPR_HSR57 = 73, H_SPR_HSR58 = 74,
  H_SPR_HSR59 = 75, H_SPR_HSR60 = 76, H_SPR_HSR61 = 77, H_SPR_HSR62 = 78,
  H_SPR_HSR63 = 79, H_SPR_CCR = 256, H_SPR_CCCR = 263, H_SPR_LR = 272,
  H_SPR_LCR = 273, H_SPR_IACC0H = 280, H_SPR_IACC0L = 281, H_SPR_ISR = 288,
  H_SPR_NEEAR0 = 352, H_SPR_NEEAR1 = 353, H_SPR_NEEAR2 = 354, H_SPR_NEEAR3 = 355,
  H_SPR_NEEAR4 = 356, H_SPR_NEEAR5 = 357, H_SPR_NEEAR6 = 358, H_SPR_NEEAR7 = 359,
  H_SPR_NEEAR8 = 360, H_SPR_NEEAR9 = 361, H_SPR_NEEAR10 = 362, H_SPR_NEEAR11 = 363,
  H_SPR_NEEAR12 = 364, H_SPR_NEEAR13 = 365, H_SPR_NEEAR14 = 366, H_SPR_NEEAR15 = 367,
  H_SPR_NEEAR16 = 368, H_SPR_NEEAR17 = 369, H_SPR_NEEAR18 = 370, H_SPR_NEEAR19 = 371,
  H_SPR_NEEAR20 = 372, H_SPR_NEEAR21 = 373, H_SPR_NEEAR22 = 374, H_SPR_NEEAR23 = 375,
  H_SPR_NEEAR24 = 376, H_SPR_NEEAR25 = 377, H_SPR_NEEAR26 = 378, H_SPR_NEEAR27 = 379,
  H_SPR_NEEAR28 = 380, H_SPR_NEEAR29 = 381, H_SPR_NEEAR30 = 382, H_SPR_NEEAR31 = 383,
  H_SPR_NESR0 = 384, H_SPR_NESR1 = 385, H_SPR_NESR2 = 386, H_SPR_NESR3 = 387,
  H_SPR_NESR4 = 388, H_SPR_NESR5 = 389, H_SPR_NESR6 = 390, H_SPR_NESR7 = 391,
  H_SPR_NESR8 = 392, H_SPR_NESR9 = 393, H_SPR_NESR10 = 394, H_SPR_NESR11 = 395,
  H_SPR_NESR12 = 396, H_SPR_NESR13 = 397, H_SPR_NESR14 = 398, H_SPR_NESR15 = 399,
  H_SPR_NESR16 = 400, H_SPR_NESR17 = 401, H_SPR_NESR18 = 402, H_SPR_NESR19 = 403,
  H_SPR_NESR20 = 404, H_SPR_NESR21 = 405, H_SPR_NESR22 = 406, H_SPR_NESR23 = 407,
  H_SPR_NESR24 = 408, H_SPR_NESR25 = 409, H_SPR_NESR26 = 410, H_SPR_NESR27 = 411,
  H_SPR_NESR28 = 412, H_SPR_NESR29 = 413, H_SPR_NESR30 = 414, H_SPR_NESR31 = 415,
  H_SPR_NECR = 416, H_SPR_GNER0 = 432, H_SPR_GNER1 = 433, H_SPR_FNER0 = 434,
  H_SPR_FNER1 = 435, H_SPR_EPCR0 = 512, H_SPR_EPCR1 = 513, H_SPR_EPCR2 = 514,
  H_SPR_EPCR3 = 515, H_SPR_EPCR4 = 516, H_SPR_EPCR5 = 517, H_SPR_EPCR6 = 518,
  H_SPR_EPCR7 = 519, H_SPR_EPCR8 = 520, H_SPR_EPCR9 = 521, H_SPR_EPCR10 = 522,
  H_SPR_EPCR11 = 523, H_SPR_EPCR12 = 524, H_SPR_EPCR13 = 525, H_SPR_EPCR14 = 526,
  H_SPR_EPCR15 = 527, H_SPR_EPCR16 = 528, H_SPR_EPCR17 = 529, H_SPR_EPCR18 = 530,
  H_SPR_EPCR19 = 531, H_SPR_EPCR20 = 532, H_SPR_EPCR21 = 533, H_SPR_EPCR22 = 534,
  H_SPR_EPCR23 = 535, H_SPR_EPCR24 = 536, H_SPR_EPCR25 = 537, H_SPR_EPCR26 = 538,
  H_SPR_EPCR27 = 539, H_SPR_EPCR28 = 540, H_SPR_EPCR29 = 541, H_SPR_EPCR30 = 542,
  H_SPR_EPCR31 = 543, H_SPR_EPCR32 = 544, H_SPR_EPCR33 = 545, H_SPR_EPCR34 = 546,
  H_SPR_EPCR35 = 547, H_SPR_EPCR36 = 548, H_SPR_EPCR37 = 549, H_SPR_EPCR38 = 550,
  H_SPR_EPCR39 = 551, H_SPR_EPCR40 = 552, H_SPR_EPCR41 = 553, H_SPR_EPCR42 = 554,
  H_SPR_EPCR43 = 555, H_SPR_EPCR44 = 556, H_SPR_EPCR45 = 557, H_SPR_EPCR46 = 558,
  H_SPR_EPCR47 = 559, H_SPR_EPCR48 = 560, H_SPR_EPCR49 = 561, H_SPR_EPCR50 = 562,
  H_SPR_EPCR51 = 563, H_SPR_EPCR52 = 564, H_SPR_EPCR53 = 565, H_SPR_EPCR54 = 566,
  H_SPR_EPCR55 = 567, H_SPR_EPCR56 = 568, H_SPR_EPCR57 = 569, H_SPR_EPCR58 = 570,
  H_SPR_EPCR59 = 571, H_SPR_EPCR60 = 572, H_SPR_EPCR61 = 573, H_SPR_EPCR62 = 574,
  H_SPR_EPCR63 = 575, H_SPR_ESR0 = 576, H_SPR_ESR1 = 577, H_SPR_ESR2 = 578,
  H_SPR_ESR3 = 579, H_SPR_ESR4 = 580, H_SPR_ESR5 = 581, H_SPR_ESR6 = 582,
  H_SPR_ESR7 = 583, H_SPR_ESR8 = 584, H_SPR_ESR9 = 585, H_SPR_ESR10 = 586,
  H_SPR_ESR11 = 587, H_SPR_ESR12 = 588, H_SPR_ESR13 = 589, H_SPR_ESR14 = 590,
  H_SPR_ESR15 = 591, H_SPR_ESR16 = 592, H_SPR_ESR17 = 593, H_SPR_ESR18 = 594,
  H_SPR_ESR19 = 595, H_SPR_ESR20 = 596, H_SPR_ESR21 = 597, H_SPR_ESR22 = 598,
  H_SPR_ESR23 = 599, H_SPR_ESR24 = 600, H_SPR_ESR25 = 601, H_SPR_ESR26 = 602,
  H_SPR_ESR27 = 603, H_SPR_ESR28 = 604, H_SPR_ESR29 = 605, H_SPR_ESR30 = 606,
  H_SPR_ESR31 = 607, H_SPR_ESR32 = 608, H_SPR_ESR33 = 609, H_SPR_ESR34 = 610,
  H_SPR_ESR35 = 611, H_SPR_ESR36 = 612, H_SPR_ESR37 = 613, H_SPR_ESR38 = 614,
  H_SPR_ESR39 = 615, H_SPR_ESR40 = 616, H_SPR_ESR41 = 617, H_SPR_ESR42 = 618,
  H_SPR_ESR43 = 619, H_SPR_ESR44 = 620, H_SPR_ESR45 = 621, H_SPR_ESR46 = 622,
  H_SPR_ESR47 = 623, H_SPR_ESR48 = 624, H_SPR_ESR49 = 625, H_SPR_ESR50 = 626,
  H_SPR_ESR51 = 627, H_SPR_ESR52 = 628, H_SPR_ESR53 = 629, H_SPR_ESR54 = 630,
  H_SPR_ESR55 = 631, H_SPR_ESR56 = 632, H_SPR_ESR57 = 633, H_SPR_ESR58 = 634,
  H_SPR_ESR59 = 635, H_SPR_ESR60 = 636, H_SPR_ESR61 = 637, H_SPR_ESR62 = 638,
  H_SPR_ESR63 = 639, H_SPR_EIR0 = 640, H_SPR_EIR1 = 641, H_SPR_EIR2 = 642,
  H_SPR_EIR3 = 643, H_SPR_EIR4 = 644, H_SPR_EIR5 = 645, H_SPR_EIR6 = 646,
  H_SPR_EIR7 = 647, H_SPR_EIR8 = 648, H_SPR_EIR9 = 649, H_SPR_EIR10 = 650,
  H_SPR_EIR11 = 651, H_SPR_EIR12 = 652, H_SPR_EIR13 = 653, H_SPR_EIR14 = 654,
  H_SPR_EIR15 = 655, H_SPR_EIR16 = 656, H_SPR_EIR17 = 657, H_SPR_EIR18 = 658,
  H_SPR_EIR19 = 659, H_SPR_EIR20 = 660, H_SPR_EIR21 = 661, H_SPR_EIR22 = 662,
  H_SPR_EIR23 = 663, H_SPR_EIR24 = 664, H_SPR_EIR25 = 665, H_SPR_EIR26 = 666,
  H_SPR_EIR27 = 667, H_SPR_EIR28 = 668, H_SPR_EIR29 = 669, H_SPR_EIR30 = 670,
  H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672, H_SPR_ESFR1 = 673, H_SPR_SR0 = 768,
  H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_SCR0 = 832,
  H_SPR_SCR1 = 833, H_SPR_SCR2 = 834, H_SPR_SCR3 = 835, H_SPR_FSR0 = 1024,
  H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026, H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028,
  H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030, H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032,
  H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034, H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036,
  H_SPR_FSR13 = 1037, H_SPR_FSR14 = 1038, H_SPR_FSR15 = 1039, H_SPR_FSR16 = 1040,
  H_SPR_FSR17 = 1041, H_SPR_FSR18 = 1042, H_SPR_FSR19 = 1043, H_SPR_FSR20 = 1044,
  H_SPR_FSR21 = 1045, H_SPR_FSR22 = 1046, H_SPR_FSR23 = 1047, H_SPR_FSR24 = 1048,
  H_SPR_FSR25 = 1049, H_SPR_FSR26 = 1050, H_SPR_FSR27 = 1051, H_SPR_FSR28 = 1052,
  H_SPR_FSR29 = 1053, H_SPR_FSR30 = 1054, H_SPR_FSR31 = 1055, H_SPR_FSR32 = 1056,
  H_SPR_FSR33 = 1057, H_SPR_FSR34 = 1058, H_SPR_FSR35 = 1059, H_SPR_FSR36 = 1060,
  H_SPR_FSR37 = 1061, H_SPR_FSR38 = 1062, H_SPR_FSR39 = 1063, H_SPR_FSR40 = 1064,
  H_SPR_FSR41 = 1065, H_SPR_FSR42 = 1066, H_SPR_FSR43 = 1067, H_SPR_FSR44 = 1068,
  H_SPR_FSR45 = 1069, H_SPR_FSR46 = 1070, H_SPR_FSR47 = 1071, H_SPR_FSR48 = 1072,
  H_SPR_FSR49 = 1073, H_SPR_FSR50 = 1074, H_SPR_FSR51 = 1075, H_SPR_FSR52 = 1076,
  H_SPR_FSR53 = 1077, H_SPR_FSR54 = 1078, H_SPR_FSR55 = 1079, H_SPR_FSR56 = 1080,
  H_SPR_FSR57 = 1081, H_SPR_FSR58 = 1082, H_SPR_FSR59 = 1083, H_SPR_FSR60 = 1084,
  H_SPR_FSR61 = 1085, H_SPR_FSR62 = 1086, H_SPR_FSR63 = 1087, H_SPR_FQOP0 = 1088,
  H_SPR_FQOP1 = 1090, H_SPR_FQOP2 = 1092, H_SPR_FQOP3 = 1094, H_SPR_FQOP4 = 1096,
  H_SPR_FQOP5 = 1098, H_SPR_FQOP6 = 1100, H_SPR_FQOP7 = 1102, H_SPR_FQOP8 = 1104,
  H_SPR_FQOP9 = 1106, H_SPR_FQOP10 = 1108, H_SPR_FQOP11 = 1110, H_SPR_FQOP12 = 1112,
  H_SPR_FQOP13 = 1114, H_SPR_FQOP14 = 1116, H_SPR_FQOP15 = 1118, H_SPR_FQOP16 = 1120,
  H_SPR_FQOP17 = 1122, H_SPR_FQOP18 = 1124, H_SPR_FQOP19 = 1126, H_SPR_FQOP20 = 1128,
  H_SPR_FQOP21 = 1130, H_SPR_FQOP22 = 1132, H_SPR_FQOP23 = 1134, H_SPR_FQOP24 = 1136,
  H_SPR_FQOP25 = 1138, H_SPR_FQOP26 = 1140, H_SPR_FQOP27 = 1142, H_SPR_FQOP28 = 1144,
  H_SPR_FQOP29 = 1146, H_SPR_FQOP30 = 1148, H_SPR_FQOP31 = 1150, H_SPR_FQST0 = 1089,
  H_SPR_FQST1 = 1091, H_SPR_FQST2 = 1093, H_SPR_FQST3 = 1095, H_SPR_FQST4 = 1097,
  H_SPR_FQST5 = 1099, H_SPR_FQST6 = 1101, H_SPR_FQST7 = 1103, H_SPR_FQST8 = 1105,
  H_SPR_FQST9 = 1107, H_SPR_FQST10 = 1109, H_SPR_FQST11 = 1111, H_SPR_FQST12 = 1113,
  H_SPR_FQST13 = 1115, H_SPR_FQST14 = 1117, H_SPR_FQST15 = 1119, H_SPR_FQST16 = 1121,
  H_SPR_FQST17 = 1123, H_SPR_FQST18 = 1125, H_SPR_FQST19 = 1127, H_SPR_FQST20 = 1129,
  H_SPR_FQST21 = 1131, H_SPR_FQST22 = 1133, H_SPR_FQST23 = 1135, H_SPR_FQST24 = 1137,
  H_SPR_FQST25 = 1139, H_SPR_FQST26 = 1141, H_SPR_FQST27 = 1143, H_SPR_FQST28 = 1145,
  H_SPR_FQST29 = 1147, H_SPR_FQST30 = 1149, H_SPR_FQST31 = 1151, H_SPR_MCILR0 = 1272,
  H_SPR_MCILR1 = 1273, H_SPR_MSR0 = 1280, H_SPR_MSR1 = 1281, H_SPR_MSR2 = 1282,
  H_SPR_MSR3 = 1283, H_SPR_MSR4 = 1284, H_SPR_MSR5 = 1285, H_SPR_MSR6 = 1286,
  H_SPR_MSR7 = 1287, H_SPR_MSR8 = 1288, H_SPR_MSR9 = 1289, H_SPR_MSR10 = 1290,
  H_SPR_MSR11 = 1291, H_SPR_MSR12 = 1292, H_SPR_MSR13 = 1293, H_SPR_MSR14 = 1294,
  H_SPR_MSR15 = 1295, H_SPR_MSR16 = 1296, H_SPR_MSR17 = 1297, H_SPR_MSR18 = 1298,
  H_SPR_MSR19 = 1299, H_SPR_MSR20 = 1300, H_SPR_MSR21 = 1301, H_SPR_MSR22 = 1302,
  H_SPR_MSR23 = 1303, H_SPR_MSR24 = 1304, H_SPR_MSR25 = 1305, H_SPR_MSR26 = 1306,
  H_SPR_MSR27 = 1307, H_SPR_MSR28 = 1308, H_SPR_MSR29 = 1309, H_SPR_MSR30 = 1310,
  H_SPR_MSR31 = 1311, H_SPR_MSR32 = 1312, H_SPR_MSR33 = 1313, H_SPR_MSR34 = 1314,
  H_SPR_MSR35 = 1315, H_SPR_MSR36 = 1316, H_SPR_MSR37 = 1317, H_SPR_MSR38 = 1318,
  H_SPR_MSR39 = 1319, H_SPR_MSR40 = 1320, H_SPR_MSR41 = 1321, H_SPR_MSR42 = 1322,
  H_SPR_MSR43 = 1323, H_SPR_MSR44 = 1324, H_SPR_MSR45 = 1325, H_SPR_MSR46 = 1326,
  H_SPR_MSR47 = 1327, H_SPR_MSR48 = 1328, H_SPR_MSR49 = 1329, H_SPR_MSR50 = 1330,
  H_SPR_MSR51 = 1331, H_SPR_MSR52 = 1332, H_SPR_MSR53 = 1333, H_SPR_MSR54 = 1334,
  H_SPR_MSR55 = 1335, H_SPR_MSR56 = 1336, H_SPR_MSR57 = 1337, H_SPR_MSR58 = 1338,
  H_SPR_MSR59 = 1339, H_SPR_MSR60 = 1340, H_SPR_MSR61 = 1341, H_SPR_MSR62 = 1342,
  H_SPR_MSR63 = 1343, H_SPR_MQOP0 = 1344, H_SPR_MQOP1 = 1346, H_SPR_MQOP2 = 1348,
  H_SPR_MQOP3 = 1350, H_SPR_MQOP4 = 1352, H_SPR_MQOP5 = 1354, H_SPR_MQOP6 = 1356,
  H_SPR_MQOP7 = 1358, H_SPR_MQOP8 = 1360, H_SPR_MQOP9 = 1362, H_SPR_MQOP10 = 1364,
  H_SPR_MQOP11 = 1366, H_SPR_MQOP12 = 1368, H_SPR_MQOP13 = 1370, H_SPR_MQOP14 = 1372,
  H_SPR_MQOP15 = 1374, H_SPR_MQOP16 = 1376, H_SPR_MQOP17 = 1378, H_SPR_MQOP18 = 1380,
  H_SPR_MQOP19 = 1382, H_SPR_MQOP20 = 1384, H_SPR_MQOP21 = 1386, H_SPR_MQOP22 = 1388,
  H_SPR_MQOP23 = 1390, H_SPR_MQOP24 = 1392, H_SPR_MQOP25 = 1394, H_SPR_MQOP26 = 1396,
  H_SPR_MQOP27 = 1398, H_SPR_MQOP28 = 1400, H_SPR_MQOP29 = 1402, H_SPR_MQOP30 = 1404,
  H_SPR_MQOP31 = 1406, H_SPR_MQST0 = 1345, H_SPR_MQST1 = 1347, H_SPR_MQST2 = 1349,
  H_SPR_MQST3 = 1351, H_SPR_MQST4 = 1353, H_SPR_MQST5 = 1355, H_SPR_MQST6 = 1357,
  H_SPR_MQST7 = 1359, H_SPR_MQST8 = 1361, H_SPR_MQST9 = 1363, H_SPR_MQST10 = 1365,
  H_SPR_MQST11 = 1367, H_SPR_MQST12 = 1369, H_SPR_MQST13 = 1371, H_SPR_MQST14 = 1373,
  H_SPR_MQST15 = 1375, H_SPR_MQST16 = 1377, H_SPR_MQST17 = 1379, H_SPR_MQST18 = 1381,
  H_SPR_MQST19 = 1383, H_SPR_MQST20 = 1385, H_SPR_MQST21 = 1387, H_SPR_MQST22 = 1389,
  H_SPR_MQST23 = 1391, H_SPR_MQST24 = 1393, H_SPR_MQST25 = 1395, H_SPR_MQST26 = 1397,
  H_SPR_MQST27 = 1399, H_SPR_MQST28 = 1401, H_SPR_MQST29 = 1403, H_SPR_MQST30 = 1405,
  H_SPR_MQST31 = 1407, H_SPR_EAR0 = 1536, H_SPR_EAR1 = 1537, H_SPR_EAR2 = 1538,
  H_SPR_EAR3 = 1539, H_SPR_EAR4 = 1540, H_SPR_EAR5 = 1541, H_SPR_EAR6 = 1542,
  H_SPR_EAR7 = 1543, H_SPR_EAR8 = 1544, H_SPR_EAR9 = 1545, H_SPR_EAR10 = 1546,
  H_SPR_EAR11 = 1547, H_SPR_EAR12 = 1548, H_SPR_EAR13 = 1549, H_SPR_EAR14 = 1550,
  H_SPR_EAR15 = 1551, H_SPR_EAR16 = 1552, H_SPR_EAR17 = 1553, H_SPR_EAR18 = 1554,
  H_SPR_EAR19 = 1555, H_SPR_EAR20 = 1556, H_SPR_EAR21 = 1557, H_SPR_EAR22 = 1558,
  H_SPR_EAR23 = 1559, H_SPR_EAR24 = 1560, H_SPR_EAR25 = 1561, H_SPR_EAR26 = 1562,
  H_SPR_EAR27 = 1563, H_SPR_EAR28 = 1564, H_SPR_EAR29 = 1565, H_SPR_EAR30 = 1566,
  H_SPR_EAR31 = 1567, H_SPR_EAR32 = 1568, H_SPR_EAR33 = 1569, H_SPR_EAR34 = 1570,
  H_SPR_EAR35 = 1571, H_SPR_EAR36 = 1572, H_SPR_EAR37 = 1573, H_SPR_EAR38 = 1574,
  H_SPR_EAR39 = 1575, H_SPR_EAR40 = 1576, H_SPR_EAR41 = 1577, H_SPR_EAR42 = 1578,
  H_SPR_EAR43 = 1579, H_SPR_EAR44 = 1580, H_SPR_EAR45 = 1581, H_SPR_EAR46 = 1582,
  H_SPR_EAR47 = 1583, H_SPR_EAR48 = 1584, H_SPR_EAR49 = 1585, H_SPR_EAR50 = 1586,
  H_SPR_EAR51 = 1587, H_SPR_EAR52 = 1588, H_SPR_EAR53 = 1589, H_SPR_EAR54 = 1590,
  H_SPR_EAR55 = 1591, H_SPR_EAR56 = 1592, H_SPR_EAR57 = 1593, H_SPR_EAR58 = 1594,
  H_SPR_EAR59 = 1595, H_SPR_EAR60 = 1596, H_SPR_EAR61 = 1597, H_SPR_EAR62 = 1598,
  H_SPR_EAR63 = 1599, H_SPR_EDR0 = 1600, H_SPR_EDR1 = 1601, H_SPR_EDR2 = 1602,
  H_SPR_EDR3 = 1603, H_SPR_EDR4 = 1604, H_SPR_EDR5 = 1605, H_SPR_EDR6 = 1606,
  H_SPR_EDR7 = 1607, H_SPR_EDR8 = 1608, H_SPR_EDR9 = 1609, H_SPR_EDR10 = 1610,
  H_SPR_EDR11 = 1611, H_SPR_EDR12 = 1612, H_SPR_EDR13 = 1613, H_SPR_EDR14 = 1614,
  H_SPR_EDR15 = 1615, H_SPR_EDR16 = 1616, H_SPR_EDR17 = 1617, H_SPR_EDR18 = 1618,
  H_SPR_EDR19 = 1619, H_SPR_EDR20 = 1620, H_SPR_EDR21 = 1621, H_SPR_EDR22 = 1622,
  H_SPR_EDR23 = 1623, H_SPR_EDR24 = 1624, H_SPR_EDR25 = 1625, H_SPR_EDR26 = 1626,
  H_SPR_EDR27 = 1627, H_SPR_EDR28 = 1628, H_SPR_EDR29 = 1629, H_SPR_EDR30 = 1630,
  H_SPR_EDR31 = 1631, H_SPR_EDR32 = 1632, H_SPR_EDR33 = 1636, H_SPR_EDR34 = 1634,
  H_SPR_EDR35 = 1635, H_SPR_EDR36 = 1636, H_SPR_EDR37 = 1637, H_SPR_EDR38 = 1638,
  H_SPR_EDR39 = 1639, H_SPR_EDR40 = 1640, H_SPR_EDR41 = 1641, H_SPR_EDR42 = 1642,
  H_SPR_EDR43 = 1643, H_SPR_EDR44 = 1644, H_SPR_EDR45 = 1645, H_SPR_EDR46 = 1646,
  H_SPR_EDR47 = 1647, H_SPR_EDR48 = 1648, H_SPR_EDR49 = 1649, H_SPR_EDR50 = 1650,
  H_SPR_EDR51 = 1651, H_SPR_EDR52 = 1652, H_SPR_EDR53 = 1653, H_SPR_EDR54 = 1654,
  H_SPR_EDR55 = 1655, H_SPR_EDR56 = 1656, H_SPR_EDR57 = 1657, H_SPR_EDR58 = 1658,
  H_SPR_EDR59 = 1659, H_SPR_EDR60 = 1660, H_SPR_EDR61 = 1661, H_SPR_EDR62 = 1662,
  H_SPR_EDR63 = 1663, H_SPR_IAMLR0 = 1664, H_SPR_IAMLR1 = 1665, H_SPR_IAMLR2 = 1666,
  H_SPR_IAMLR3 = 1667, H_SPR_IAMLR4 = 1668, H_SPR_IAMLR5 = 1669, H_SPR_IAMLR6 = 1670,
  H_SPR_IAMLR7 = 1671, H_SPR_IAMLR8 = 1672, H_SPR_IAMLR9 = 1673, H_SPR_IAMLR10 = 1674,
  H_SPR_IAMLR11 = 1675, H_SPR_IAMLR12 = 1676, H_SPR_IAMLR13 = 1677, H_SPR_IAMLR14 = 1678,
  H_SPR_IAMLR15 = 1679, H_SPR_IAMLR16 = 1680, H_SPR_IAMLR17 = 1681, H_SPR_IAMLR18 = 1682,
  H_SPR_IAMLR19 = 1683, H_SPR_IAMLR20 = 1684, H_SPR_IAMLR21 = 1685, H_SPR_IAMLR22 = 1686,
  H_SPR_IAMLR23 = 1687, H_SPR_IAMLR24 = 1688, H_SPR_IAMLR25 = 1689, H_SPR_IAMLR26 = 1690,
  H_SPR_IAMLR27 = 1691, H_SPR_IAMLR28 = 1692, H_SPR_IAMLR29 = 1693, H_SPR_IAMLR30 = 1694,
  H_SPR_IAMLR31 = 1695, H_SPR_IAMLR32 = 1696, H_SPR_IAMLR33 = 1697, H_SPR_IAMLR34 = 1698,
  H_SPR_IAMLR35 = 1699, H_SPR_IAMLR36 = 1700, H_SPR_IAMLR37 = 1701, H_SPR_IAMLR38 = 1702,
  H_SPR_IAMLR39 = 1703, H_SPR_IAMLR40 = 1704, H_SPR_IAMLR41 = 1705, H_SPR_IAMLR42 = 1706,
  H_SPR_IAMLR43 = 1707, H_SPR_IAMLR44 = 1708, H_SPR_IAMLR45 = 1709, H_SPR_IAMLR46 = 1710,
  H_SPR_IAMLR47 = 1711, H_SPR_IAMLR48 = 1712, H_SPR_IAMLR49 = 1713, H_SPR_IAMLR50 = 1714,
  H_SPR_IAMLR51 = 1715, H_SPR_IAMLR52 = 1716, H_SPR_IAMLR53 = 1717, H_SPR_IAMLR54 = 1718,
  H_SPR_IAMLR55 = 1719, H_SPR_IAMLR56 = 1720, H_SPR_IAMLR57 = 1721, H_SPR_IAMLR58 = 1722,
  H_SPR_IAMLR59 = 1723, H_SPR_IAMLR60 = 1724, H_SPR_IAMLR61 = 1725, H_SPR_IAMLR62 = 1726,
  H_SPR_IAMLR63 = 1727, H_SPR_IAMPR0 = 1728, H_SPR_IAMPR1 = 1729, H_SPR_IAMPR2 = 1730,
  H_SPR_IAMPR3 = 1731, H_SPR_IAMPR4 = 1732, H_SPR_IAMPR5 = 1733, H_SPR_IAMPR6 = 1734,
  H_SPR_IAMPR7 = 1735, H_SPR_IAMPR8 = 1736, H_SPR_IAMPR9 = 1737, H_SPR_IAMPR10 = 1738,
  H_SPR_IAMPR11 = 1739, H_SPR_IAMPR12 = 1740, H_SPR_IAMPR13 = 1741, H_SPR_IAMPR14 = 1742,
  H_SPR_IAMPR15 = 1743, H_SPR_IAMPR16 = 1744, H_SPR_IAMPR17 = 1745, H_SPR_IAMPR18 = 1746,
  H_SPR_IAMPR19 = 1747, H_SPR_IAMPR20 = 1748, H_SPR_IAMPR21 = 1749, H_SPR_IAMPR22 = 1750,
  H_SPR_IAMPR23 = 1751, H_SPR_IAMPR24 = 1752, H_SPR_IAMPR25 = 1753, H_SPR_IAMPR26 = 1754,
  H_SPR_IAMPR27 = 1755, H_SPR_IAMPR28 = 1756, H_SPR_IAMPR29 = 1757, H_SPR_IAMPR30 = 1758,
  H_SPR_IAMPR31 = 1759, H_SPR_IAMPR32 = 1760, H_SPR_IAMPR33 = 1761, H_SPR_IAMPR34 = 1762,
  H_SPR_IAMPR35 = 1763, H_SPR_IAMPR36 = 1764, H_SPR_IAMPR37 = 1765, H_SPR_IAMPR38 = 1766,
  H_SPR_IAMPR39 = 1767, H_SPR_IAMPR40 = 1768, H_SPR_IAMPR41 = 1769, H_SPR_IAMPR42 = 1770,
  H_SPR_IAMPR43 = 1771, H_SPR_IAMPR44 = 1772, H_SPR_IAMPR45 = 1773, H_SPR_IAMPR46 = 1774,
  H_SPR_IAMPR47 = 1775, H_SPR_IAMPR48 = 1776, H_SPR_IAMPR49 = 1777, H_SPR_IAMPR50 = 1778,
  H_SPR_IAMPR51 = 1779, H_SPR_IAMPR52 = 1780, H_SPR_IAMPR53 = 1781, H_SPR_IAMPR54 = 1782,
  H_SPR_IAMPR55 = 1783, H_SPR_IAMPR56 = 1784, H_SPR_IAMPR57 = 1785, H_SPR_IAMPR58 = 1786,
  H_SPR_IAMPR59 = 1787, H_SPR_IAMPR60 = 1788, H_SPR_IAMPR61 = 1789, H_SPR_IAMPR62 = 1790,
  H_SPR_IAMPR63 = 1791, H_SPR_DAMLR0 = 1792, H_SPR_DAMLR1 = 1793, H_SPR_DAMLR2 = 1794,
  H_SPR_DAMLR3 = 1795, H_SPR_DAMLR4 = 1796, H_SPR_DAMLR5 = 1797, H_SPR_DAMLR6 = 1798,
  H_SPR_DAMLR7 = 1799, H_SPR_DAMLR8 = 1800, H_SPR_DAMLR9 = 1801, H_SPR_DAMLR10 = 1802,
  H_SPR_DAMLR11 = 1803, H_SPR_DAMLR12 = 1804, H_SPR_DAMLR13 = 1805, H_SPR_DAMLR14 = 1806,
  H_SPR_DAMLR15 = 1807, H_SPR_DAMLR16 = 1808, H_SPR_DAMLR17 = 1809, H_SPR_DAMLR18 = 1810,
  H_SPR_DAMLR19 = 1811, H_SPR_DAMLR20 = 1812, H_SPR_DAMLR21 = 1813, H_SPR_DAMLR22 = 1814,
  H_SPR_DAMLR23 = 1815, H_SPR_DAMLR24 = 1816, H_SPR_DAMLR25 = 1817, H_SPR_DAMLR26 = 1818,
  H_SPR_DAMLR27 = 1819, H_SPR_DAMLR28 = 1820, H_SPR_DAMLR29 = 1821, H_SPR_DAMLR30 = 1822,
  H_SPR_DAMLR31 = 1823, H_SPR_DAMLR32 = 1824, H_SPR_DAMLR33 = 1825, H_SPR_DAMLR34 = 1826,
  H_SPR_DAMLR35 = 1827, H_SPR_DAMLR36 = 1828, H_SPR_DAMLR37 = 1829, H_SPR_DAMLR38 = 1830,
  H_SPR_DAMLR39 = 1831, H_SPR_DAMLR40 = 1832, H_SPR_DAMLR41 = 1833, H_SPR_DAMLR42 = 1834,
  H_SPR_DAMLR43 = 1835, H_SPR_DAMLR44 = 1836, H_SPR_DAMLR45 = 1837, H_SPR_DAMLR46 = 1838,
  H_SPR_DAMLR47 = 1839, H_SPR_DAMLR48 = 1840, H_SPR_DAMLR49 = 1841, H_SPR_DAMLR50 = 1842,
  H_SPR_DAMLR51 = 1843, H_SPR_DAMLR52 = 1844, H_SPR_DAMLR53 = 1845, H_SPR_DAMLR54 = 1846,
  H_SPR_DAMLR55 = 1847, H_SPR_DAMLR56 = 1848, H_SPR_DAMLR57 = 1849, H_SPR_DAMLR58 = 1850,
  H_SPR_DAMLR59 = 1851, H_SPR_DAMLR60 = 1852, H_SPR_DAMLR61 = 1853, H_SPR_DAMLR62 = 1854,
  H_SPR_DAMLR63 = 1855, H_SPR_DAMPR0 = 1856, H_SPR_DAMPR1 = 1857, H_SPR_DAMPR2 = 1858,
  H_SPR_DAMPR3 = 1859, H_SPR_DAMPR4 = 1860, H_SPR_DAMPR5 = 1861, H_SPR_DAMPR6 = 1862,
  H_SPR_DAMPR7 = 1863, H_SPR_DAMPR8 = 1864, H_SPR_DAMPR9 = 1865, H_SPR_DAMPR10 = 1866,
  H_SPR_DAMPR11 = 1867, H_SPR_DAMPR12 = 1868, H_SPR_DAMPR13 = 1869, H_SPR_DAMPR14 = 1870,
  H_SPR_DAMPR15 = 1871, H_SPR_DAMPR16 = 1872, H_SPR_DAMPR17 = 1873, H_SPR_DAMPR18 = 1874,
  H_SPR_DAMPR19 = 1875, H_SPR_DAMPR20 = 1876, H_SPR_DAMPR21 = 1877, H_SPR_DAMPR22 = 1878,
  H_SPR_DAMPR23 = 1879, H_SPR_DAMPR24 = 1880, H_SPR_DAMPR25 = 1881, H_SPR_DAMPR26 = 1882,
  H_SPR_DAMPR27 = 1883, H_SPR_DAMPR28 = 1884, H_SPR_DAMPR29 = 1885, H_SPR_DAMPR30 = 1886,
  H_SPR_DAMPR31 = 1887, H_SPR_DAMPR32 = 1888, H_SPR_DAMPR33 = 1889, H_SPR_DAMPR34 = 1890,
  H_SPR_DAMPR35 = 1891, H_SPR_DAMPR36 = 1892, H_SPR_DAMPR37 = 1893, H_SPR_DAMPR38 = 1894,
  H_SPR_DAMPR39 = 1895, H_SPR_DAMPR40 = 1896, H_SPR_DAMPR41 = 1897, H_SPR_DAMPR42 = 1898,
  H_SPR_DAMPR43 = 1899, H_SPR_DAMPR44 = 1900, H_SPR_DAMPR45 = 1901, H_SPR_DAMPR46 = 1902,
  H_SPR_DAMPR47 = 1903, H_SPR_DAMPR48 = 1904, H_SPR_DAMPR49 = 1905, H_SPR_DAMPR50 = 1906,
  H_SPR_DAMPR51 = 1907, H_SPR_DAMPR52 = 1908, H_SPR_DAMPR53 = 1909, H_SPR_DAMPR54 = 1910,
  H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912, H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914,
  H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916, H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918,
  H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920, H_SPR_STBAR = 1921, H_SPR_MMCR = 1922,
  H_SPR_IAMVR1 = 1925, H_SPR_DAMVR1 = 1927, H_SPR_CXNR = 1936, H_SPR_TTBR = 1937,
  H_SPR_TPLR = 1938, H_SPR_TPPR = 1939, H_SPR_TPXR = 1940, H_SPR_TIMERH = 1952,
  H_SPR_TIMERL = 1953, H_SPR_TIMERD = 1954, H_SPR_DCR = 2048, H_SPR_BRR = 2049,
  H_SPR_NMAR = 2050, H_SPR_BTBR = 2051, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053,
  H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057,
  H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061,
  H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065,
  H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069,
  H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073,
  H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077,
  H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081,
  H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085,
  H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089,
  H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093,
  H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098,
  H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
}
enum  accg_names {
  H_ACCG_ACCG0, H_ACCG_ACCG1, H_ACCG_ACCG2, H_ACCG_ACCG3,
  H_ACCG_ACCG4, H_ACCG_ACCG5, H_ACCG_ACCG6, H_ACCG_ACCG7,
  H_ACCG_ACCG8, H_ACCG_ACCG9, H_ACCG_ACCG10, H_ACCG_ACCG11,
  H_ACCG_ACCG12, H_ACCG_ACCG13, H_ACCG_ACCG14, H_ACCG_ACCG15,
  H_ACCG_ACCG16, H_ACCG_ACCG17, H_ACCG_ACCG18, H_ACCG_ACCG19,
  H_ACCG_ACCG20, H_ACCG_ACCG21, H_ACCG_ACCG22, H_ACCG_ACCG23,
  H_ACCG_ACCG24, H_ACCG_ACCG25, H_ACCG_ACCG26, H_ACCG_ACCG27,
  H_ACCG_ACCG28, H_ACCG_ACCG29, H_ACCG_ACCG30, H_ACCG_ACCG31,
  H_ACCG_ACCG32, H_ACCG_ACCG33, H_ACCG_ACCG34, H_ACCG_ACCG35,
  H_ACCG_ACCG36, H_ACCG_ACCG37, H_ACCG_ACCG38, H_ACCG_ACCG39,
  H_ACCG_ACCG40, H_ACCG_ACCG41, H_ACCG_ACCG42, H_ACCG_ACCG43,
  H_ACCG_ACCG44, H_ACCG_ACCG45, H_ACCG_ACCG46, H_ACCG_ACCG47,
  H_ACCG_ACCG48, H_ACCG_ACCG49, H_ACCG_ACCG50, H_ACCG_ACCG51,
  H_ACCG_ACCG52, H_ACCG_ACCG53, H_ACCG_ACCG54, H_ACCG_ACCG55,
  H_ACCG_ACCG56, H_ACCG_ACCG57, H_ACCG_ACCG58, H_ACCG_ACCG59,
  H_ACCG_ACCG60, H_ACCG_ACCG61, H_ACCG_ACCG62, H_ACCG_ACCG63
}
enum  acc_names {
  H_ACC40_ACC0, H_ACC40_ACC1, H_ACC40_ACC2, H_ACC40_ACC3,
  H_ACC40_ACC4, H_ACC40_ACC5, H_ACC40_ACC6, H_ACC40_ACC7,
  H_ACC40_ACC8, H_ACC40_ACC9, H_ACC40_ACC10, H_ACC40_ACC11,
  H_ACC40_ACC12, H_ACC40_ACC13, H_ACC40_ACC14, H_ACC40_ACC15,
  H_ACC40_ACC16, H_ACC40_ACC17, H_ACC40_ACC18, H_ACC40_ACC19,
  H_ACC40_ACC20, H_ACC40_ACC21, H_ACC40_ACC22, H_ACC40_ACC23,
  H_ACC40_ACC24, H_ACC40_ACC25, H_ACC40_ACC26, H_ACC40_ACC27,
  H_ACC40_ACC28, H_ACC40_ACC29, H_ACC40_ACC30, H_ACC40_ACC31,
  H_ACC40_ACC32, H_ACC40_ACC33, H_ACC40_ACC34, H_ACC40_ACC35,
  H_ACC40_ACC36, H_ACC40_ACC37, H_ACC40_ACC38, H_ACC40_ACC39,
  H_ACC40_ACC40, H_ACC40_ACC41, H_ACC40_ACC42, H_ACC40_ACC43,
  H_ACC40_ACC44, H_ACC40_ACC45, H_ACC40_ACC46, H_ACC40_ACC47,
  H_ACC40_ACC48, H_ACC40_ACC49, H_ACC40_ACC50, H_ACC40_ACC51,
  H_ACC40_ACC52, H_ACC40_ACC53, H_ACC40_ACC54, H_ACC40_ACC55,
  H_ACC40_ACC56, H_ACC40_ACC57, H_ACC40_ACC58, H_ACC40_ACC59,
  H_ACC40_ACC60, H_ACC40_ACC61, H_ACC40_ACC62, H_ACC40_ACC63
}
enum  iacc0_names { H_IACC0_IACC0 }
enum  iccr_names { H_ICCR_ICC0, H_ICCR_ICC1, H_ICCR_ICC2, H_ICCR_ICC3 }
enum  fccr_names { H_FCCR_FCC0, H_FCCR_FCC1, H_FCCR_FCC2, H_FCCR_FCC3 }
enum  cccr_names {
  H_CCCR_CC0, H_CCCR_CC1, H_CCCR_CC2, H_CCCR_CC3,
  H_CCCR_CC4, H_CCCR_CC5, H_CCCR_CC6, H_CCCR_CC7
}
enum  mach_attr {
  MACH_BASE, MACH_FR30, MACH_MAX, MACH_BASE,
  MACH_FRV, MACH_FR550, MACH_FR500, MACH_FR450,
  MACH_FR400, MACH_TOMCAT, MACH_SIMPLE, MACH_MAX,
  MACH_BASE, MACH_IP2022, MACH_IP2022EXT, MACH_MAX,
  MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX,
  MACH_BASE, MACH_M16C, MACH_M32C, MACH_MAX,
  MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2,
  MACH_MAX, MACH_BASE, MACH_MEP, MACH_H1,
  MACH_MAX, MACH_BASE, MACH_MS1, MACH_MS1_003,
  MACH_MS2, MACH_MAX, MACH_BASE, MACH_OPENRISC,
  MACH_OR1300, MACH_MAX, MACH_BASE, MACH_XC16X,
  MACH_MAX, MACH_BASE, MACH_XSTORMY16, MACH_MAX
}
enum  isa_attr {
  ISA_FR30, ISA_MAX, ISA_FRV, ISA_MAX,
  ISA_IP2K, ISA_MAX, ISA_IQ2000, ISA_MAX,
  ISA_M16C, ISA_M32C, ISA_MAX, ISA_M32R,
  ISA_MAX, ISA_MEP, ISA_EXT_CORE1, ISA_EXT_CORE2,
  ISA_EXT_COP2_16, ISA_EXT_COP2_32, ISA_EXT_COP2_48, ISA_EXT_COP2_64,
  ISA_MAX, ISA_MT, ISA_MAX, ISA_OR32,
  ISA_MAX, ISA_XC16X, ISA_MAX, ISA_XSTORMY16,
  ISA_MAX
}
enum  unit_attr {
  UNIT_NIL, UNIT_I0, UNIT_I1, UNIT_I01,
  UNIT_I2, UNIT_I3, UNIT_IALL, UNIT_FM0,
  UNIT_FM1, UNIT_FM01, UNIT_FM2, UNIT_FM3,
  UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1,
  UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_IACC,
  UNIT_LOAD, UNIT_STORE, UNIT_SCAN, UNIT_DCPL,
  UNIT_MDUALACC, UNIT_MDCUTSSI, UNIT_MCLRACC_1, UNIT_NUM_UNITS
}
enum  fr400_major_attr {
  FR400_MAJOR_NONE, FR400_MAJOR_I_1, FR400_MAJOR_I_2, FR400_MAJOR_I_3,
  FR400_MAJOR_I_4, FR400_MAJOR_I_5, FR400_MAJOR_B_1, FR400_MAJOR_B_2,
  FR400_MAJOR_B_3, FR400_MAJOR_B_4, FR400_MAJOR_B_5, FR400_MAJOR_B_6,
  FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2
}
enum  fr450_major_attr {
  FR450_MAJOR_NONE, FR450_MAJOR_I_1, FR450_MAJOR_I_2, FR450_MAJOR_I_3,
  FR450_MAJOR_I_4, FR450_MAJOR_I_5, FR450_MAJOR_B_1, FR450_MAJOR_B_2,
  FR450_MAJOR_B_3, FR450_MAJOR_B_4, FR450_MAJOR_B_5, FR450_MAJOR_B_6,
  FR450_MAJOR_C_1, FR450_MAJOR_C_2, FR450_MAJOR_M_1, FR450_MAJOR_M_2,
  FR450_MAJOR_M_3, FR450_MAJOR_M_4, FR450_MAJOR_M_5, FR450_MAJOR_M_6
}
enum  fr500_major_attr {
  FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3,
  FR500_MAJOR_I_4, FR500_MAJOR_I_5, FR500_MAJOR_I_6, FR500_MAJOR_B_1,
  FR500_MAJOR_B_2, FR500_MAJOR_B_3, FR500_MAJOR_B_4, FR500_MAJOR_B_5,
  FR500_MAJOR_B_6, FR500_MAJOR_C_1, FR500_MAJOR_C_2, FR500_MAJOR_F_1,
  FR500_MAJOR_F_2, FR500_MAJOR_F_3, FR500_MAJOR_F_4, FR500_MAJOR_F_5,
  FR500_MAJOR_F_6, FR500_MAJOR_F_7, FR500_MAJOR_F_8, FR500_MAJOR_M_1,
  FR500_MAJOR_M_2, FR500_MAJOR_M_3, FR500_MAJOR_M_4, FR500_MAJOR_M_5,
  FR500_MAJOR_M_6, FR500_MAJOR_M_7, FR500_MAJOR_M_8
}
enum  fr550_major_attr {
  FR550_MAJOR_NONE, FR550_MAJOR_I_1, FR550_MAJOR_I_2, FR550_MAJOR_I_3,
  FR550_MAJOR_I_4, FR550_MAJOR_I_5, FR550_MAJOR_I_6, FR550_MAJOR_I_7,
  FR550_MAJOR_I_8, FR550_MAJOR_B_1, FR550_MAJOR_B_2, FR550_MAJOR_B_3,
  FR550_MAJOR_B_4, FR550_MAJOR_B_5, FR550_MAJOR_B_6, FR550_MAJOR_C_1,
  FR550_MAJOR_C_2, FR550_MAJOR_F_1, FR550_MAJOR_F_2, FR550_MAJOR_F_3,
  FR550_MAJOR_F_4, FR550_MAJOR_M_1, FR550_MAJOR_M_2, FR550_MAJOR_M_3,
  FR550_MAJOR_M_4, FR550_MAJOR_M_5
}
enum  cgen_ifld_attr {
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_ISA, CGEN_IFLD_RL_TYPE, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS,
  CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL,
  CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT,
  CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH,
  CGEN_IFLD_ISA, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS,
  CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED,
  CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31,
  CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR,
  CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED,
  CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH,
  CGEN_IFLD_END_NBOOLS, CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR,
  CGEN_IFLD_RESERVED, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS,
  CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
}
enum  ifield_type {
  FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2,
  FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC,
  FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1,
  FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ,
  FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4,
  FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4,
  FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6,
  FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10,
  FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9,
  FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST,
  FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX, FRV_F_NIL,
  FRV_F_ANYOF, FRV_F_PACK, FRV_F_OP, FRV_F_OPE1,
  FRV_F_OPE2, FRV_F_OPE3, FRV_F_OPE4, FRV_F_GRI,
  FRV_F_GRJ, FRV_F_GRK, FRV_F_FRI, FRV_F_FRJ,
  FRV_F_FRK, FRV_F_CPRI, FRV_F_CPRJ, FRV_F_CPRK,
  FRV_F_ACCGI, FRV_F_ACCGK, FRV_F_ACC40SI, FRV_F_ACC40UI,
  FRV_F_ACC40SK, FRV_F_ACC40UK, FRV_F_CRI, FRV_F_CRJ,
  FRV_F_CRK, FRV_F_CCI, FRV_F_CRJ_INT, FRV_F_CRJ_FLOAT,
  FRV_F_ICCI_1, FRV_F_ICCI_2, FRV_F_ICCI_3, FRV_F_FCCI_1,
  FRV_F_FCCI_2, FRV_F_FCCI_3, FRV_F_FCCK, FRV_F_EIR,
  FRV_F_S10, FRV_F_S12, FRV_F_D12, FRV_F_U16,
  FRV_F_S16, FRV_F_S6, FRV_F_S6_1, FRV_F_U6,
  FRV_F_S5, FRV_F_U12_H, FRV_F_U12_L, FRV_F_U12,
  FRV_F_INT_CC, FRV_F_FLT_CC, FRV_F_COND, FRV_F_CCOND,
  FRV_F_HINT, FRV_F_LI, FRV_F_LOCK, FRV_F_DEBUG,
  FRV_F_A, FRV_F_AE, FRV_F_SPR_H, FRV_F_SPR_L,
  FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6, FRV_F_LABELL18,
  FRV_F_LABEL24, FRV_F_LRAE, FRV_F_LRAD, FRV_F_LRAS,
  FRV_F_TLBPROPX, FRV_F_TLBPRL, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL,
  FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL,
  FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL,
  FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL,
  FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL,
  FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4,
  FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8,
  FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LRA_NULL,
  FRV_F_TLBPR_NULL, FRV_F_LI_OFF, FRV_F_LI_ON, FRV_F_RELOC_ANN,
  FRV_F_MAX, IP2K_F_NIL, IP2K_F_ANYOF, IP2K_F_IMM8,
  IP2K_F_REG, IP2K_F_ADDR16CJP, IP2K_F_DIR, IP2K_F_BITNO,
  IP2K_F_OP3, IP2K_F_OP4, IP2K_F_OP4MID, IP2K_F_OP6,
  IP2K_F_OP8, IP2K_F_OP6_10LOW, IP2K_F_OP6_7LOW, IP2K_F_RETI3,
  IP2K_F_SKIPB, IP2K_F_PAGE3, IP2K_F_MAX, IQ2000_F_NIL,
  IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS, IQ2000_F_RT,
  IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP, IQ2000_F_CP_OP_10,
  IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM, IQ2000_F_RD_RS,
  IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG, IQ2000_F_JTARGQ10,
  IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT, IQ2000_F_INDEX,
  IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL, IQ2000_F_EXCODE,
  IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19, IQ2000_F_5,
  IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z, IQ2000_F_CAM_Y,
  IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z, IQ2000_F_CM_4Z,
  IQ2000_F_MAX, M32C_F_NIL, M32C_F_ANYOF, M32C_F_0_1,
  M32C_F_0_2, M32C_F_0_3, M32C_F_0_4, M32C_F_1_3,
  M32C_F_2_2, M32C_F_3_4, M32C_F_3_1, M32C_F_4_1,
  M32C_F_4_3, M32C_F_4_4, M32C_F_4_6, M32C_F_5_1,
  M32C_F_5_3, M32C_F_6_2, M32C_F_7_1, M32C_F_8_1,
  M32C_F_8_2, M32C_F_8_3, M32C_F_8_4, M32C_F_8_8,
  M32C_F_9_3, M32C_F_9_1, M32C_F_10_1, M32C_F_10_2,
  M32C_F_10_3, M32C_F_11_1, M32C_F_12_1, M32C_F_12_2,
  M32C_F_12_3, M32C_F_12_4, M32C_F_12_6, M32C_F_13_3,
  M32C_F_14_1, M32C_F_14_2, M32C_F_15_1, M32C_F_16_1,
  M32C_F_16_2, M32C_F_16_4, M32C_F_16_8, M32C_F_18_1,
  M32C_F_18_2, M32C_F_18_3, M32C_F_20_1, M32C_F_20_3,
  M32C_F_20_2, M32C_F_20_4, M32C_F_21_3, M32C_F_24_2,
  M32C_F_24_8, M32C_F_32_16, M32C_F_SRC16_RN, M32C_F_SRC16_AN,
  M32C_F_SRC32_AN_UNPREFIXED, M32C_F_SRC32_AN_PREFIXED, M32C_F_SRC32_RN_UNPREFIXED_QI, M32C_F_SRC32_RN_PREFIXED_QI,
  M32C_F_SRC32_RN_UNPREFIXED_HI, M32C_F_SRC32_RN_PREFIXED_HI, M32C_F_SRC32_RN_UNPREFIXED_SI, M32C_F_SRC32_RN_PREFIXED_SI,
  M32C_F_DST32_RN_EXT_UNPREFIXED, M32C_F_DST16_RN, M32C_F_DST16_RN_EXT, M32C_F_DST16_RN_QI_S,
  M32C_F_DST16_AN, M32C_F_DST16_AN_S, M32C_F_DST32_AN_UNPREFIXED, M32C_F_DST32_AN_PREFIXED,
  M32C_F_DST32_RN_UNPREFIXED_QI, M32C_F_DST32_RN_PREFIXED_QI, M32C_F_DST32_RN_UNPREFIXED_HI, M32C_F_DST32_RN_PREFIXED_HI,
  M32C_F_DST32_RN_UNPREFIXED_SI, M32C_F_DST32_RN_PREFIXED_SI, M32C_F_DST16_1_S, M32C_F_IMM_8_S4,
  M32C_F_IMM_12_S4, M32C_F_IMM_13_U3, M32C_F_IMM_20_S4, M32C_F_IMM1_S,
  M32C_F_IMM3_S, M32C_F_DSP_8_U6, M32C_F_DSP_8_U8, M32C_F_DSP_8_S8,
  M32C_F_DSP_10_U6, M32C_F_DSP_16_U8, M32C_F_DSP_16_S8, M32C_F_DSP_24_U8,
  M32C_F_DSP_24_S8, M32C_F_DSP_32_U8, M32C_F_DSP_32_S8, M32C_F_DSP_40_U8,
  M32C_F_DSP_40_S8, M32C_F_DSP_48_U8, M32C_F_DSP_48_S8, M32C_F_DSP_56_U8,
  M32C_F_DSP_56_S8, M32C_F_DSP_64_U8, M32C_F_DSP_64_S8, M32C_F_DSP_8_U16,
  M32C_F_DSP_8_S16, M32C_F_DSP_16_U16, M32C_F_DSP_16_S16, M32C_F_DSP_24_U16,
  M32C_F_DSP_24_S16, M32C_F_DSP_32_U16, M32C_F_DSP_32_S16, M32C_F_DSP_40_U16,
  M32C_F_DSP_40_S16, M32C_F_DSP_48_U16, M32C_F_DSP_48_S16, M32C_F_DSP_64_U16,
  M32C_F_DSP_8_S24, M32C_F_DSP_8_U24, M32C_F_DSP_16_U24, M32C_F_DSP_24_U24,
  M32C_F_DSP_32_U24, M32C_F_DSP_40_U20, M32C_F_DSP_40_U24, M32C_F_DSP_40_S32,
  M32C_F_DSP_48_U20, M32C_F_DSP_48_U24, M32C_F_DSP_16_S32, M32C_F_DSP_24_S32,
  M32C_F_DSP_32_S32, M32C_F_DSP_48_U32, M32C_F_DSP_48_S32, M32C_F_DSP_56_S16,
  M32C_F_DSP_64_S16, M32C_F_BITNO16_S, M32C_F_BITNO32_PREFIXED, M32C_F_BITNO32_UNPREFIXED,
  M32C_F_BITBASE16_U11_S, M32C_F_BITBASE32_16_U11_UNPREFIXED, M32C_F_BITBASE32_16_S11_UNPREFIXED, M32C_F_BITBASE32_16_U19_UNPREFIXED,
  M32C_F_BITBASE32_16_S19_UNPREFIXED, M32C_F_BITBASE32_16_U27_UNPREFIXED, M32C_F_BITBASE32_24_U11_PREFIXED, M32C_F_BITBASE32_24_S11_PREFIXED,
  M32C_F_BITBASE32_24_U19_PREFIXED, M32C_F_BITBASE32_24_S19_PREFIXED, M32C_F_BITBASE32_24_U27_PREFIXED, M32C_F_LAB_5_3,
  M32C_F_LAB32_JMP_S, M32C_F_LAB_8_8, M32C_F_LAB_8_16, M32C_F_LAB_8_24,
  M32C_F_LAB_16_8, M32C_F_LAB_24_8, M32C_F_LAB_32_8, M32C_F_LAB_40_8,
  M32C_F_COND16, M32C_F_COND16J_5, M32C_F_COND32, M32C_F_COND32J,
  M32C_F_MAX, M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1,
  M32R_F_OP2, M32R_F_COND, M32R_F_R1, M32R_F_R2,
  M32R_F_SIMM8, M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3,
  M32R_F_UIMM4, M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16,
  M32R_F_UIMM24, M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16,
  M32R_F_DISP24, M32R_F_OP23, M32R_F_OP3, M32R_F_ACC,
  M32R_F_ACCS, M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4,
  M32R_F_BIT14, M32R_F_IMM1, M32R_F_MAX, MEP_F_NIL,
  MEP_F_ANYOF, MEP_F_MAJOR, MEP_F_RN, MEP_F_RN3,
  MEP_F_RM, MEP_F_RL, MEP_F_SUB2, MEP_F_SUB3,
  MEP_F_SUB4, MEP_F_EXT, MEP_F_CRN, MEP_F_CSRN_HI,
  MEP_F_CSRN_LO, MEP_F_CSRN, MEP_F_CRNX_HI, MEP_F_CRNX_LO,
  MEP_F_CRNX, MEP_F_0, MEP_F_1, MEP_F_2,
  MEP_F_3, MEP_F_4, MEP_F_5, MEP_F_6,
  MEP_F_7, MEP_F_8, MEP_F_9, MEP_F_10,
  MEP_F_11, MEP_F_12, MEP_F_13, MEP_F_14,
  MEP_F_15, MEP_F_16, MEP_F_17, MEP_F_18,
  MEP_F_19, MEP_F_20, MEP_F_21, MEP_F_22,
  MEP_F_23, MEP_F_24, MEP_F_25, MEP_F_26,
  MEP_F_27, MEP_F_28, MEP_F_29, MEP_F_30,
  MEP_F_31, MEP_F_8S8A2, MEP_F_12S4A2, MEP_F_17S16A2,
  MEP_F_24S5A2N_HI, MEP_F_24S5A2N_LO, MEP_F_24S5A2N, MEP_F_24U5A2N_HI,
  MEP_F_24U5A2N_LO, MEP_F_24U5A2N, MEP_F_2U6, MEP_F_7U9,
  MEP_F_7U9A2, MEP_F_7U9A4, MEP_F_16S16, MEP_F_2U10,
  MEP_F_3U5, MEP_F_4U8, MEP_F_5U8, MEP_F_5U24,
  MEP_F_6S8, MEP_F_8S8, MEP_F_16U16, MEP_F_12U16,
  MEP_F_3U29, MEP_F_8S24, MEP_F_8S24A2, MEP_F_8S24A4,
  MEP_F_8S24A8, MEP_F_24U8A4N_HI, MEP_F_24U8A4N_LO, MEP_F_24U8A4N,
  MEP_F_24U8N_HI, MEP_F_24U8N_LO, MEP_F_24U8N, MEP_F_24U4N_HI,
  MEP_F_24U4N_LO, MEP_F_24U4N, MEP_F_CALLNUM, MEP_F_CCRN_HI,
  MEP_F_CCRN_LO, MEP_F_CCRN, MEP_F_FMAX_0_4, MEP_F_FMAX_4_4,
  MEP_F_FMAX_8_4, MEP_F_FMAX_12_4, MEP_F_FMAX_16_4, MEP_F_FMAX_20_4,
  MEP_F_FMAX_24_4, MEP_F_FMAX_28_1, MEP_F_FMAX_29_1, MEP_F_FMAX_30_1,
  MEP_F_FMAX_31_1, MEP_F_FMAX_FRD, MEP_F_FMAX_FRN, MEP_F_FMAX_FRM,
  MEP_F_FMAX_RM, MEP_F_MAX, MT_F_NIL, MT_F_ANYOF,
  MT_F_MSYS, MT_F_OPC, MT_F_IMM, MT_F_UU24,
  MT_F_SR1, MT_F_SR2, MT_F_DR, MT_F_DRRR,
  MT_F_IMM16U, MT_F_IMM16S, MT_F_IMM16A, MT_F_UU4A,
  MT_F_UU4B, MT_F_UU12, MT_F_UU8, MT_F_UU16,
  MT_F_UU1, MT_F_MSOPC, MT_F_UU_26_25, MT_F_MASK,
  MT_F_BANKADDR, MT_F_RDA, MT_F_UU_2_25, MT_F_RBBC,
  MT_F_PERM, MT_F_MODE, MT_F_UU_1_24, MT_F_WR,
  MT_F_FBINCR, MT_F_UU_2_23, MT_F_XMODE, MT_F_A23,
  MT_F_MASK1, MT_F_CR, MT_F_TYPE, MT_F_INCAMT,
  MT_F_CBS, MT_F_UU_1_19, MT_F_BALL, MT_F_COLNUM,
  MT_F_BRC, MT_F_INCR, MT_F_FBDISP, MT_F_UU_4_15,
  MT_F_LENGTH, MT_F_UU_1_15, MT_F_RC, MT_F_RCNUM,
  MT_F_ROWNUM, MT_F_CBX, MT_F_ID, MT_F_SIZE,
  MT_F_ROWNUM1, MT_F_UU_3_11, MT_F_RC1, MT_F_CCB,
  MT_F_CBRB, MT_F_CDB, MT_F_ROWNUM2, MT_F_CELL,
  MT_F_UU_3_9, MT_F_CONTNUM, MT_F_UU_1_6, MT_F_DUP,
  MT_F_RC2, MT_F_CTXDISP, MT_F_IMM16L, MT_F_LOOPO,
  MT_F_CB1SEL, MT_F_CB2SEL, MT_F_CB1INCR, MT_F_CB2INCR,
  MT_F_RC3, MT_F_MSYSFRSR2, MT_F_BRC2, MT_F_BALL2,
  MT_F_MAX, OPENRISC_F_NIL, OPENRISC_F_ANYOF, OPENRISC_F_CLASS,
  OPENRISC_F_SUB, OPENRISC_F_R1, OPENRISC_F_R2, OPENRISC_F_R3,
  OPENRISC_F_SIMM16, OPENRISC_F_UIMM16, OPENRISC_F_UIMM5, OPENRISC_F_HI16,
  OPENRISC_F_LO16, OPENRISC_F_OP1, OPENRISC_F_OP2, OPENRISC_F_OP3,
  OPENRISC_F_OP4, OPENRISC_F_OP5, OPENRISC_F_OP6, OPENRISC_F_OP7,
  OPENRISC_F_I16_1, OPENRISC_F_I16_2, OPENRISC_F_DISP26, OPENRISC_F_ABS26,
  OPENRISC_F_I16NC, OPENRISC_F_F_15_8, OPENRISC_F_F_10_3, OPENRISC_F_F_4_1,
  OPENRISC_F_F_7_3, OPENRISC_F_F_10_7, OPENRISC_F_F_10_11, OPENRISC_F_MAX,
  XC16X_F_NIL, XC16X_F_ANYOF, XC16X_F_OP1, XC16X_F_OP2,
  XC16X_F_CONDCODE, XC16X_F_ICONDCODE, XC16X_F_RCOND, XC16X_F_QCOND,
  XC16X_F_EXTCCODE, XC16X_F_R0, XC16X_F_R1, XC16X_F_R2,
  XC16X_F_R3, XC16X_F_R4, XC16X_F_UIMM2, XC16X_F_UIMM3,
  XC16X_F_UIMM4, XC16X_F_UIMM7, XC16X_F_UIMM8, XC16X_F_UIMM16,
  XC16X_F_MEMORY, XC16X_F_MEMGR8, XC16X_F_REL8, XC16X_F_RELHI8,
  XC16X_F_REG8, XC16X_F_REGMEM8, XC16X_F_REGOFF8, XC16X_F_REGHI8,
  XC16X_F_REGB8, XC16X_F_SEG8, XC16X_F_SEGNUM8, XC16X_F_MASK8,
  XC16X_F_PAGENUM, XC16X_F_DATAHI8, XC16X_F_DATA8, XC16X_F_OFFSET16,
  XC16X_F_OP_BIT1, XC16X_F_OP_BIT2, XC16X_F_OP_BIT4, XC16X_F_OP_BIT3,
  XC16X_F_OP_2BIT, XC16X_F_OP_BITONE, XC16X_F_OP_ONEBIT, XC16X_F_OP_1BIT,
  XC16X_F_OP_LBIT4, XC16X_F_OP_LBIT2, XC16X_F_OP_BIT8, XC16X_F_OP_BIT16,
  XC16X_F_QBIT, XC16X_F_QLOBIT, XC16X_F_QHIBIT, XC16X_F_QLOBIT2,
  XC16X_F_POF, XC16X_F_MAX, XSTORMY16_F_NIL, XSTORMY16_F_ANYOF,
  XSTORMY16_F_RD, XSTORMY16_F_RDM, XSTORMY16_F_RM, XSTORMY16_F_RS,
  XSTORMY16_F_RB, XSTORMY16_F_RBJ, XSTORMY16_F_OP1, XSTORMY16_F_OP2,
  XSTORMY16_F_OP2A, XSTORMY16_F_OP2M, XSTORMY16_F_OP3, XSTORMY16_F_OP3A,
  XSTORMY16_F_OP3B, XSTORMY16_F_OP4, XSTORMY16_F_OP4M, XSTORMY16_F_OP4B,
  XSTORMY16_F_OP5, XSTORMY16_F_OP5A, XSTORMY16_F_OP, XSTORMY16_F_IMM2,
  XSTORMY16_F_IMM3, XSTORMY16_F_IMM3B, XSTORMY16_F_IMM4, XSTORMY16_F_IMM8,
  XSTORMY16_F_IMM12, XSTORMY16_F_IMM16, XSTORMY16_F_LMEM8, XSTORMY16_F_HMEM8,
  XSTORMY16_F_REL8_2, XSTORMY16_F_REL8_4, XSTORMY16_F_REL12, XSTORMY16_F_REL12A,
  XSTORMY16_F_ABS24_1, XSTORMY16_F_ABS24_2, XSTORMY16_F_ABS24, XSTORMY16_F_MAX
}
enum  cgen_hw_attr {
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA,
  CGEN_HW_RL_TYPE, CGEN_HW_END_NBOOLS, CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR,
  CGEN_HW_PC, CGEN_HW_PROFILE, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31,
  CGEN_HW_MACH, CGEN_HW_END_NBOOLS, CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR,
  CGEN_HW_PC, CGEN_HW_PROFILE, CGEN_HW_IS_FLOAT, CGEN_HW_END_BOOLS,
  CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_ISA, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS,
  CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE,
  CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
}
enum  cgen_hw_type {
  CGEN_HW_MAX, HW_H_MEMORY, HW_H_SINT, HW_H_UINT,
  HW_H_ADDR, HW_H_IADDR, HW_H_PC, HW_H_GR,
  HW_H_CR, HW_H_DR, HW_H_PS, HW_H_R13,
  HW_H_R14, HW_H_R15, HW_H_NBIT, HW_H_ZBIT,
  HW_H_VBIT, HW_H_CBIT, HW_H_IBIT, HW_H_SBIT,
  HW_H_TBIT, HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR,
  HW_H_SCR, HW_H_ILM, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_RELOC_ANN, HW_H_PC, HW_H_PSR_IMPLE, HW_H_PSR_VER,
  HW_H_PSR_ICE, HW_H_PSR_NEM, HW_H_PSR_CM, HW_H_PSR_BE,
  HW_H_PSR_ESR, HW_H_PSR_EF, HW_H_PSR_EM, HW_H_PSR_PIL,
  HW_H_PSR_PS, HW_H_PSR_ET, HW_H_PSR_S, HW_H_TBR_TBA,
  HW_H_TBR_TT, HW_H_BPSR_BS, HW_H_BPSR_BET, HW_H_GR,
  HW_H_GR_DOUBLE, HW_H_GR_HI, HW_H_GR_LO, HW_H_FR,
  HW_H_FR_DOUBLE, HW_H_FR_INT, HW_H_FR_HI, HW_H_FR_LO,
  HW_H_FR_0, HW_H_FR_1, HW_H_FR_2, HW_H_FR_3,
  HW_H_CPR, HW_H_CPR_DOUBLE, HW_H_SPR, HW_H_ACCG,
  HW_H_ACC40S, HW_H_ACC40U, HW_H_IACC0, HW_H_ICCR,
  HW_H_FCCR, HW_H_CCCR, HW_H_PACK, HW_H_HINT_TAKEN,
  HW_H_HINT_NOT_TAKEN, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_SPR,
  HW_H_REGISTERS, HW_H_STACK, HW_H_PABITS, HW_H_ZBIT,
  HW_H_CBIT, HW_H_DCBIT, HW_H_PC, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_GR_QI,
  HW_H_GR_HI, HW_H_GR_SI, HW_H_GR_EXT_QI, HW_H_GR_EXT_HI,
  HW_H_R0L, HW_H_R0H, HW_H_R1L, HW_H_R1H,
  HW_H_R0, HW_H_R1, HW_H_R2, HW_H_R3,
  HW_H_R0L_R0H, HW_H_R2R0, HW_H_R3R1, HW_H_R1R2R0,
  HW_H_AR, HW_H_AR_QI, HW_H_AR_HI, HW_H_AR_SI,
  HW_H_A0, HW_H_A1, HW_H_SB, HW_H_FB,
  HW_H_SP, HW_H_SBIT, HW_H_ZBIT, HW_H_OBIT,
  HW_H_CBIT, HW_H_UBIT, HW_H_IBIT, HW_H_BBIT,
  HW_H_DBIT, HW_H_DCT0, HW_H_DCT1, HW_H_SVF,
  HW_H_DRC0, HW_H_DRC1, HW_H_DMD0, HW_H_DMD1,
  HW_H_INTB, HW_H_SVP, HW_H_VCT, HW_H_ISP,
  HW_H_DMA0, HW_H_DMA1, HW_H_DRA0, HW_H_DRA1,
  HW_H_DSA0, HW_H_DSA1, HW_H_COND16, HW_H_COND16C,
  HW_H_COND16J, HW_H_COND16J_5, HW_H_COND32, HW_H_CR1_32,
  HW_H_CR2_32, HW_H_CR3_32, HW_H_CR_16, HW_H_FLAGS,
  HW_H_SHIMM, HW_H_BIT_INDEX, HW_H_SRC_INDEX, HW_H_DST_INDEX,
  HW_H_SRC_INDIRECT, HW_H_DST_INDIRECT, HW_H_NONE, HW_MAX,
  HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR,
  HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16,
  HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM,
  HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW,
  HW_H_BBPSW, HW_H_LOCK, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GPR, HW_H_CSR, HW_H_CR64,
  HW_H_CR, HW_H_CCR, HW_H_CR_FMAX, HW_H_CCR_FMAX,
  HW_H_FMAX_COMPARE_I_P, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_SPR,
  HW_H_PC, HW_MAX, HW_H_MEMORY, HW_H_SINT,
  HW_H_UINT, HW_H_ADDR, HW_H_IADDR, HW_H_PC,
  HW_H_GR, HW_H_SR, HW_H_HI16, HW_H_LO16,
  HW_H_CBIT, HW_H_DELAY_INSN, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GR, HW_H_EXT, HW_H_PSW,
  HW_H_GRB, HW_H_CC, HW_H_ECC, HW_H_GRB8,
  HW_H_R8, HW_H_REGMEM8, HW_H_REGDIV8, HW_H_R0,
  HW_H_R01, HW_H_REGBMEM8, HW_H_MEMGR8, HW_H_COND,
  HW_H_CBIT, HW_H_SGTDIS, HW_MAX, HW_H_MEMORY,
  HW_H_SINT, HW_H_UINT, HW_H_ADDR, HW_H_IADDR,
  HW_H_PC, HW_H_GR, HW_H_RB, HW_H_RBJ,
  HW_H_RPSW, HW_H_Z8, HW_H_Z16, HW_H_CY,
  HW_H_HC, HW_H_OV, HW_H_PT, HW_H_S,
  HW_H_BRANCHCOND, HW_H_WORDSIZE, HW_MAX
}
enum  cgen_operand_attr {
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT,
  CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY,
  CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH,
  CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR,
  CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX,
  CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_ISA, CGEN_OPERAND_RL_TYPE, CGEN_OPERAND_END_NBOOLS,
  CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT,
  CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY,
  CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW, CGEN_OPERAND_END_BOOLS,
  CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_ISA, CGEN_OPERAND_CDATA,
  CGEN_OPERAND_ALIGN, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31,
  CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR,
  CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE,
  CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX,
  CGEN_OPERAND_DOT_PREFIX, CGEN_OPERAND_POF_PREFIX, CGEN_OPERAND_PAG_PREFIX, CGEN_OPERAND_SOF_PREFIX,
  CGEN_OPERAND_SEG_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH,
  CGEN_OPERAND_END_NBOOLS, CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR,
  CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX,
  CGEN_OPERAND_SEM_ONLY, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH,
  CGEN_OPERAND_END_NBOOLS
}
enum  cgen_operand_type {
  CGEN_OPERAND_MAX, FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ,
  FR30_OPERAND_RIC, FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ,
  FR30_OPERAND_RS1, FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14,
  FR30_OPERAND_R15, FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C,
  FR30_OPERAND_U8, FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8,
  FR30_OPERAND_DISP9, FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10,
  FR30_OPERAND_I32, FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8,
  FR30_OPERAND_DIR9, FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12,
  FR30_OPERAND_REGLIST_LOW_LD, FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST,
  FR30_OPERAND_CC, FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT,
  FR30_OPERAND_ZBIT, FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT,
  FR30_OPERAND_TBIT, FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR,
  FR30_OPERAND_SCR, FR30_OPERAND_ILM, FR30_OPERAND_MAX, FRV_OPERAND_PC,
  FRV_OPERAND_PACK, FRV_OPERAND_GRI, FRV_OPERAND_GRJ, FRV_OPERAND_GRK,
  FRV_OPERAND_GRKHI, FRV_OPERAND_GRKLO, FRV_OPERAND_GRDOUBLEK, FRV_OPERAND_ACC40SI,
  FRV_OPERAND_ACC40UI, FRV_OPERAND_ACC40SK, FRV_OPERAND_ACC40UK, FRV_OPERAND_ACCGI,
  FRV_OPERAND_ACCGK, FRV_OPERAND_CPRI, FRV_OPERAND_CPRJ, FRV_OPERAND_CPRK,
  FRV_OPERAND_CPRDOUBLEK, FRV_OPERAND_FRINTI, FRV_OPERAND_FRINTJ, FRV_OPERAND_FRINTK,
  FRV_OPERAND_FRI, FRV_OPERAND_FRJ, FRV_OPERAND_FRK, FRV_OPERAND_FRKHI,
  FRV_OPERAND_FRKLO, FRV_OPERAND_FRDOUBLEI, FRV_OPERAND_FRDOUBLEJ, FRV_OPERAND_FRDOUBLEK,
  FRV_OPERAND_CRI, FRV_OPERAND_CRJ, FRV_OPERAND_CRJ_INT, FRV_OPERAND_CRJ_FLOAT,
  FRV_OPERAND_CRK, FRV_OPERAND_CCI, FRV_OPERAND_ICCI_1, FRV_OPERAND_ICCI_2,
  FRV_OPERAND_ICCI_3, FRV_OPERAND_FCCI_1, FRV_OPERAND_FCCI_2, FRV_OPERAND_FCCI_3,
  FRV_OPERAND_FCCK, FRV_OPERAND_EIR, FRV_OPERAND_S10, FRV_OPERAND_U16,
  FRV_OPERAND_S16, FRV_OPERAND_S6, FRV_OPERAND_S6_1, FRV_OPERAND_U6,
  FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND, FRV_OPERAND_HINT,
  FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI, FRV_OPERAND_LOCK,
  FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16, FRV_OPERAND_LRAE,
  FRV_OPERAND_LRAD, FRV_OPERAND_LRAS, FRV_OPERAND_TLBPROPX, FRV_OPERAND_TLBPRL,
  FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN,
  FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12, FRV_OPERAND_U12,
  FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16, FRV_OPERAND_UHI16,
  FRV_OPERAND_LABEL24, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS,
  FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA,
  FRV_OPERAND_TBR_TT, FRV_OPERAND_LDANN, FRV_OPERAND_LDDANN, FRV_OPERAND_CALLANN,
  FRV_OPERAND_MAX, IP2K_OPERAND_PC, IP2K_OPERAND_ADDR16CJP, IP2K_OPERAND_FR,
  IP2K_OPERAND_LIT8, IP2K_OPERAND_BITNO, IP2K_OPERAND_ADDR16P, IP2K_OPERAND_ADDR16H,
  IP2K_OPERAND_ADDR16L, IP2K_OPERAND_RETI3, IP2K_OPERAND_PABITS, IP2K_OPERAND_ZBIT,
  IP2K_OPERAND_CBIT, IP2K_OPERAND_DCBIT, IP2K_OPERAND_MAX, IQ2000_OPERAND_PC,
  IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD, IQ2000_OPERAND_RD_RS,
  IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT, IQ2000_OPERAND_IMM,
  IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG, IQ2000_OPERAND_MASK,
  IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT, IQ2000_OPERAND__INDEX,
  IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y, IQ2000_OPERAND_CAM_Z,
  IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z, IQ2000_OPERAND_CM_4Z,
  IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM, IQ2000_OPERAND_HI16,
  IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10, IQ2000_OPERAND_MAX,
  M32C_OPERAND_PC, M32C_OPERAND_SRC16RNQI, M32C_OPERAND_SRC16RNHI, M32C_OPERAND_SRC32RNUNPREFIXEDQI,
  M32C_OPERAND_SRC32RNUNPREFIXEDHI, M32C_OPERAND_SRC32RNUNPREFIXEDSI, M32C_OPERAND_SRC32RNPREFIXEDQI, M32C_OPERAND_SRC32RNPREFIXEDHI,
  M32C_OPERAND_SRC32RNPREFIXEDSI, M32C_OPERAND_SRC16AN, M32C_OPERAND_SRC16ANQI, M32C_OPERAND_SRC16ANHI,
  M32C_OPERAND_SRC32ANUNPREFIXED, M32C_OPERAND_SRC32ANUNPREFIXEDQI, M32C_OPERAND_SRC32ANUNPREFIXEDHI, M32C_OPERAND_SRC32ANUNPREFIXEDSI,
  M32C_OPERAND_SRC32ANPREFIXED, M32C_OPERAND_SRC32ANPREFIXEDQI, M32C_OPERAND_SRC32ANPREFIXEDHI, M32C_OPERAND_SRC32ANPREFIXEDSI,
  M32C_OPERAND_DST16RNQI, M32C_OPERAND_DST16RNHI, M32C_OPERAND_DST16RNSI, M32C_OPERAND_DST16RNEXTQI,
  M32C_OPERAND_DST32R0QI_S, M32C_OPERAND_DST32R0HI_S, M32C_OPERAND_DST32RNUNPREFIXEDQI, M32C_OPERAND_DST32RNUNPREFIXEDHI,
  M32C_OPERAND_DST32RNUNPREFIXEDSI, M32C_OPERAND_DST32RNEXTUNPREFIXEDQI, M32C_OPERAND_DST32RNEXTUNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDQI,
  M32C_OPERAND_DST32RNPREFIXEDHI, M32C_OPERAND_DST32RNPREFIXEDSI, M32C_OPERAND_DST16RNQI_S, M32C_OPERAND_DST16ANQI_S,
  M32C_OPERAND_BIT16RN, M32C_OPERAND_BIT32RNPREFIXED, M32C_OPERAND_BIT32RNUNPREFIXED, M32C_OPERAND_R0,
  M32C_OPERAND_R1, M32C_OPERAND_R2, M32C_OPERAND_R3, M32C_OPERAND_R0L,
  M32C_OPERAND_R0H, M32C_OPERAND_R2R0, M32C_OPERAND_R3R1, M32C_OPERAND_R1R2R0,
  M32C_OPERAND_DST16AN, M32C_OPERAND_DST16ANQI, M32C_OPERAND_DST16ANHI, M32C_OPERAND_DST16ANSI,
  M32C_OPERAND_DST16AN_S, M32C_OPERAND_DST32ANUNPREFIXED, M32C_OPERAND_DST32ANUNPREFIXEDQI, M32C_OPERAND_DST32ANUNPREFIXEDHI,
  M32C_OPERAND_DST32ANUNPREFIXEDSI, M32C_OPERAND_DST32ANEXTUNPREFIXED, M32C_OPERAND_DST32ANPREFIXED, M32C_OPERAND_DST32ANPREFIXEDQI,
  M32C_OPERAND_DST32ANPREFIXEDHI, M32C_OPERAND_DST32ANPREFIXEDSI, M32C_OPERAND_BIT16AN, M32C_OPERAND_BIT32ANPREFIXED,
  M32C_OPERAND_BIT32ANUNPREFIXED, M32C_OPERAND_A0, M32C_OPERAND_A1, M32C_OPERAND_SB,
  M32C_OPERAND_FB, M32C_OPERAND_SP, M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL, M32C_OPERAND_REGSETPOP,
  M32C_OPERAND_REGSETPUSH, M32C_OPERAND_RN16_PUSH_S, M32C_OPERAND_AN16_PUSH_S, M32C_OPERAND_DSP_8_U6,
  M32C_OPERAND_DSP_8_U8, M32C_OPERAND_DSP_8_U16, M32C_OPERAND_DSP_8_S8, M32C_OPERAND_DSP_8_S24,
  M32C_OPERAND_DSP_8_U24, M32C_OPERAND_DSP_10_U6, M32C_OPERAND_DSP_16_U8, M32C_OPERAND_DSP_16_U16,
  M32C_OPERAND_DSP_16_U20, M32C_OPERAND_DSP_16_U24, M32C_OPERAND_DSP_16_S8, M32C_OPERAND_DSP_16_S16,
  M32C_OPERAND_DSP_24_U8, M32C_OPERAND_DSP_24_U16, M32C_OPERAND_DSP_24_U20, M32C_OPERAND_DSP_24_U24,
  M32C_OPERAND_DSP_24_S8, M32C_OPERAND_DSP_24_S16, M32C_OPERAND_DSP_32_U8, M32C_OPERAND_DSP_32_U16,
  M32C_OPERAND_DSP_32_U24, M32C_OPERAND_DSP_32_U20, M32C_OPERAND_DSP_32_S8, M32C_OPERAND_DSP_32_S16,
  M32C_OPERAND_DSP_40_U8, M32C_OPERAND_DSP_40_S8, M32C_OPERAND_DSP_40_U16, M32C_OPERAND_DSP_40_S16,
  M32C_OPERAND_DSP_40_U20, M32C_OPERAND_DSP_40_U24, M32C_OPERAND_DSP_48_U8, M32C_OPERAND_DSP_48_S8,
  M32C_OPERAND_DSP_48_U16, M32C_OPERAND_DSP_48_S16, M32C_OPERAND_DSP_48_U20, M32C_OPERAND_DSP_48_U24,
  M32C_OPERAND_IMM_8_S4, M32C_OPERAND_IMM_8_S4N, M32C_OPERAND_IMM_SH_8_S4, M32C_OPERAND_IMM_8_QI,
  M32C_OPERAND_IMM_8_HI, M32C_OPERAND_IMM_12_S4, M32C_OPERAND_IMM_12_S4N, M32C_OPERAND_IMM_SH_12_S4,
  M32C_OPERAND_IMM_13_U3, M32C_OPERAND_IMM_20_S4, M32C_OPERAND_IMM_SH_20_S4, M32C_OPERAND_IMM_16_QI,
  M32C_OPERAND_IMM_16_HI, M32C_OPERAND_IMM_16_SI, M32C_OPERAND_IMM_24_QI, M32C_OPERAND_IMM_24_HI,
  M32C_OPERAND_IMM_24_SI, M32C_OPERAND_IMM_32_QI, M32C_OPERAND_IMM_32_SI, M32C_OPERAND_IMM_32_HI,
  M32C_OPERAND_IMM_40_QI, M32C_OPERAND_IMM_40_HI, M32C_OPERAND_IMM_40_SI, M32C_OPERAND_IMM_48_QI,
  M32C_OPERAND_IMM_48_HI, M32C_OPERAND_IMM_48_SI, M32C_OPERAND_IMM_56_QI, M32C_OPERAND_IMM_56_HI,
  M32C_OPERAND_IMM_64_HI, M32C_OPERAND_IMM1_S, M32C_OPERAND_IMM3_S, M32C_OPERAND_BIT3_S,
  M32C_OPERAND_BITNO16R, M32C_OPERAND_BITNO32PREFIXED, M32C_OPERAND_BITNO32UNPREFIXED, M32C_OPERAND_BITBASE16_16_U8,
  M32C_OPERAND_BITBASE16_16_S8, M32C_OPERAND_BITBASE16_16_U16, M32C_OPERAND_BITBASE16_8_U11_S, M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED,
  M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED, M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED,
  M32C_OPERAND_BITBASE32_24_U11_PREFIXED, M32C_OPERAND_BITBASE32_24_S11_PREFIXED, M32C_OPERAND_BITBASE32_24_U19_PREFIXED, M32C_OPERAND_BITBASE32_24_S19_PREFIXED,
  M32C_OPERAND_BITBASE32_24_U27_PREFIXED, M32C_OPERAND_LAB_5_3, M32C_OPERAND_LAB32_JMP_S, M32C_OPERAND_LAB_8_8,
  M32C_OPERAND_LAB_8_16, M32C_OPERAND_LAB_8_24, M32C_OPERAND_LAB_16_8, M32C_OPERAND_LAB_24_8,
  M32C_OPERAND_LAB_32_8, M32C_OPERAND_LAB_40_8, M32C_OPERAND_SBIT, M32C_OPERAND_OBIT,
  M32C_OPERAND_ZBIT, M32C_OPERAND_CBIT, M32C_OPERAND_UBIT, M32C_OPERAND_IBIT,
  M32C_OPERAND_BBIT, M32C_OPERAND_DBIT, M32C_OPERAND_COND16_16, M32C_OPERAND_COND16_24,
  M32C_OPERAND_COND16_32, M32C_OPERAND_COND32_16, M32C_OPERAND_COND32_24, M32C_OPERAND_COND32_32,
  M32C_OPERAND_COND32_40, M32C_OPERAND_COND16C, M32C_OPERAND_COND16J, M32C_OPERAND_COND16J5,
  M32C_OPERAND_COND32, M32C_OPERAND_COND32J, M32C_OPERAND_SCCOND32, M32C_OPERAND_FLAGS16,
  M32C_OPERAND_FLAGS32, M32C_OPERAND_CR16, M32C_OPERAND_CR1_UNPREFIXED_32, M32C_OPERAND_CR1_PREFIXED_32,
  M32C_OPERAND_CR2_32, M32C_OPERAND_CR3_UNPREFIXED_32, M32C_OPERAND_CR3_PREFIXED_32, M32C_OPERAND_Z,
  M32C_OPERAND_S, M32C_OPERAND_Q, M32C_OPERAND_G, M32C_OPERAND_X,
  M32C_OPERAND_SIZE, M32C_OPERAND_BITINDEX, M32C_OPERAND_SRCINDEX, M32C_OPERAND_DSTINDEX,
  M32C_OPERAND_NOREMAINDER, M32C_OPERAND_SRC16_RN_DIRECT_QI, M32C_OPERAND_SRC16_RN_DIRECT_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_SRC32_RN_DIRECT_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_RN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_DIRECT_QI, M32C_OPERAND_SRC16_AN_DIRECT_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_HI,
  M32C_OPERAND_SRC32_AN_DIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_AN_INDIRECT_QI, M32C_OPERAND_SRC16_AN_INDIRECT_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_SRC32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_HI,
  M32C_OPERAND_SRC32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_SB_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_QI,
  M32C_OPERAND_SRC16_16_8_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_20_AN_RELATIVE_QI, M32C_OPERAND_SRC16_16_8_SB_RELATIVE_HI,
  M32C_OPERAND_SRC16_16_16_SB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_FB_RELATIVE_HI, M32C_OPERAND_SRC16_16_8_AN_RELATIVE_HI, M32C_OPERAND_SRC16_16_16_AN_RELATIVE_HI,
  M32C_OPERAND_SRC16_16_20_AN_RELATIVE_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_8_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_SRC32_24_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_SRC16_16_16_ABSOLUTE_QI,
  M32C_OPERAND_SRC16_16_16_ABSOLUTE_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_SRC16_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC16_2_S_16_ABSOLUTE_QI,
  M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_QI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_SRC32_2_S_8_SB_RELATIVE_HI,
  M32C_OPERAND_SRC32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_SRC32_2_S_16_ABSOLUTE_HI, M32C_OPERAND_DST16_RN_DIRECT_QI, M32C_OPERAND_DST16_RN_DIRECT_HI,
  M32C_OPERAND_DST16_RN_DIRECT_SI, M32C_OPERAND_DST16_RN_DIRECT_EXT_QI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_QI,
  M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_RN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_RN_DIRECT_PREFIXED_SI,
  M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_RN_DIRECT_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_R3_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST16_AN_DIRECT_QI,
  M32C_OPERAND_DST16_AN_DIRECT_HI, M32C_OPERAND_DST16_AN_DIRECT_SI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_QI,
  M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_HI, M32C_OPERAND_DST32_AN_DIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_DIRECT_PREFIXED_SI,
  M32C_OPERAND_DST16_AN_INDIRECT_QI, M32C_OPERAND_DST16_AN_INDIRECT_HI, M32C_OPERAND_DST16_AN_INDIRECT_SI, M32C_OPERAND_DST16_AN_INDIRECT_EXT_QI,
  M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_HI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_HI,
  M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_PREFIXED_SI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_AN_INDIRECT_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST16_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_16_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_24_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_32_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_32_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_40_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_48_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_QI,
  M32C_OPERAND_DST16_48_16_AN_RELATIVE_QI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_QI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_24_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_24_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_32_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_40_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_40_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_8_SB_RELATIVE_HI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_HI,
  M32C_OPERAND_DST16_48_8_FB_RELATIVE_HI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_16_AN_RELATIVE_HI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_HI,
  M32C_OPERAND_DST16_16_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_16_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_24_16_SB_RELATIVE_SI,
  M32C_OPERAND_DST16_24_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_24_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_24_20_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_32_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_32_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_32_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_32_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_40_16_SB_RELATIVE_SI,
  M32C_OPERAND_DST16_40_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_40_8_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_40_20_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_48_8_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_16_SB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_FB_RELATIVE_SI, M32C_OPERAND_DST16_48_8_AN_RELATIVE_SI,
  M32C_OPERAND_DST16_48_16_AN_RELATIVE_SI, M32C_OPERAND_DST16_48_20_AN_RELATIVE_SI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_EXT_QI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_8_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_EXT_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_SB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_FB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_32_16_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_AN_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_8_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_FB_RELATIVE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_8_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_QI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_HI, M32C_OPERAND_DST32_24_8_SB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_24_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_8_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_24_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_SB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_40_16_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_AN_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_8_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_SB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_8_FB_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_FB_RELATIVE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_8_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_48_24_AN_RELATIVE_PREFIXED_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_SB_RELATIVE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_8_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_8_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_24_AN_RELATIVE_EXTUNPREFIXED_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_QI, M32C_OPERAND_DST16_24_16_ABSOLUTE_QI, M32C_OPERAND_DST16_32_16_ABSOLUTE_QI,
  M32C_OPERAND_DST16_40_16_ABSOLUTE_QI, M32C_OPERAND_DST16_48_16_ABSOLUTE_QI, M32C_OPERAND_DST16_16_16_ABSOLUTE_HI, M32C_OPERAND_DST16_24_16_ABSOLUTE_HI,
  M32C_OPERAND_DST16_32_16_ABSOLUTE_HI, M32C_OPERAND_DST16_40_16_ABSOLUTE_HI, M32C_OPERAND_DST16_48_16_ABSOLUTE_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_SI,
  M32C_OPERAND_DST16_24_16_ABSOLUTE_SI, M32C_OPERAND_DST16_32_16_ABSOLUTE_SI, M32C_OPERAND_DST16_40_16_ABSOLUTE_SI, M32C_OPERAND_DST16_48_16_ABSOLUTE_SI,
  M32C_OPERAND_DST16_16_16_ABSOLUTE_EXT_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_QI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_24_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_32_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_UNPREFIXED_SI,
  M32C_OPERAND_DST32_40_24_ABSOLUTE_UNPREFIXED_SI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_QI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_QI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_HI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_HI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_HI, M32C_OPERAND_DST32_24_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_24_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_32_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_DST32_32_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_16_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_40_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_48_16_ABSOLUTE_PREFIXED_SI,
  M32C_OPERAND_DST32_48_24_ABSOLUTE_PREFIXED_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_16_ABSOLUTE_EXTUNPREFIXED_HI,
  M32C_OPERAND_DST32_16_24_ABSOLUTE_EXTUNPREFIXED_HI, M32C_OPERAND_BIT16_RN_DIRECT, M32C_OPERAND_BIT32_RN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_RN_DIRECT_PREFIXED,
  M32C_OPERAND_BIT16_AN_DIRECT, M32C_OPERAND_BIT32_AN_DIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_DIRECT_PREFIXED, M32C_OPERAND_BIT16_AN_INDIRECT,
  M32C_OPERAND_BIT32_AN_INDIRECT_UNPREFIXED, M32C_OPERAND_BIT32_AN_INDIRECT_PREFIXED, M32C_OPERAND_BIT16_16_8_SB_RELATIVE, M32C_OPERAND_BIT16_16_16_SB_RELATIVE,
  M32C_OPERAND_BIT16_16_8_FB_RELATIVE, M32C_OPERAND_BIT16_16_8_AN_RELATIVE, M32C_OPERAND_BIT16_16_16_AN_RELATIVE, M32C_OPERAND_BIT32_16_11_SB_RELATIVE_UNPREFIXED,
  M32C_OPERAND_BIT32_16_19_SB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_19_FB_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_11_AN_RELATIVE_UNPREFIXED,
  M32C_OPERAND_BIT32_16_19_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_AN_RELATIVE_UNPREFIXED, M32C_OPERAND_BIT32_24_11_SB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_SB_RELATIVE_PREFIXED,
  M32C_OPERAND_BIT32_24_11_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_FB_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_11_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT32_24_19_AN_RELATIVE_PREFIXED,
  M32C_OPERAND_BIT32_24_27_AN_RELATIVE_PREFIXED, M32C_OPERAND_BIT16_11_SB_RELATIVE_S, M32C_OPERAND_RN16_PUSH_S_DERIVED, M32C_OPERAND_AN16_PUSH_S_DERIVED,
  M32C_OPERAND_BIT16_16_16_ABSOLUTE, M32C_OPERAND_BIT32_16_19_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_16_27_ABSOLUTE_UNPREFIXED, M32C_OPERAND_BIT32_24_19_ABSOLUTE_PREFIXED,
  M32C_OPERAND_BIT32_24_27_ABSOLUTE_PREFIXED, M32C_OPERAND_DST16_3_S_R0L_DIRECT_QI, M32C_OPERAND_DST16_3_S_R0H_DIRECT_QI, M32C_OPERAND_DST16_3_S_8_8_SB_RELATIVE_QI,
  M32C_OPERAND_DST16_3_S_8_8_FB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_8_16_ABSOLUTE_QI, M32C_OPERAND_DST16_3_S_16_8_SB_RELATIVE_QI, M32C_OPERAND_DST16_3_S_16_8_FB_RELATIVE_QI,
  M32C_OPERAND_DST16_3_S_16_16_ABSOLUTE_QI, M32C_OPERAND_SRCDST16_R0L_R0H_S_DERIVED, M32C_OPERAND_DST32_2_S_R0L_DIRECT_QI, M32C_OPERAND_DST32_2_S_R0_DIRECT_HI,
  M32C_OPERAND_DST32_1_S_A0_DIRECT_HI, M32C_OPERAND_DST32_1_S_A1_DIRECT_HI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_QI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_QI,
  M32C_OPERAND_DST32_2_S_16_ABSOLUTE_QI, M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_HI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_HI,
  M32C_OPERAND_DST32_2_S_8_SB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_8_FB_RELATIVE_SI, M32C_OPERAND_DST32_2_S_16_ABSOLUTE_SI, M32C_OPERAND_SRC16_BASIC_QI,
  M32C_OPERAND_SRC16_BASIC_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_QI, M32C_OPERAND_SRC32_BASIC_PREFIXED_QI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_BASIC_PREFIXED_HI, M32C_OPERAND_SRC32_BASIC_UNPREFIXED_SI, M32C_OPERAND_SRC32_BASIC_PREFIXED_SI, M32C_OPERAND_SRC32_BASIC_EXTPREFIXED_QI,
  M32C_OPERAND_SRC16_16_8_QI, M32C_OPERAND_SRC16_16_16_QI, M32C_OPERAND_SRC16_16_8_HI, M32C_OPERAND_SRC16_16_16_HI,
  M32C_OPERAND_SRC32_16_8_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_QI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_HI,
  M32C_OPERAND_SRC32_16_16_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_24_UNPREFIXED_HI, M32C_OPERAND_SRC32_16_8_UNPREFIXED_SI, M32C_OPERAND_SRC32_16_16_UNPREFIXED_SI,
  M32C_OPERAND_SRC32_16_24_UNPREFIXED_SI, M32C_OPERAND_SRC32_24_8_PREFIXED_QI, M32C_OPERAND_SRC32_24_16_PREFIXED_QI, M32C_OPERAND_SRC32_24_24_PREFIXED_QI,
  M32C_OPERAND_SRC32_24_8_PREFIXED_HI, M32C_OPERAND_SRC32_24_16_PREFIXED_HI, M32C_OPERAND_SRC32_24_24_PREFIXED_HI, M32C_OPERAND_SRC32_24_8_PREFIXED_SI,
  M32C_OPERAND_SRC32_24_16_PREFIXED_SI, M32C_OPERAND_SRC32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_BASIC_QI, M32C_OPERAND_DST16_BASIC_HI,
  M32C_OPERAND_DST16_BASIC_SI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_QI, M32C_OPERAND_DST32_BASIC_PREFIXED_QI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_HI,
  M32C_OPERAND_DST32_BASIC_PREFIXED_HI, M32C_OPERAND_DST32_BASIC_UNPREFIXED_SI, M32C_OPERAND_DST32_BASIC_PREFIXED_SI, M32C_OPERAND_DST16_16_QI,
  M32C_OPERAND_DST16_16_8_QI, M32C_OPERAND_DST16_16_16_QI, M32C_OPERAND_DST16_16_16SA_QI, M32C_OPERAND_DST16_16_20AR_QI,
  M32C_OPERAND_DST16_16_HI, M32C_OPERAND_DST16_16_8_HI, M32C_OPERAND_DST16_16_16_HI, M32C_OPERAND_DST16_16_16SA_HI,
  M32C_OPERAND_DST16_16_20AR_HI, M32C_OPERAND_DST16_16_SI, M32C_OPERAND_DST16_16_8_SI, M32C_OPERAND_DST16_16_16_SI,
  M32C_OPERAND_DST16_16_16SA_SI, M32C_OPERAND_DST16_16_20AR_SI, M32C_OPERAND_DST16_16_EXT_QI, M32C_OPERAND_DST16_AN_INDIRECT_MOVA_HI,
  M32C_OPERAND_DST16_16_8_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_AN_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_8_SB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_SB_RELATIVE_MOVA_HI,
  M32C_OPERAND_DST16_16_8_FB_RELATIVE_MOVA_HI, M32C_OPERAND_DST16_16_16_ABSOLUTE_MOVA_HI, M32C_OPERAND_DST16_16_MOVA_HI, M32C_OPERAND_DST32_AN_INDIRECT_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_8_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_24_AN_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_SB_RELATIVE_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_16_SB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_8_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_FB_RELATIVE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_16_ABSOLUTE_UNPREFIXED_MOVA_SI,
  M32C_OPERAND_DST32_16_24_ABSOLUTE_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_MOVA_SI, M32C_OPERAND_DST32_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_8_UNPREFIXED_QI,
  M32C_OPERAND_DST32_16_16_UNPREFIXED_QI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_QI, M32C_OPERAND_DST32_16_24_UNPREFIXED_QI, M32C_OPERAND_DST32_16_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_8_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16_UNPREFIXED_HI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_HI, M32C_OPERAND_DST32_16_24_UNPREFIXED_HI,
  M32C_OPERAND_DST32_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_8_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16_UNPREFIXED_SI, M32C_OPERAND_DST32_16_16SA_UNPREFIXED_SI,
  M32C_OPERAND_DST32_16_24_UNPREFIXED_SI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_QI, M32C_OPERAND_DST32_16_EXTUNPREFIXED_HI, M32C_OPERAND_DST32_16_UNPREFIXED_MULEX_HI,
  M32C_OPERAND_DST16_24_QI, M32C_OPERAND_DST16_24_HI, M32C_OPERAND_DST32_24_UNPREFIXED_QI, M32C_OPERAND_DST32_24_PREFIXED_QI,
  M32C_OPERAND_DST32_24_8_PREFIXED_QI, M32C_OPERAND_DST32_24_16_PREFIXED_QI, M32C_OPERAND_DST32_24_24_PREFIXED_QI, M32C_OPERAND_DST32_24_UNPREFIXED_HI,
  M32C_OPERAND_DST32_24_PREFIXED_HI, M32C_OPERAND_DST32_24_8_PREFIXED_HI, M32C_OPERAND_DST32_24_16_PREFIXED_HI, M32C_OPERAND_DST32_24_24_PREFIXED_HI,
  M32C_OPERAND_DST32_24_UNPREFIXED_SI, M32C_OPERAND_DST32_24_PREFIXED_SI, M32C_OPERAND_DST32_24_8_PREFIXED_SI, M32C_OPERAND_DST32_24_16_PREFIXED_SI,
  M32C_OPERAND_DST32_24_24_PREFIXED_SI, M32C_OPERAND_DST16_32_QI, M32C_OPERAND_DST16_32_HI, M32C_OPERAND_DST32_32_UNPREFIXED_QI,
  M32C_OPERAND_DST32_32_PREFIXED_QI, M32C_OPERAND_DST32_32_UNPREFIXED_HI, M32C_OPERAND_DST32_32_PREFIXED_HI, M32C_OPERAND_DST32_32_UNPREFIXED_SI,
  M32C_OPERAND_DST32_32_PREFIXED_SI, M32C_OPERAND_DST32_40_UNPREFIXED_QI, M32C_OPERAND_DST32_40_PREFIXED_QI, M32C_OPERAND_DST32_40_UNPREFIXED_HI,
  M32C_OPERAND_DST32_40_PREFIXED_HI, M32C_OPERAND_DST32_40_UNPREFIXED_SI, M32C_OPERAND_DST32_40_PREFIXED_SI, M32C_OPERAND_DST32_48_PREFIXED_QI,
  M32C_OPERAND_DST32_48_PREFIXED_HI, M32C_OPERAND_DST32_48_PREFIXED_SI, M32C_OPERAND_BIT16_16, M32C_OPERAND_BIT16_16_BASIC,
  M32C_OPERAND_BIT16_16_8, M32C_OPERAND_BIT16_16_16, M32C_OPERAND_BIT32_16_UNPREFIXED, M32C_OPERAND_BIT32_24_PREFIXED,
  M32C_OPERAND_BIT32_BASIC_UNPREFIXED, M32C_OPERAND_BIT32_16_8_UNPREFIXED, M32C_OPERAND_BIT32_16_16_UNPREFIXED, M32C_OPERAND_BIT32_16_24_UNPREFIXED,
  M32C_OPERAND_SRC16_2_S, M32C_OPERAND_SRC32_2_S_QI, M32C_OPERAND_SRC32_2_S_HI, M32C_OPERAND_DST16_3_S_8,
  M32C_OPERAND_DST16_3_S_16, M32C_OPERAND_SRCDST16_R0L_R0H_S, M32C_OPERAND_DST32_2_S_BASIC_QI, M32C_OPERAND_DST32_2_S_BASIC_HI,
  M32C_OPERAND_DST32_2_S_8_QI, M32C_OPERAND_DST32_2_S_16_QI, M32C_OPERAND_DST32_2_S_8_HI, M32C_OPERAND_DST32_2_S_16_HI,
  M32C_OPERAND_DST32_2_S_8_SI, M32C_OPERAND_DST32_2_S_16_SI, M32C_OPERAND_DST32_AN_S, M32C_OPERAND_BIT16_11_S,
  M32C_OPERAND_RN16_PUSH_S_ANYOF, M32C_OPERAND_AN16_PUSH_S_ANYOF, M32C_OPERAND_MAX, M32R_OPERAND_PC,
  M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1, M32R_OPERAND_SRC2,
  M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8, M32R_OPERAND_SIMM16,
  M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5, M32R_OPERAND_UIMM8,
  M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD, M32R_OPERAND_ACCS,
  M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16, M32R_OPERAND_SLO16,
  M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8, M32R_OPERAND_DISP16,
  M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM, M32R_OPERAND_MAX,
  MEP_OPERAND_PC, MEP_OPERAND_R0, MEP_OPERAND_RN, MEP_OPERAND_RM,
  MEP_OPERAND_RL, MEP_OPERAND_RN3, MEP_OPERAND_RMA, MEP_OPERAND_RNC,
  MEP_OPERAND_RNUC, MEP_OPERAND_RNS, MEP_OPERAND_RNUS, MEP_OPERAND_RNL,
  MEP_OPERAND_RNUL, MEP_OPERAND_RN3C, MEP_OPERAND_RN3UC, MEP_OPERAND_RN3S,
  MEP_OPERAND_RN3US, MEP_OPERAND_RN3L, MEP_OPERAND_RN3UL, MEP_OPERAND_LP,
  MEP_OPERAND_SAR, MEP_OPERAND_HI, MEP_OPERAND_LO, MEP_OPERAND_MB0,
  MEP_OPERAND_ME0, MEP_OPERAND_MB1, MEP_OPERAND_ME1, MEP_OPERAND_PSW,
  MEP_OPERAND_EPC, MEP_OPERAND_EXC, MEP_OPERAND_NPC, MEP_OPERAND_DBG,
  MEP_OPERAND_DEPC, MEP_OPERAND_OPT, MEP_OPERAND_R1, MEP_OPERAND_TP,
  MEP_OPERAND_SP, MEP_OPERAND_TPR, MEP_OPERAND_SPR, MEP_OPERAND_CSRN,
  MEP_OPERAND_CSRN_IDX, MEP_OPERAND_CRN64, MEP_OPERAND_CRN, MEP_OPERAND_CRNX64,
  MEP_OPERAND_CRNX, MEP_OPERAND_CCRN, MEP_OPERAND_CCCC, MEP_OPERAND_PCREL8A2,
  MEP_OPERAND_PCREL12A2, MEP_OPERAND_PCREL17A2, MEP_OPERAND_PCREL24A2, MEP_OPERAND_PCABS24A2,
  MEP_OPERAND_SDISP16, MEP_OPERAND_SIMM16, MEP_OPERAND_UIMM16, MEP_OPERAND_CODE16,
  MEP_OPERAND_UDISP2, MEP_OPERAND_UIMM2, MEP_OPERAND_SIMM6, MEP_OPERAND_SIMM8,
  MEP_OPERAND_ADDR24A4, MEP_OPERAND_CODE24, MEP_OPERAND_CALLNUM, MEP_OPERAND_UIMM3,
  MEP_OPERAND_UIMM4, MEP_OPERAND_UIMM5, MEP_OPERAND_UDISP7, MEP_OPERAND_UDISP7A2,
  MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4,
  MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP8, MEP_OPERAND_CDISP8A2, MEP_OPERAND_CDISP8A4,
  MEP_OPERAND_CDISP8A8, MEP_OPERAND_ZERO, MEP_OPERAND_CP_FLAG, MEP_OPERAND_FMAX_FRD,
  MEP_OPERAND_FMAX_FRN, MEP_OPERAND_FMAX_FRM, MEP_OPERAND_FMAX_FRD_INT, MEP_OPERAND_FMAX_FRN_INT,
  MEP_OPERAND_FMAX_CCRN, MEP_OPERAND_FMAX_CIRR, MEP_OPERAND_FMAX_CBCR, MEP_OPERAND_FMAX_CERR,
  MEP_OPERAND_FMAX_RM, MEP_OPERAND_FMAX_COMPARE_I_P, MEP_OPERAND_MAX, MT_OPERAND_PC,
  MT_OPERAND_FRSR1, MT_OPERAND_FRSR2, MT_OPERAND_FRDR, MT_OPERAND_FRDRRR,
  MT_OPERAND_IMM16, MT_OPERAND_IMM16Z, MT_OPERAND_IMM16O, MT_OPERAND_RC,
  MT_OPERAND_RCNUM, MT_OPERAND_CONTNUM, MT_OPERAND_RBBC, MT_OPERAND_COLNUM,
  MT_OPERAND_ROWNUM, MT_OPERAND_ROWNUM1, MT_OPERAND_ROWNUM2, MT_OPERAND_RC1,
  MT_OPERAND_RC2, MT_OPERAND_CBRB, MT_OPERAND_CELL, MT_OPERAND_DUP,
  MT_OPERAND_CTXDISP, MT_OPERAND_FBDISP, MT_OPERAND_TYPE, MT_OPERAND_MASK,
  MT_OPERAND_BANKADDR, MT_OPERAND_INCAMT, MT_OPERAND_XMODE, MT_OPERAND_MASK1,
  MT_OPERAND_BALL, MT_OPERAND_BRC, MT_OPERAND_RDA, MT_OPERAND_WR,
  MT_OPERAND_BALL2, MT_OPERAND_BRC2, MT_OPERAND_PERM, MT_OPERAND_A23,
  MT_OPERAND_CR, MT_OPERAND_CBS, MT_OPERAND_INCR, MT_OPERAND_LENGTH,
  MT_OPERAND_CBX, MT_OPERAND_CCB, MT_OPERAND_CDB, MT_OPERAND_MODE,
  MT_OPERAND_ID, MT_OPERAND_SIZE, MT_OPERAND_FBINCR, MT_OPERAND_LOOPSIZE,
  MT_OPERAND_IMM16L, MT_OPERAND_RC3, MT_OPERAND_CB1SEL, MT_OPERAND_CB2SEL,
  MT_OPERAND_CB1INCR, MT_OPERAND_CB2INCR, MT_OPERAND_MAX, OPENRISC_OPERAND_PC,
  OPENRISC_OPERAND_SR, OPENRISC_OPERAND_CBIT, OPENRISC_OPERAND_SIMM_16, OPENRISC_OPERAND_UIMM_16,
  OPENRISC_OPERAND_DISP_26, OPENRISC_OPERAND_ABS_26, OPENRISC_OPERAND_UIMM_5, OPENRISC_OPERAND_RD,
  OPENRISC_OPERAND_RA, OPENRISC_OPERAND_RB, OPENRISC_OPERAND_OP_F_23, OPENRISC_OPERAND_OP_F_3,
  OPENRISC_OPERAND_HI16, OPENRISC_OPERAND_LO16, OPENRISC_OPERAND_UI16NC, OPENRISC_OPERAND_MAX,
  XC16X_OPERAND_PC, XC16X_OPERAND_SR, XC16X_OPERAND_DR, XC16X_OPERAND_DRI,
  XC16X_OPERAND_SRB, XC16X_OPERAND_DRB, XC16X_OPERAND_SR2, XC16X_OPERAND_SRC1,
  XC16X_OPERAND_SRC2, XC16X_OPERAND_SRDIV, XC16X_OPERAND_REGNAM, XC16X_OPERAND_UIMM2,
  XC16X_OPERAND_UIMM3, XC16X_OPERAND_UIMM4, XC16X_OPERAND_UIMM7, XC16X_OPERAND_UIMM8,
  XC16X_OPERAND_UIMM16, XC16X_OPERAND_UPOF16, XC16X_OPERAND_REG8, XC16X_OPERAND_REGMEM8,
  XC16X_OPERAND_REGBMEM8, XC16X_OPERAND_REGOFF8, XC16X_OPERAND_REGHI8, XC16X_OPERAND_REGB8,
  XC16X_OPERAND_GENREG, XC16X_OPERAND_SEG, XC16X_OPERAND_SEGHI8, XC16X_OPERAND_CADDR,
  XC16X_OPERAND_REL, XC16X_OPERAND_RELHI, XC16X_OPERAND_CONDBIT, XC16X_OPERAND_BIT1,
  XC16X_OPERAND_BIT2, XC16X_OPERAND_BIT4, XC16X_OPERAND_LBIT4, XC16X_OPERAND_LBIT2,
  XC16X_OPERAND_BIT8, XC16X_OPERAND_U4, XC16X_OPERAND_BITONE, XC16X_OPERAND_BIT01,
  XC16X_OPERAND_COND, XC16X_OPERAND_ICOND, XC16X_OPERAND_EXTCOND, XC16X_OPERAND_MEMORY,
  XC16X_OPERAND_MEMGR8, XC16X_OPERAND_CBIT, XC16X_OPERAND_QBIT, XC16X_OPERAND_QLOBIT,
  XC16X_OPERAND_QHIBIT, XC16X_OPERAND_MASK8, XC16X_OPERAND_MASKLO8, XC16X_OPERAND_PAGENUM,
  XC16X_OPERAND_DATA8, XC16X_OPERAND_DATAHI8, XC16X_OPERAND_SGTDISBIT, XC16X_OPERAND_UPAG16,
  XC16X_OPERAND_USEG8, XC16X_OPERAND_USEG16, XC16X_OPERAND_USOF16, XC16X_OPERAND_HASH,
  XC16X_OPERAND_DOT, XC16X_OPERAND_POF, XC16X_OPERAND_PAG, XC16X_OPERAND_SOF,
  XC16X_OPERAND_SEGM, XC16X_OPERAND_MAX, XSTORMY16_OPERAND_PC, XSTORMY16_OPERAND_PSW_Z8,
  XSTORMY16_OPERAND_PSW_Z16, XSTORMY16_OPERAND_PSW_CY, XSTORMY16_OPERAND_PSW_HC, XSTORMY16_OPERAND_PSW_OV,
  XSTORMY16_OPERAND_PSW_PT, XSTORMY16_OPERAND_PSW_S, XSTORMY16_OPERAND_RD, XSTORMY16_OPERAND_RDM,
  XSTORMY16_OPERAND_RM, XSTORMY16_OPERAND_RS, XSTORMY16_OPERAND_RB, XSTORMY16_OPERAND_RBJ,
  XSTORMY16_OPERAND_BCOND2, XSTORMY16_OPERAND_WS2, XSTORMY16_OPERAND_BCOND5, XSTORMY16_OPERAND_IMM2,
  XSTORMY16_OPERAND_IMM3, XSTORMY16_OPERAND_IMM3B, XSTORMY16_OPERAND_IMM4, XSTORMY16_OPERAND_IMM8,
  XSTORMY16_OPERAND_IMM8SMALL, XSTORMY16_OPERAND_IMM12, XSTORMY16_OPERAND_IMM16, XSTORMY16_OPERAND_LMEM8,
  XSTORMY16_OPERAND_HMEM8, XSTORMY16_OPERAND_REL8_2, XSTORMY16_OPERAND_REL8_4, XSTORMY16_OPERAND_REL12,
  XSTORMY16_OPERAND_REL12A, XSTORMY16_OPERAND_ABS24, XSTORMY16_OPERAND_PSW, XSTORMY16_OPERAND_RPSW,
  XSTORMY16_OPERAND_SP, XSTORMY16_OPERAND_R0, XSTORMY16_OPERAND_R1, XSTORMY16_OPERAND_R2,
  XSTORMY16_OPERAND_R8, XSTORMY16_OPERAND_MAX
}
enum  cgen_insn_attr {
  CGEN_INSN_ALIAS = 0, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT,
  CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS,
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI,
  CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED,
  CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING,
  CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_AUDIO,
  CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT,
  CGEN_INSN_FR400_MAJOR, CGEN_INSN_FR450_MAJOR, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_EXT_SKIP_INSN,
  CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN,
  CGEN_INSN_LOAD_DELAY, CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD,
  CGEN_INSN_USES_RS, CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS,
  CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS,
  CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI,
  CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS,
  CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_ISA, CGEN_INSN_RL_TYPE, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS,
  CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI,
  CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS,
  CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL, CGEN_INSN_SPECIAL_M32R,
  CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL,
  CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT,
  CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB,
  CGEN_INSN_OPTIONAL_BIT_INSN, CGEN_INSN_OPTIONAL_MUL_INSN, CGEN_INSN_OPTIONAL_DIV_INSN, CGEN_INSN_OPTIONAL_DEBUG_INSN,
  CGEN_INSN_OPTIONAL_LDZ_INSN, CGEN_INSN_OPTIONAL_ABS_INSN, CGEN_INSN_OPTIONAL_AVE_INSN, CGEN_INSN_OPTIONAL_MINMAX_INSN,
  CGEN_INSN_OPTIONAL_CLIP_INSN, CGEN_INSN_OPTIONAL_SAT_INSN, CGEN_INSN_OPTIONAL_UCI_INSN, CGEN_INSN_OPTIONAL_DSP_INSN,
  CGEN_INSN_OPTIONAL_CP_INSN, CGEN_INSN_OPTIONAL_CP64_INSN, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP,
  CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP,
  CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_ISA, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_LOAD_DELAY,
  CGEN_INSN_MEMORY_ACCESS, CGEN_INSN_AL_INSN, CGEN_INSN_IO_INSN, CGEN_INSN_BR_INSN,
  CGEN_INSN_JAL_HAZARD, CGEN_INSN_USES_FRDR, CGEN_INSN_USES_FRDRRR, CGEN_INSN_USES_FRSR1,
  CGEN_INSN_USES_FRSR2, CGEN_INSN_SKIPA, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL,
  CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT,
  CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB,
  CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH,
  CGEN_INSN_END_NBOOLS, CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI,
  CGEN_INSN_COND_CTI, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE,
  CGEN_INSN_RELAXED, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS,
  CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS,
  CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI,
  CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED,
  CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31,
  CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
}

Variables

const CGEN_ATTR_TABLE frv_cgen_hardware_attr_table []
const CGEN_ATTR_TABLE frv_cgen_ifield_attr_table []
const CGEN_ATTR_TABLE frv_cgen_operand_attr_table []
const CGEN_ATTR_TABLE frv_cgen_insn_attr_table []
CGEN_KEYWORD frv_cgen_opval_gr_names
CGEN_KEYWORD frv_cgen_opval_fr_names
CGEN_KEYWORD frv_cgen_opval_cpr_names
CGEN_KEYWORD frv_cgen_opval_spr_names
CGEN_KEYWORD frv_cgen_opval_accg_names
CGEN_KEYWORD frv_cgen_opval_acc_names
CGEN_KEYWORD frv_cgen_opval_iacc0_names
CGEN_KEYWORD frv_cgen_opval_iccr_names
CGEN_KEYWORD frv_cgen_opval_fccr_names
CGEN_KEYWORD frv_cgen_opval_cccr_names
CGEN_KEYWORD frv_cgen_opval_h_pack
CGEN_KEYWORD frv_cgen_opval_h_hint_taken
CGEN_KEYWORD frv_cgen_opval_h_hint_not_taken
const CGEN_HW_ENTRY frv_cgen_hw_table []

Define Documentation

Definition at line 62 of file frv-desc.h.

Definition at line 54 of file frv-desc.h.

#define CGEN_ARCH   frv

Definition at line 30 of file frv-desc.h.

#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)

Definition at line 678 of file frv-desc.h.

#define CGEN_ATTR_CGEN_HW_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)

Definition at line 676 of file frv-desc.h.

#define CGEN_ATTR_CGEN_HW_PC_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)

Definition at line 679 of file frv-desc.h.

#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)

Definition at line 680 of file frv-desc.h.

#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)

Definition at line 677 of file frv-desc.h.

#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)

Definition at line 626 of file frv-desc.h.

#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)

Definition at line 623 of file frv-desc.h.

#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)

Definition at line 625 of file frv-desc.h.

#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)

Definition at line 627 of file frv-desc.h.

#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)

Definition at line 628 of file frv-desc.h.

#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)

Definition at line 629 of file frv-desc.h.

#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)

Definition at line 624 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)

Definition at line 782 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_AUDIO_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_AUDIO)) != 0)

Definition at line 797 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)

Definition at line 785 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_CONDITIONAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_CONDITIONAL)) != 0)

Definition at line 794 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)

Definition at line 787 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_FR400_MAJOR_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_FR400_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 778 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_FR450_MAJOR_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_FR450_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 779 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_FR500_MAJOR_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_FR500_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 780 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_FR550_MAJOR_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_FR550_MAJOR-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 781 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_FR_ACCESS_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_FR_ACCESS)) != 0)

Definition at line 795 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 776 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)

Definition at line 790 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_NON_EXCEPTING_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_NON_EXCEPTING)) != 0)

Definition at line 793 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_PBB_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)

Definition at line 791 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_PRESERVE_OVF_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_PRESERVE_OVF)) != 0)

Definition at line 796 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_PRIVILEGED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_PRIVILEGED)) != 0)

Definition at line 792 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)

Definition at line 788 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)

Definition at line 789 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)

Definition at line 786 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)

Definition at line 784 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_UNIT_VALUE (   attrs)    ((attrs)->nonbool[CGEN_INSN_UNIT-CGEN_INSN_START_NBOOLS-1].nonbitset)

Definition at line 777 of file frv-desc.h.

#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)

Definition at line 783 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)

Definition at line 718 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)

Definition at line 724 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE (   attrs)    ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)

Definition at line 715 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)

Definition at line 721 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)

Definition at line 717 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)

Definition at line 722 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)

Definition at line 723 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)

Definition at line 719 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)

Definition at line 720 of file frv-desc.h.

#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE (   attrs)    (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)

Definition at line 716 of file frv-desc.h.

Definition at line 673 of file frv-desc.h.

Definition at line 620 of file frv-desc.h.

#define CGEN_INSN_LSB0_P   1

Definition at line 43 of file frv-desc.h.

Definition at line 773 of file frv-desc.h.

#define CGEN_INT_INSN_P   1

Definition at line 51 of file frv-desc.h.

#define CGEN_MAX_INSN_SIZE   4

Definition at line 49 of file frv-desc.h.

#define CGEN_MIN_INSN_SIZE   4

Definition at line 46 of file frv-desc.h.

Definition at line 59 of file frv-desc.h.

Definition at line 712 of file frv-desc.h.

#define CGEN_SYM (   s)    frv_cgen_s

Definition at line 36 of file frv-desc.h.

#define HAVE_CPU_FRVBF

Definition at line 41 of file frv-desc.h.

#define MAX_HW   ((int) HW_MAX)

Definition at line 699 of file frv-desc.h.

#define MAX_IFLD   ((int) FRV_F_MAX)

Definition at line 662 of file frv-desc.h.

#define MAX_ISAS   1

Definition at line 605 of file frv-desc.h.

#define MAX_MACHS   ((int) MACH_MAX)

Definition at line 606 of file frv-desc.h.

#define MAX_OPERAND_INSTANCES   8

Definition at line 757 of file frv-desc.h.

#define MAX_OPERANDS   89

Definition at line 754 of file frv-desc.h.


Typedef Documentation

typedef enum acc_names ACC_NAMES
typedef enum accg_names ACCG_NAMES
typedef enum cccr_names CCCR_NAMES
typedef enum cgen_hw_attr CGEN_HW_ATTR
typedef enum cgen_hw_type CGEN_HW_TYPE
typedef enum cpr_names CPR_NAMES
typedef enum fccr_names FCCR_NAMES
typedef enum flt_cc FLT_CC
typedef enum fr_names FR_NAMES
typedef enum gr_names GR_NAMES
typedef enum iacc0_names IACC0_NAMES
typedef enum iccr_names ICCR_NAMES
typedef enum ifield_type IFIELD_TYPE
typedef enum insn_op INSN_OP
typedef enum insn_ope1 INSN_OPE1
typedef enum insn_ope2 INSN_OPE2
typedef enum insn_ope3 INSN_OPE3
typedef enum insn_ope4 INSN_OPE4
typedef enum int_cc INT_CC
typedef enum isa_attr ISA_ATTR
typedef enum mach_attr MACH_ATTR
typedef enum spr_names SPR_NAMES
typedef enum unit_attr UNIT_ATTR

Enumeration Type Documentation

enum acc_names
Enumerator:
H_ACC40_ACC0 
H_ACC40_ACC1 
H_ACC40_ACC2 
H_ACC40_ACC3 
H_ACC40_ACC4 
H_ACC40_ACC5 
H_ACC40_ACC6 
H_ACC40_ACC7 
H_ACC40_ACC8 
H_ACC40_ACC9 
H_ACC40_ACC10 
H_ACC40_ACC11 
H_ACC40_ACC12 
H_ACC40_ACC13 
H_ACC40_ACC14 
H_ACC40_ACC15 
H_ACC40_ACC16 
H_ACC40_ACC17 
H_ACC40_ACC18 
H_ACC40_ACC19 
H_ACC40_ACC20 
H_ACC40_ACC21 
H_ACC40_ACC22 
H_ACC40_ACC23 
H_ACC40_ACC24 
H_ACC40_ACC25 
H_ACC40_ACC26 
H_ACC40_ACC27 
H_ACC40_ACC28 
H_ACC40_ACC29 
H_ACC40_ACC30 
H_ACC40_ACC31 
H_ACC40_ACC32 
H_ACC40_ACC33 
H_ACC40_ACC34 
H_ACC40_ACC35 
H_ACC40_ACC36 
H_ACC40_ACC37 
H_ACC40_ACC38 
H_ACC40_ACC39 
H_ACC40_ACC40 
H_ACC40_ACC41 
H_ACC40_ACC42 
H_ACC40_ACC43 
H_ACC40_ACC44 
H_ACC40_ACC45 
H_ACC40_ACC46 
H_ACC40_ACC47 
H_ACC40_ACC48 
H_ACC40_ACC49 
H_ACC40_ACC50 
H_ACC40_ACC51 
H_ACC40_ACC52 
H_ACC40_ACC53 
H_ACC40_ACC54 
H_ACC40_ACC55 
H_ACC40_ACC56 
H_ACC40_ACC57 
H_ACC40_ACC58 
H_ACC40_ACC59 
H_ACC40_ACC60 
H_ACC40_ACC61 
H_ACC40_ACC62 
H_ACC40_ACC63 

Definition at line 499 of file frv-desc.h.

enum accg_names
Enumerator:
H_ACCG_ACCG0 
H_ACCG_ACCG1 
H_ACCG_ACCG2 
H_ACCG_ACCG3 
H_ACCG_ACCG4 
H_ACCG_ACCG5 
H_ACCG_ACCG6 
H_ACCG_ACCG7 
H_ACCG_ACCG8 
H_ACCG_ACCG9 
H_ACCG_ACCG10 
H_ACCG_ACCG11 
H_ACCG_ACCG12 
H_ACCG_ACCG13 
H_ACCG_ACCG14 
H_ACCG_ACCG15 
H_ACCG_ACCG16 
H_ACCG_ACCG17 
H_ACCG_ACCG18 
H_ACCG_ACCG19 
H_ACCG_ACCG20 
H_ACCG_ACCG21 
H_ACCG_ACCG22 
H_ACCG_ACCG23 
H_ACCG_ACCG24 
H_ACCG_ACCG25 
H_ACCG_ACCG26 
H_ACCG_ACCG27 
H_ACCG_ACCG28 
H_ACCG_ACCG29 
H_ACCG_ACCG30 
H_ACCG_ACCG31 
H_ACCG_ACCG32 
H_ACCG_ACCG33 
H_ACCG_ACCG34 
H_ACCG_ACCG35 
H_ACCG_ACCG36 
H_ACCG_ACCG37 
H_ACCG_ACCG38 
H_ACCG_ACCG39 
H_ACCG_ACCG40 
H_ACCG_ACCG41 
H_ACCG_ACCG42 
H_ACCG_ACCG43 
H_ACCG_ACCG44 
H_ACCG_ACCG45 
H_ACCG_ACCG46 
H_ACCG_ACCG47 
H_ACCG_ACCG48 
H_ACCG_ACCG49 
H_ACCG_ACCG50 
H_ACCG_ACCG51 
H_ACCG_ACCG52 
H_ACCG_ACCG53 
H_ACCG_ACCG54 
H_ACCG_ACCG55 
H_ACCG_ACCG56 
H_ACCG_ACCG57 
H_ACCG_ACCG58 
H_ACCG_ACCG59 
H_ACCG_ACCG60 
H_ACCG_ACCG61 
H_ACCG_ACCG62 
H_ACCG_ACCG63 

Definition at line 479 of file frv-desc.h.

enum cccr_names
Enumerator:
H_CCCR_CC0 
H_CCCR_CC1 
H_CCCR_CC2 
H_CCCR_CC3 
H_CCCR_CC4 
H_CCCR_CC5 
H_CCCR_CC6 
H_CCCR_CC7 

Definition at line 534 of file frv-desc.h.

Enumerator:
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_ISA 
CGEN_HW_RL_TYPE 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_IS_FLOAT 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_ISA 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 
CGEN_HW_VIRTUAL 
CGEN_HW_CACHE_ADDR 
CGEN_HW_PC 
CGEN_HW_PROFILE 
CGEN_HW_END_BOOLS 
CGEN_HW_START_NBOOLS 
CGEN_HW_MACH 
CGEN_HW_END_NBOOLS 

Definition at line 667 of file frv-desc.h.

Enumerator:
CGEN_HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_CR 
HW_H_DR 
HW_H_PS 
HW_H_R13 
HW_H_R14 
HW_H_R15 
HW_H_NBIT 
HW_H_ZBIT 
HW_H_VBIT 
HW_H_CBIT 
HW_H_IBIT 
HW_H_SBIT 
HW_H_TBIT 
HW_H_D0BIT 
HW_H_D1BIT 
HW_H_CCR 
HW_H_SCR 
HW_H_ILM 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_RELOC_ANN 
HW_H_PC 
HW_H_PSR_IMPLE 
HW_H_PSR_VER 
HW_H_PSR_ICE 
HW_H_PSR_NEM 
HW_H_PSR_CM 
HW_H_PSR_BE 
HW_H_PSR_ESR 
HW_H_PSR_EF 
HW_H_PSR_EM 
HW_H_PSR_PIL 
HW_H_PSR_PS 
HW_H_PSR_ET 
HW_H_PSR_S 
HW_H_TBR_TBA 
HW_H_TBR_TT 
HW_H_BPSR_BS 
HW_H_BPSR_BET 
HW_H_GR 
HW_H_GR_DOUBLE 
HW_H_GR_HI 
HW_H_GR_LO 
HW_H_FR 
HW_H_FR_DOUBLE 
HW_H_FR_INT 
HW_H_FR_HI 
HW_H_FR_LO 
HW_H_FR_0 
HW_H_FR_1 
HW_H_FR_2 
HW_H_FR_3 
HW_H_CPR 
HW_H_CPR_DOUBLE 
HW_H_SPR 
HW_H_ACCG 
HW_H_ACC40S 
HW_H_ACC40U 
HW_H_IACC0 
HW_H_ICCR 
HW_H_FCCR 
HW_H_CCCR 
HW_H_PACK 
HW_H_HINT_TAKEN 
HW_H_HINT_NOT_TAKEN 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_SPR 
HW_H_REGISTERS 
HW_H_STACK 
HW_H_PABITS 
HW_H_ZBIT 
HW_H_CBIT 
HW_H_DCBIT 
HW_H_PC 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_GR_QI 
HW_H_GR_HI 
HW_H_GR_SI 
HW_H_GR_EXT_QI 
HW_H_GR_EXT_HI 
HW_H_R0L 
HW_H_R0H 
HW_H_R1L 
HW_H_R1H 
HW_H_R0 
HW_H_R1 
HW_H_R2 
HW_H_R3 
HW_H_R0L_R0H 
HW_H_R2R0 
HW_H_R3R1 
HW_H_R1R2R0 
HW_H_AR 
HW_H_AR_QI 
HW_H_AR_HI 
HW_H_AR_SI 
HW_H_A0 
HW_H_A1 
HW_H_SB 
HW_H_FB 
HW_H_SP 
HW_H_SBIT 
HW_H_ZBIT 
HW_H_OBIT 
HW_H_CBIT 
HW_H_UBIT 
HW_H_IBIT 
HW_H_BBIT 
HW_H_DBIT 
HW_H_DCT0 
HW_H_DCT1 
HW_H_SVF 
HW_H_DRC0 
HW_H_DRC1 
HW_H_DMD0 
HW_H_DMD1 
HW_H_INTB 
HW_H_SVP 
HW_H_VCT 
HW_H_ISP 
HW_H_DMA0 
HW_H_DMA1 
HW_H_DRA0 
HW_H_DRA1 
HW_H_DSA0 
HW_H_DSA1 
HW_H_COND16 
HW_H_COND16C 
HW_H_COND16J 
HW_H_COND16J_5 
HW_H_COND32 
HW_H_CR1_32 
HW_H_CR2_32 
HW_H_CR3_32 
HW_H_CR_16 
HW_H_FLAGS 
HW_H_SHIMM 
HW_H_BIT_INDEX 
HW_H_SRC_INDEX 
HW_H_DST_INDEX 
HW_H_SRC_INDIRECT 
HW_H_DST_INDIRECT 
HW_H_NONE 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_HI16 
HW_H_SLO16 
HW_H_ULO16 
HW_H_GR 
HW_H_CR 
HW_H_ACCUM 
HW_H_ACCUMS 
HW_H_COND 
HW_H_PSW 
HW_H_BPSW 
HW_H_BBPSW 
HW_H_LOCK 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GPR 
HW_H_CSR 
HW_H_CR64 
HW_H_CR 
HW_H_CCR 
HW_H_CR_FMAX 
HW_H_CCR_FMAX 
HW_H_FMAX_COMPARE_I_P 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_SPR 
HW_H_PC 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_SR 
HW_H_HI16 
HW_H_LO16 
HW_H_CBIT 
HW_H_DELAY_INSN 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_EXT 
HW_H_PSW 
HW_H_GRB 
HW_H_CC 
HW_H_ECC 
HW_H_GRB8 
HW_H_R8 
HW_H_REGMEM8 
HW_H_REGDIV8 
HW_H_R0 
HW_H_R01 
HW_H_REGBMEM8 
HW_H_MEMGR8 
HW_H_COND 
HW_H_CBIT 
HW_H_SGTDIS 
HW_MAX 
HW_H_MEMORY 
HW_H_SINT 
HW_H_UINT 
HW_H_ADDR 
HW_H_IADDR 
HW_H_PC 
HW_H_GR 
HW_H_RB 
HW_H_RBJ 
HW_H_RPSW 
HW_H_Z8 
HW_H_Z16 
HW_H_CY 
HW_H_HC 
HW_H_OV 
HW_H_PT 
HW_H_S 
HW_H_BRANCHCOND 
HW_H_WORDSIZE 
HW_MAX 

Definition at line 683 of file frv-desc.h.

Enumerator:
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_ISA 
CGEN_IFLD_RL_TYPE 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_RELOC 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_ISA 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_RELOC 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 
CGEN_IFLD_VIRTUAL 
CGEN_IFLD_PCREL_ADDR 
CGEN_IFLD_ABS_ADDR 
CGEN_IFLD_RESERVED 
CGEN_IFLD_SIGN_OPT 
CGEN_IFLD_SIGNED 
CGEN_IFLD_END_BOOLS 
CGEN_IFLD_START_NBOOLS 
CGEN_IFLD_MACH 
CGEN_IFLD_END_NBOOLS 

Definition at line 613 of file frv-desc.h.

Enumerator:
CGEN_INSN_ALIAS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_NOT_IN_DELAY_SLOT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_PRIVILEGED 
CGEN_INSN_NON_EXCEPTING 
CGEN_INSN_CONDITIONAL 
CGEN_INSN_FR_ACCESS 
CGEN_INSN_PRESERVE_OVF 
CGEN_INSN_AUDIO 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_UNIT 
CGEN_INSN_FR400_MAJOR 
CGEN_INSN_FR450_MAJOR 
CGEN_INSN_FR500_MAJOR 
CGEN_INSN_FR550_MAJOR 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_EXT_SKIP_INSN 
CGEN_INSN_SKIPA 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_YIELD_INSN 
CGEN_INSN_LOAD_DELAY 
CGEN_INSN_EVEN_REG_NUM 
CGEN_INSN_UNSUPPORTED 
CGEN_INSN_USES_RD 
CGEN_INSN_USES_RS 
CGEN_INSN_USES_RT 
CGEN_INSN_USES_R31 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_ISA 
CGEN_INSN_RL_TYPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_FILL_SLOT 
CGEN_INSN_SPECIAL 
CGEN_INSN_SPECIAL_M32R 
CGEN_INSN_SPECIAL_FLOAT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_PIPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_OPTIONAL_BIT_INSN 
CGEN_INSN_OPTIONAL_MUL_INSN 
CGEN_INSN_OPTIONAL_DIV_INSN 
CGEN_INSN_OPTIONAL_DEBUG_INSN 
CGEN_INSN_OPTIONAL_LDZ_INSN 
CGEN_INSN_OPTIONAL_ABS_INSN 
CGEN_INSN_OPTIONAL_AVE_INSN 
CGEN_INSN_OPTIONAL_MINMAX_INSN 
CGEN_INSN_OPTIONAL_CLIP_INSN 
CGEN_INSN_OPTIONAL_SAT_INSN 
CGEN_INSN_OPTIONAL_UCI_INSN 
CGEN_INSN_OPTIONAL_DSP_INSN 
CGEN_INSN_OPTIONAL_CP_INSN 
CGEN_INSN_OPTIONAL_CP64_INSN 
CGEN_INSN_OPTIONAL_VLIW64 
CGEN_INSN_MAY_TRAP 
CGEN_INSN_VLIW_ALONE 
CGEN_INSN_VLIW_NO_CORE_NOP 
CGEN_INSN_VLIW_NO_COP_NOP 
CGEN_INSN_VLIW64_NO_MATCHING_NOP 
CGEN_INSN_VLIW32_NO_MATCHING_NOP 
CGEN_INSN_VOLATILE 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_ISA 
CGEN_INSN_LATENCY 
CGEN_INSN_CONFIG 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_LOAD_DELAY 
CGEN_INSN_MEMORY_ACCESS 
CGEN_INSN_AL_INSN 
CGEN_INSN_IO_INSN 
CGEN_INSN_BR_INSN 
CGEN_INSN_JAL_HAZARD 
CGEN_INSN_USES_FRDR 
CGEN_INSN_USES_FRDRRR 
CGEN_INSN_USES_FRSR1 
CGEN_INSN_USES_FRSR2 
CGEN_INSN_SKIPA 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_NOT_IN_DELAY_SLOT 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_PIPE 
CGEN_INSN_END_NBOOLS 
CGEN_INSN_ALIAS 
CGEN_INSN_VIRTUAL 
CGEN_INSN_UNCOND_CTI 
CGEN_INSN_COND_CTI 
CGEN_INSN_SKIP_CTI 
CGEN_INSN_DELAY_SLOT 
CGEN_INSN_RELAXABLE 
CGEN_INSN_RELAXED 
CGEN_INSN_NO_DIS 
CGEN_INSN_PBB 
CGEN_INSN_END_BOOLS 
CGEN_INSN_START_NBOOLS 
CGEN_INSN_MACH 
CGEN_INSN_END_NBOOLS 

Definition at line 762 of file frv-desc.h.

Enumerator:
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_ISA 
CGEN_OPERAND_RL_TYPE 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_RELOC 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_ISA 
CGEN_OPERAND_CDATA 
CGEN_OPERAND_ALIGN 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_RELOC 
CGEN_OPERAND_HASH_PREFIX 
CGEN_OPERAND_DOT_PREFIX 
CGEN_OPERAND_POF_PREFIX 
CGEN_OPERAND_PAG_PREFIX 
CGEN_OPERAND_SOF_PREFIX 
CGEN_OPERAND_SEG_PREFIX 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 
CGEN_OPERAND_VIRTUAL 
CGEN_OPERAND_PCREL_ADDR 
CGEN_OPERAND_ABS_ADDR 
CGEN_OPERAND_SIGN_OPT 
CGEN_OPERAND_SIGNED 
CGEN_OPERAND_NEGATIVE 
CGEN_OPERAND_RELAX 
CGEN_OPERAND_SEM_ONLY 
CGEN_OPERAND_END_BOOLS 
CGEN_OPERAND_START_NBOOLS 
CGEN_OPERAND_MACH 
CGEN_OPERAND_END_NBOOLS 

Definition at line 704 of file frv-desc.h.

Enumerator:
CGEN_OPERAND_MAX 
FR30_OPERAND_PC 
FR30_OPERAND_RI 
FR30_OPERAND_RJ 
FR30_OPERAND_RIC 
FR30_OPERAND_RJC 
FR30_OPERAND_CRI 
FR30_OPERAND_CRJ 
FR30_OPERAND_RS1 
FR30_OPERAND_RS2 
FR30_OPERAND_R13 
FR30_OPERAND_R14 
FR30_OPERAND_R15 
FR30_OPERAND_PS 
FR30_OPERAND_U4 
FR30_OPERAND_U4C 
FR30_OPERAND_U8 
FR30_OPERAND_I8 
FR30_OPERAND_UDISP6 
FR30_OPERAND_DISP8 
FR30_OPERAND_DISP9 
FR30_OPERAND_DISP10 
FR30_OPERAND_S10 
FR30_OPERAND_U10 
FR30_OPERAND_I32 
FR30_OPERAND_M4 
FR30_OPERAND_I20 
FR30_OPERAND_DIR8 
FR30_OPERAND_DIR9 
FR30_OPERAND_DIR10 
FR30_OPERAND_LABEL9 
FR30_OPERAND_LABEL12 
FR30_OPERAND_REGLIST_LOW_LD 
FR30_OPERAND_REGLIST_HI_LD 
FR30_OPERAND_REGLIST_LOW_ST 
FR30_OPERAND_REGLIST_HI_ST 
FR30_OPERAND_CC 
FR30_OPERAND_CCC 
FR30_OPERAND_NBIT 
FR30_OPERAND_VBIT 
FR30_OPERAND_ZBIT 
FR30_OPERAND_CBIT 
FR30_OPERAND_IBIT 
FR30_OPERAND_SBIT 
FR30_OPERAND_TBIT 
FR30_OPERAND_D0BIT 
FR30_OPERAND_D1BIT 
FR30_OPERAND_CCR 
FR30_OPERAND_SCR 
FR30_OPERAND_ILM 
FR30_OPERAND_MAX 
FRV_OPERAND_PC 
FRV_OPERAND_PACK 
FRV_OPERAND_GRI 
FRV_OPERAND_GRJ 
FRV_OPERAND_GRK 
FRV_OPERAND_GRKHI 
FRV_OPERAND_GRKLO 
FRV_OPERAND_GRDOUBLEK 
FRV_OPERAND_ACC40SI 
FRV_OPERAND_ACC40UI 
FRV_OPERAND_ACC40SK 
FRV_OPERAND_ACC40UK 
FRV_OPERAND_ACCGI 
FRV_OPERAND_ACCGK 
FRV_OPERAND_CPRI 
FRV_OPERAND_CPRJ 
FRV_OPERAND_CPRK 
FRV_OPERAND_CPRDOUBLEK 
FRV_OPERAND_FRINTI 
FRV_OPERAND_FRINTJ 
FRV_OPERAND_FRINTK 
FRV_OPERAND_FRI 
FRV_OPERAND_FRJ 
FRV_OPERAND_FRK 
FRV_OPERAND_FRKHI 
FRV_OPERAND_FRKLO 
FRV_OPERAND_FRDOUBLEI 
FRV_OPERAND_FRDOUBLEJ 
FRV_OPERAND_FRDOUBLEK 
FRV_OPERAND_CRI 
FRV_OPERAND_CRJ 
FRV_OPERAND_CRJ_INT 
FRV_OPERAND_CRJ_FLOAT 
FRV_OPERAND_CRK 
FRV_OPERAND_CCI 
FRV_OPERAND_ICCI_1 
FRV_OPERAND_ICCI_2 
FRV_OPERAND_ICCI_3 
FRV_OPERAND_FCCI_1 
FRV_OPERAND_FCCI_2 
FRV_OPERAND_FCCI_3 
FRV_OPERAND_FCCK 
FRV_OPERAND_EIR 
FRV_OPERAND_S10 
FRV_OPERAND_U16 
FRV_OPERAND_S16 
FRV_OPERAND_S6 
FRV_OPERAND_S6_1 
FRV_OPERAND_U6 
FRV_OPERAND_S5 
FRV_OPERAND_COND 
FRV_OPERAND_CCOND 
FRV_OPERAND_HINT 
FRV_OPERAND_HINT_TAKEN 
FRV_OPERAND_HINT_NOT_TAKEN 
FRV_OPERAND_LI 
FRV_OPERAND_LOCK 
FRV_OPERAND_DEBUG 
FRV_OPERAND_AE 
FRV_OPERAND_LABEL16 
FRV_OPERAND_LRAE 
FRV_OPERAND_LRAD 
FRV_OPERAND_LRAS 
FRV_OPERAND_TLBPROPX 
FRV_OPERAND_TLBPRL 
FRV_OPERAND_A0 
FRV_OPERAND_A1 
FRV_OPERAND_FRINTIEVEN 
FRV_OPERAND_FRINTJEVEN 
FRV_OPERAND_FRINTKEVEN 
FRV_OPERAND_D12 
FRV_OPERAND_S12 
FRV_OPERAND_U12 
FRV_OPERAND_SPR 
FRV_OPERAND_ULO16 
FRV_OPERAND_SLO16 
FRV_OPERAND_UHI16 
FRV_OPERAND_LABEL24 
FRV_OPERAND_PSR_ESR 
FRV_OPERAND_PSR_S 
FRV_OPERAND_PSR_PS 
FRV_OPERAND_PSR_ET 
FRV_OPERAND_BPSR_BS 
FRV_OPERAND_BPSR_BET 
FRV_OPERAND_TBR_TBA 
FRV_OPERAND_TBR_TT 
FRV_OPERAND_LDANN 
FRV_OPERAND_LDDANN 
FRV_OPERAND_CALLANN 
FRV_OPERAND_MAX 
IP2K_OPERAND_PC 
IP2K_OPERAND_ADDR16CJP 
IP2K_OPERAND_FR 
IP2K_OPERAND_LIT8 
IP2K_OPERAND_BITNO 
IP2K_OPERAND_ADDR16P 
IP2K_OPERAND_ADDR16H 
IP2K_OPERAND_ADDR16L 
IP2K_OPERAND_RETI3 
IP2K_OPERAND_PABITS 
IP2K_OPERAND_ZBIT 
IP2K_OPERAND_CBIT 
IP2K_OPERAND_DCBIT 
IP2K_OPERAND_MAX 
IQ2000_OPERAND_PC 
IQ2000_OPERAND_RS 
IQ2000_OPERAND_RT 
IQ2000_OPERAND_RD 
IQ2000_OPERAND_RD_RS 
IQ2000_OPERAND_RD_RT 
IQ2000_OPERAND_RT_RS 
IQ2000_OPERAND_SHAMT 
IQ2000_OPERAND_IMM 
IQ2000_OPERAND_OFFSET 
IQ2000_OPERAND_BASEOFF 
IQ2000_OPERAND_JMPTARG 
IQ2000_OPERAND_MASK 
IQ2000_OPERAND_MASKQ10 
IQ2000_OPERAND_MASKL 
IQ2000_OPERAND_COUNT 
IQ2000_OPERAND__INDEX 
IQ2000_OPERAND_EXECODE 
IQ2000_OPERAND_BYTECOUNT 
IQ2000_OPERAND_CAM_Y 
IQ2000_OPERAND_CAM_Z 
IQ2000_OPERAND_CM_3FUNC 
IQ2000_OPERAND_CM_4FUNC 
IQ2000_OPERAND_CM_3Z 
IQ2000_OPERAND_CM_4Z 
IQ2000_OPERAND_BASE 
IQ2000_OPERAND_MASKR 
IQ2000_OPERAND_BITNUM 
IQ2000_OPERAND_HI16 
IQ2000_OPERAND_LO16 
IQ2000_OPERAND_MLO16 
IQ2000_OPERAND_JMPTARGQ10 
IQ2000_OPERAND_MAX 
M32C_OPERAND_PC 
M32C_OPERAND_SRC16RNQI 
M32C_OPERAND_SRC16RNHI 
M32C_OPERAND_SRC32RNUNPREFIXEDQI 
M32C_OPERAND_SRC32RNUNPREFIXEDHI 
M32C_OPERAND_SRC32RNUNPREFIXEDSI 
M32C_OPERAND_SRC32RNPREFIXEDQI 
M32C_OPERAND_SRC32RNPREFIXEDHI 
M32C_OPERAND_SRC32RNPREFIXEDSI 
M32C_OPERAND_SRC16AN 
M32C_OPERAND_SRC16ANQI 
M32C_OPERAND_SRC16ANHI 
M32C_OPERAND_SRC32ANUNPREFIXED 
M32C_OPERAND_SRC32ANUNPREFIXEDQI 
M32C_OPERAND_SRC32ANUNPREFIXEDHI 
M32C_OPERAND_SRC32ANUNPREFIXEDSI 
M32C_OPERAND_SRC32ANPREFIXED 
M32C_OPERAND_SRC32ANPREFIXEDQI 
M32C_OPERAND_SRC32ANPREFIXEDHI 
M32C_OPERAND_SRC32ANPREFIXEDSI 
M32C_OPERAND_DST16RNQI 
M32C_OPERAND_DST16RNHI 
M32C_OPERAND_DST16RNSI 
M32C_OPERAND_DST16RNEXTQI 
M32C_OPERAND_DST32R0QI_S 
M32C_OPERAND_DST32R0HI_S 
M32C_OPERAND_DST32RNUNPREFIXEDQI 
M32C_OPERAND_DST32RNUNPREFIXEDHI 
M32C_OPERAND_DST32RNUNPREFIXEDSI 
M32C_OPERAND_DST32RNEXTUNPREFIXEDQI 
M32C_OPERAND_DST32RNEXTUNPREFIXEDHI 
M32C_OPERAND_DST32RNPREFIXEDQI 
M32C_OPERAND_DST32RNPREFIXEDHI 
M32C_OPERAND_DST32RNPREFIXEDSI 
M32C_OPERAND_DST16RNQI_S 
M32C_OPERAND_DST16ANQI_S 
M32C_OPERAND_BIT16RN 
M32C_OPERAND_BIT32RNPREFIXED 
M32C_OPERAND_BIT32RNUNPREFIXED 
M32C_OPERAND_R0 
M32C_OPERAND_R1 
M32C_OPERAND_R2 
M32C_OPERAND_R3 
M32C_OPERAND_R0L 
M32C_OPERAND_R0H 
M32C_OPERAND_R2R0 
M32C_OPERAND_R3R1 
M32C_OPERAND_R1R2R0 
M32C_OPERAND_DST16AN 
M32C_OPERAND_DST16ANQI 
M32C_OPERAND_DST16ANHI 
M32C_OPERAND_DST16ANSI 
M32C_OPERAND_DST16AN_S 
M32C_OPERAND_DST32ANUNPREFIXED 
M32C_OPERAND_DST32ANUNPREFIXEDQI 
M32C_OPERAND_DST32ANUNPREFIXEDHI 
M32C_OPERAND_DST32ANUNPREFIXEDSI 
M32C_OPERAND_DST32ANEXTUNPREFIXED 
M32C_OPERAND_DST32ANPREFIXED 
M32C_OPERAND_DST32ANPREFIXEDQI 
M32C_OPERAND_DST32ANPREFIXEDHI 
M32C_OPERAND_DST32ANPREFIXEDSI 
M32C_OPERAND_BIT16AN 
M32C_OPERAND_BIT32ANPREFIXED 
M32C_OPERAND_BIT32ANUNPREFIXED 
M32C_OPERAND_A0 
M32C_OPERAND_A1 
M32C_OPERAND_SB 
M32C_OPERAND_FB 
M32C_OPERAND_SP 
M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL 
M32C_OPERAND_REGSETPOP 
M32C_OPERAND_REGSETPUSH 
M32C_OPERAND_RN16_PUSH_S 
M32C_OPERAND_AN16_PUSH_S 
M32C_OPERAND_DSP_8_U6 
M32C_OPERAND_DSP_8_U8 
M32C_OPERAND_DSP_8_U16 
M32C_OPERAND_DSP_8_S8 
M32C_OPERAND_DSP_8_S24 
M32C_OPERAND_DSP_8_U24 
M32C_OPERAND_DSP_10_U6 
M32C_OPERAND_DSP_16_U8 
M32C_OPERAND_DSP_16_U16 
M32C_OPERAND_DSP_16_U20 
M32C_OPERAND_DSP_16_U24 
M32C_OPERAND_DSP_16_S8 
M32C_OPERAND_DSP_16_S16 
M32C_OPERAND_DSP_24_U8 
M32C_OPERAND_DSP_24_U16 
M32C_OPERAND_DSP_24_U20 
M32C_OPERAND_DSP_24_U24 
M32C_OPERAND_DSP_24_S8 
M32C_OPERAND_DSP_24_S16 
M32C_OPERAND_DSP_32_U8 
M32C_OPERAND_DSP_32_U16 
M32C_OPERAND_DSP_32_U24 
M32C_OPERAND_DSP_32_U20