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cell-binutils  2.17cvs20070401
fr30-desc.h
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00001 /* CPU data header for fr30.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #ifndef FR30_CPU_H
00026 #define FR30_CPU_H
00027 
00028 #include "opcode/cgen-bitset.h"
00029 
00030 #define CGEN_ARCH fr30
00031 
00032 /* Given symbol S, return fr30_cgen_<S>.  */
00033 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00034 #define CGEN_SYM(s) fr30##_cgen_##s
00035 #else
00036 #define CGEN_SYM(s) fr30_cgen_s
00037 #endif
00038 
00039 
00040 /* Selected cpu families.  */
00041 #define HAVE_CPU_FR30BF
00042 
00043 #define CGEN_INSN_LSB0_P 0
00044 
00045 /* Minimum size of any insn (in bytes).  */
00046 #define CGEN_MIN_INSN_SIZE 2
00047 
00048 /* Maximum size of any insn (in bytes).  */
00049 #define CGEN_MAX_INSN_SIZE 6
00050 
00051 #define CGEN_INT_INSN_P 0
00052 
00053 /* Maximum number of syntax elements in an instruction.  */
00054 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
00055 
00056 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
00057    e.g. In "b,a foo" the ",a" is an operand.  If mnemonics have operands
00058    we can't hash on everything up to the space.  */
00059 #define CGEN_MNEMONIC_OPERANDS
00060 
00061 /* Maximum number of fields in an instruction.  */
00062 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
00063 
00064 /* Enums.  */
00065 
00066 /* Enum declaration for insn op1 enums.  */
00067 typedef enum insn_op1 {
00068   OP1_0, OP1_1, OP1_2, OP1_3
00069  , OP1_4, OP1_5, OP1_6, OP1_7
00070  , OP1_8, OP1_9, OP1_A, OP1_B
00071  , OP1_C, OP1_D, OP1_E, OP1_F
00072 } INSN_OP1;
00073 
00074 /* Enum declaration for insn op2 enums.  */
00075 typedef enum insn_op2 {
00076   OP2_0, OP2_1, OP2_2, OP2_3
00077  , OP2_4, OP2_5, OP2_6, OP2_7
00078  , OP2_8, OP2_9, OP2_A, OP2_B
00079  , OP2_C, OP2_D, OP2_E, OP2_F
00080 } INSN_OP2;
00081 
00082 /* Enum declaration for insn op3 enums.  */
00083 typedef enum insn_op3 {
00084   OP3_0, OP3_1, OP3_2, OP3_3
00085  , OP3_4, OP3_5, OP3_6, OP3_7
00086  , OP3_8, OP3_9, OP3_A, OP3_B
00087  , OP3_C, OP3_D, OP3_E, OP3_F
00088 } INSN_OP3;
00089 
00090 /* Enum declaration for insn op4 enums.  */
00091 typedef enum insn_op4 {
00092   OP4_0
00093 } INSN_OP4;
00094 
00095 /* Enum declaration for insn op5 enums.  */
00096 typedef enum insn_op5 {
00097   OP5_0, OP5_1
00098 } INSN_OP5;
00099 
00100 /* Enum declaration for insn cc enums.  */
00101 typedef enum insn_cc {
00102   CC_RA, CC_NO, CC_EQ, CC_NE
00103  , CC_C, CC_NC, CC_N, CC_P
00104  , CC_V, CC_NV, CC_LT, CC_GE
00105  , CC_LE, CC_GT, CC_LS, CC_HI
00106 } INSN_CC;
00107 
00108 /* Enum declaration for .  */
00109 typedef enum gr_names {
00110   H_GR_R0 = 0, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3
00111  , H_GR_R4 = 4, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7
00112  , H_GR_R8 = 8, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11
00113  , H_GR_R12 = 12, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
00114  , H_GR_AC = 13, H_GR_FP = 14, H_GR_SP = 15
00115 } GR_NAMES;
00116 
00117 /* Enum declaration for .  */
00118 typedef enum cr_names {
00119   H_CR_CR0, H_CR_CR1, H_CR_CR2, H_CR_CR3
00120  , H_CR_CR4, H_CR_CR5, H_CR_CR6, H_CR_CR7
00121  , H_CR_CR8, H_CR_CR9, H_CR_CR10, H_CR_CR11
00122  , H_CR_CR12, H_CR_CR13, H_CR_CR14, H_CR_CR15
00123 } CR_NAMES;
00124 
00125 /* Enum declaration for .  */
00126 typedef enum dr_names {
00127   H_DR_TBR, H_DR_RP, H_DR_SSP, H_DR_USP
00128  , H_DR_MDH, H_DR_MDL
00129 } DR_NAMES;
00130 
00131 /* Attributes.  */
00132 
00133 /* Enum declaration for machine type selection.  */
00134 typedef enum mach_attr {
00135   MACH_BASE, MACH_FR30, MACH_MAX
00136 } MACH_ATTR;
00137 
00138 /* Enum declaration for instruction set selection.  */
00139 typedef enum isa_attr {
00140   ISA_FR30, ISA_MAX
00141 } ISA_ATTR;
00142 
00143 /* Number of architecture variants.  */
00144 #define MAX_ISAS  1
00145 #define MAX_MACHS ((int) MACH_MAX)
00146 
00147 /* Ifield support.  */
00148 
00149 /* Ifield attribute indices.  */
00150 
00151 /* Enum declaration for cgen_ifld attrs.  */
00152 typedef enum cgen_ifld_attr {
00153   CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
00154  , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
00155  , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
00156 } CGEN_IFLD_ATTR;
00157 
00158 /* Number of non-boolean elements in cgen_ifld_attr.  */
00159 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
00160 
00161 /* cgen_ifld attribute accessor macros.  */
00162 #define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
00163 #define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
00164 #define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
00165 #define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
00166 #define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
00167 #define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
00168 #define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
00169 
00170 /* Enum declaration for fr30 ifield types.  */
00171 typedef enum ifield_type {
00172   FR30_F_NIL, FR30_F_ANYOF, FR30_F_OP1, FR30_F_OP2
00173  , FR30_F_OP3, FR30_F_OP4, FR30_F_OP5, FR30_F_CC
00174  , FR30_F_CCC, FR30_F_RJ, FR30_F_RI, FR30_F_RS1
00175  , FR30_F_RS2, FR30_F_RJC, FR30_F_RIC, FR30_F_CRJ
00176  , FR30_F_CRI, FR30_F_U4, FR30_F_U4C, FR30_F_I4
00177  , FR30_F_M4, FR30_F_U8, FR30_F_I8, FR30_F_I20_4
00178  , FR30_F_I20_16, FR30_F_I20, FR30_F_I32, FR30_F_UDISP6
00179  , FR30_F_DISP8, FR30_F_DISP9, FR30_F_DISP10, FR30_F_S10
00180  , FR30_F_U10, FR30_F_REL9, FR30_F_DIR8, FR30_F_DIR9
00181  , FR30_F_DIR10, FR30_F_REL12, FR30_F_REGLIST_HI_ST, FR30_F_REGLIST_LOW_ST
00182  , FR30_F_REGLIST_HI_LD, FR30_F_REGLIST_LOW_LD, FR30_F_MAX
00183 } IFIELD_TYPE;
00184 
00185 #define MAX_IFLD ((int) FR30_F_MAX)
00186 
00187 /* Hardware attribute indices.  */
00188 
00189 /* Enum declaration for cgen_hw attrs.  */
00190 typedef enum cgen_hw_attr {
00191   CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
00192  , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
00193 } CGEN_HW_ATTR;
00194 
00195 /* Number of non-boolean elements in cgen_hw_attr.  */
00196 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
00197 
00198 /* cgen_hw attribute accessor macros.  */
00199 #define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
00200 #define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
00201 #define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
00202 #define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
00203 #define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
00204 
00205 /* Enum declaration for fr30 hardware types.  */
00206 typedef enum cgen_hw_type {
00207   HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
00208  , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CR
00209  , HW_H_DR, HW_H_PS, HW_H_R13, HW_H_R14
00210  , HW_H_R15, HW_H_NBIT, HW_H_ZBIT, HW_H_VBIT
00211  , HW_H_CBIT, HW_H_IBIT, HW_H_SBIT, HW_H_TBIT
00212  , HW_H_D0BIT, HW_H_D1BIT, HW_H_CCR, HW_H_SCR
00213  , HW_H_ILM, HW_MAX
00214 } CGEN_HW_TYPE;
00215 
00216 #define MAX_HW ((int) HW_MAX)
00217 
00218 /* Operand attribute indices.  */
00219 
00220 /* Enum declaration for cgen_operand attrs.  */
00221 typedef enum cgen_operand_attr {
00222   CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
00223  , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
00224  , CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH
00225  , CGEN_OPERAND_END_NBOOLS
00226 } CGEN_OPERAND_ATTR;
00227 
00228 /* Number of non-boolean elements in cgen_operand_attr.  */
00229 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
00230 
00231 /* cgen_operand attribute accessor macros.  */
00232 #define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
00233 #define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
00234 #define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
00235 #define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
00236 #define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
00237 #define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
00238 #define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
00239 #define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
00240 #define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
00241 #define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0)
00242 
00243 /* Enum declaration for fr30 operand types.  */
00244 typedef enum cgen_operand_type {
00245   FR30_OPERAND_PC, FR30_OPERAND_RI, FR30_OPERAND_RJ, FR30_OPERAND_RIC
00246  , FR30_OPERAND_RJC, FR30_OPERAND_CRI, FR30_OPERAND_CRJ, FR30_OPERAND_RS1
00247  , FR30_OPERAND_RS2, FR30_OPERAND_R13, FR30_OPERAND_R14, FR30_OPERAND_R15
00248  , FR30_OPERAND_PS, FR30_OPERAND_U4, FR30_OPERAND_U4C, FR30_OPERAND_U8
00249  , FR30_OPERAND_I8, FR30_OPERAND_UDISP6, FR30_OPERAND_DISP8, FR30_OPERAND_DISP9
00250  , FR30_OPERAND_DISP10, FR30_OPERAND_S10, FR30_OPERAND_U10, FR30_OPERAND_I32
00251  , FR30_OPERAND_M4, FR30_OPERAND_I20, FR30_OPERAND_DIR8, FR30_OPERAND_DIR9
00252  , FR30_OPERAND_DIR10, FR30_OPERAND_LABEL9, FR30_OPERAND_LABEL12, FR30_OPERAND_REGLIST_LOW_LD
00253  , FR30_OPERAND_REGLIST_HI_LD, FR30_OPERAND_REGLIST_LOW_ST, FR30_OPERAND_REGLIST_HI_ST, FR30_OPERAND_CC
00254  , FR30_OPERAND_CCC, FR30_OPERAND_NBIT, FR30_OPERAND_VBIT, FR30_OPERAND_ZBIT
00255  , FR30_OPERAND_CBIT, FR30_OPERAND_IBIT, FR30_OPERAND_SBIT, FR30_OPERAND_TBIT
00256  , FR30_OPERAND_D0BIT, FR30_OPERAND_D1BIT, FR30_OPERAND_CCR, FR30_OPERAND_SCR
00257  , FR30_OPERAND_ILM, FR30_OPERAND_MAX
00258 } CGEN_OPERAND_TYPE;
00259 
00260 /* Number of operands types.  */
00261 #define MAX_OPERANDS 49
00262 
00263 /* Maximum number of operands referenced by any insn.  */
00264 #define MAX_OPERAND_INSTANCES 8
00265 
00266 /* Insn attribute indices.  */
00267 
00268 /* Enum declaration for cgen_insn attrs.  */
00269 typedef enum cgen_insn_attr {
00270   CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
00271  , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
00272  , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_NOT_IN_DELAY_SLOT, CGEN_INSN_END_BOOLS
00273  , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
00274 } CGEN_INSN_ATTR;
00275 
00276 /* Number of non-boolean elements in cgen_insn_attr.  */
00277 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
00278 
00279 /* cgen_insn attribute accessor macros.  */
00280 #define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
00281 #define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
00282 #define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
00283 #define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
00284 #define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
00285 #define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
00286 #define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
00287 #define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
00288 #define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
00289 #define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
00290 #define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
00291 #define CGEN_ATTR_CGEN_INSN_NOT_IN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NOT_IN_DELAY_SLOT)) != 0)
00292 
00293 /* cgen.h uses things we just defined.  */
00294 #include "opcode/cgen.h"
00295 
00296 extern const struct cgen_ifld fr30_cgen_ifld_table[];
00297 
00298 /* Attributes.  */
00299 extern const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[];
00300 extern const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[];
00301 extern const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[];
00302 extern const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[];
00303 
00304 /* Hardware decls.  */
00305 
00306 extern CGEN_KEYWORD fr30_cgen_opval_gr_names;
00307 extern CGEN_KEYWORD fr30_cgen_opval_cr_names;
00308 extern CGEN_KEYWORD fr30_cgen_opval_dr_names;
00309 extern CGEN_KEYWORD fr30_cgen_opval_h_ps;
00310 extern CGEN_KEYWORD fr30_cgen_opval_h_r13;
00311 extern CGEN_KEYWORD fr30_cgen_opval_h_r14;
00312 extern CGEN_KEYWORD fr30_cgen_opval_h_r15;
00313 
00314 extern const CGEN_HW_ENTRY fr30_cgen_hw_table[];
00315 
00316 
00317 
00318 #endif /* FR30_CPU_H */