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cell-binutils  2.17cvs20070401
fr30-desc.c
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00001 /* CPU data for fr30.
00002 
00003 THIS FILE IS MACHINE GENERATED WITH CGEN.
00004 
00005 Copyright 1996-2005 Free Software Foundation, Inc.
00006 
00007 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
00008 
00009 This program is free software; you can redistribute it and/or modify
00010 it under the terms of the GNU General Public License as published by
00011 the Free Software Foundation; either version 2, or (at your option)
00012 any later version.
00013 
00014 This program is distributed in the hope that it will be useful,
00015 but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License along
00020 with this program; if not, write to the Free Software Foundation, Inc.,
00021 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00022 
00023 */
00024 
00025 #include "sysdep.h"
00026 #include <stdio.h>
00027 #include <stdarg.h>
00028 #include "ansidecl.h"
00029 #include "bfd.h"
00030 #include "symcat.h"
00031 #include "fr30-desc.h"
00032 #include "fr30-opc.h"
00033 #include "opintl.h"
00034 #include "libiberty.h"
00035 #include "xregex.h"
00036 
00037 /* Attributes.  */
00038 
00039 static const CGEN_ATTR_ENTRY bool_attr[] =
00040 {
00041   { "#f", 0 },
00042   { "#t", 1 },
00043   { 0, 0 }
00044 };
00045 
00046 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
00047 {
00048   { "base", MACH_BASE },
00049   { "fr30", MACH_FR30 },
00050   { "max", MACH_MAX },
00051   { 0, 0 }
00052 };
00053 
00054 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
00055 {
00056   { "fr30", ISA_FR30 },
00057   { "max", ISA_MAX },
00058   { 0, 0 }
00059 };
00060 
00061 const CGEN_ATTR_TABLE fr30_cgen_ifield_attr_table[] =
00062 {
00063   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00064   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00065   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00066   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00067   { "RESERVED", &bool_attr[0], &bool_attr[0] },
00068   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00069   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00070   { 0, 0, 0 }
00071 };
00072 
00073 const CGEN_ATTR_TABLE fr30_cgen_hardware_attr_table[] =
00074 {
00075   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00076   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00077   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
00078   { "PC", &bool_attr[0], &bool_attr[0] },
00079   { "PROFILE", &bool_attr[0], &bool_attr[0] },
00080   { 0, 0, 0 }
00081 };
00082 
00083 const CGEN_ATTR_TABLE fr30_cgen_operand_attr_table[] =
00084 {
00085   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00086   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00087   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
00088   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
00089   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
00090   { "SIGNED", &bool_attr[0], &bool_attr[0] },
00091   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
00092   { "RELAX", &bool_attr[0], &bool_attr[0] },
00093   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
00094   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
00095   { 0, 0, 0 }
00096 };
00097 
00098 const CGEN_ATTR_TABLE fr30_cgen_insn_attr_table[] =
00099 {
00100   { "MACH", & MACH_attr[0], & MACH_attr[0] },
00101   { "ALIAS", &bool_attr[0], &bool_attr[0] },
00102   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
00103   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
00104   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
00105   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
00106   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00107   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
00108   { "RELAXED", &bool_attr[0], &bool_attr[0] },
00109   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
00110   { "PBB", &bool_attr[0], &bool_attr[0] },
00111   { "NOT-IN-DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
00112   { 0, 0, 0 }
00113 };
00114 
00115 /* Instruction set variants.  */
00116 
00117 static const CGEN_ISA fr30_cgen_isa_table[] = {
00118   { "fr30", 16, 16, 16, 48 },
00119   { 0, 0, 0, 0, 0 }
00120 };
00121 
00122 /* Machine variants.  */
00123 
00124 static const CGEN_MACH fr30_cgen_mach_table[] = {
00125   { "fr30", "fr30", MACH_FR30, 0 },
00126   { 0, 0, 0, 0 }
00127 };
00128 
00129 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_gr_names_entries[] =
00130 {
00131   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
00132   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
00133   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
00134   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
00135   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
00136   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
00137   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
00138   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
00139   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
00140   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
00141   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
00142   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
00143   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
00144   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
00145   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
00146   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 },
00147   { "ac", 13, {0, {{{0, 0}}}}, 0, 0 },
00148   { "fp", 14, {0, {{{0, 0}}}}, 0, 0 },
00149   { "sp", 15, {0, {{{0, 0}}}}, 0, 0 }
00150 };
00151 
00152 CGEN_KEYWORD fr30_cgen_opval_gr_names =
00153 {
00154   & fr30_cgen_opval_gr_names_entries[0],
00155   19,
00156   0, 0, 0, 0, ""
00157 };
00158 
00159 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_cr_names_entries[] =
00160 {
00161   { "cr0", 0, {0, {{{0, 0}}}}, 0, 0 },
00162   { "cr1", 1, {0, {{{0, 0}}}}, 0, 0 },
00163   { "cr2", 2, {0, {{{0, 0}}}}, 0, 0 },
00164   { "cr3", 3, {0, {{{0, 0}}}}, 0, 0 },
00165   { "cr4", 4, {0, {{{0, 0}}}}, 0, 0 },
00166   { "cr5", 5, {0, {{{0, 0}}}}, 0, 0 },
00167   { "cr6", 6, {0, {{{0, 0}}}}, 0, 0 },
00168   { "cr7", 7, {0, {{{0, 0}}}}, 0, 0 },
00169   { "cr8", 8, {0, {{{0, 0}}}}, 0, 0 },
00170   { "cr9", 9, {0, {{{0, 0}}}}, 0, 0 },
00171   { "cr10", 10, {0, {{{0, 0}}}}, 0, 0 },
00172   { "cr11", 11, {0, {{{0, 0}}}}, 0, 0 },
00173   { "cr12", 12, {0, {{{0, 0}}}}, 0, 0 },
00174   { "cr13", 13, {0, {{{0, 0}}}}, 0, 0 },
00175   { "cr14", 14, {0, {{{0, 0}}}}, 0, 0 },
00176   { "cr15", 15, {0, {{{0, 0}}}}, 0, 0 }
00177 };
00178 
00179 CGEN_KEYWORD fr30_cgen_opval_cr_names =
00180 {
00181   & fr30_cgen_opval_cr_names_entries[0],
00182   16,
00183   0, 0, 0, 0, ""
00184 };
00185 
00186 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_dr_names_entries[] =
00187 {
00188   { "tbr", 0, {0, {{{0, 0}}}}, 0, 0 },
00189   { "rp", 1, {0, {{{0, 0}}}}, 0, 0 },
00190   { "ssp", 2, {0, {{{0, 0}}}}, 0, 0 },
00191   { "usp", 3, {0, {{{0, 0}}}}, 0, 0 },
00192   { "mdh", 4, {0, {{{0, 0}}}}, 0, 0 },
00193   { "mdl", 5, {0, {{{0, 0}}}}, 0, 0 }
00194 };
00195 
00196 CGEN_KEYWORD fr30_cgen_opval_dr_names =
00197 {
00198   & fr30_cgen_opval_dr_names_entries[0],
00199   6,
00200   0, 0, 0, 0, ""
00201 };
00202 
00203 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_ps_entries[] =
00204 {
00205   { "ps", 0, {0, {{{0, 0}}}}, 0, 0 }
00206 };
00207 
00208 CGEN_KEYWORD fr30_cgen_opval_h_ps =
00209 {
00210   & fr30_cgen_opval_h_ps_entries[0],
00211   1,
00212   0, 0, 0, 0, ""
00213 };
00214 
00215 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r13_entries[] =
00216 {
00217   { "r13", 0, {0, {{{0, 0}}}}, 0, 0 }
00218 };
00219 
00220 CGEN_KEYWORD fr30_cgen_opval_h_r13 =
00221 {
00222   & fr30_cgen_opval_h_r13_entries[0],
00223   1,
00224   0, 0, 0, 0, ""
00225 };
00226 
00227 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r14_entries[] =
00228 {
00229   { "r14", 0, {0, {{{0, 0}}}}, 0, 0 }
00230 };
00231 
00232 CGEN_KEYWORD fr30_cgen_opval_h_r14 =
00233 {
00234   & fr30_cgen_opval_h_r14_entries[0],
00235   1,
00236   0, 0, 0, 0, ""
00237 };
00238 
00239 static CGEN_KEYWORD_ENTRY fr30_cgen_opval_h_r15_entries[] =
00240 {
00241   { "r15", 0, {0, {{{0, 0}}}}, 0, 0 }
00242 };
00243 
00244 CGEN_KEYWORD fr30_cgen_opval_h_r15 =
00245 {
00246   & fr30_cgen_opval_h_r15_entries[0],
00247   1,
00248   0, 0, 0, 0, ""
00249 };
00250 
00251 
00252 /* The hardware table.  */
00253 
00254 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00255 #define A(a) (1 << CGEN_HW_##a)
00256 #else
00257 #define A(a) (1 << CGEN_HW_a)
00258 #endif
00259 
00260 const CGEN_HW_ENTRY fr30_cgen_hw_table[] =
00261 {
00262   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00263   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00264   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00265   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00266   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00267   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
00268   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
00269   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_cr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00270   { "h-dr", HW_H_DR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_dr_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00271   { "h-ps", HW_H_PS, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_ps, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00272   { "h-r13", HW_H_R13, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r13, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00273   { "h-r14", HW_H_R14, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r14, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00274   { "h-r15", HW_H_R15, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_h_r15, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00275   { "h-nbit", HW_H_NBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00276   { "h-zbit", HW_H_ZBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00277   { "h-vbit", HW_H_VBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00278   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00279   { "h-ibit", HW_H_IBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00280   { "h-sbit", HW_H_SBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00281   { "h-tbit", HW_H_TBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00282   { "h-d0bit", HW_H_D0BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00283   { "h-d1bit", HW_H_D1BIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00284   { "h-ccr", HW_H_CCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00285   { "h-scr", HW_H_SCR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00286   { "h-ilm", HW_H_ILM, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00287   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00288 };
00289 
00290 #undef A
00291 
00292 
00293 /* The instruction field table.  */
00294 
00295 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00296 #define A(a) (1 << CGEN_IFLD_##a)
00297 #else
00298 #define A(a) (1 << CGEN_IFLD_a)
00299 #endif
00300 
00301 const CGEN_IFLD fr30_cgen_ifld_table[] =
00302 {
00303   { FR30_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00304   { FR30_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00305   { FR30_F_OP1, "f-op1", 0, 16, 0, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00306   { FR30_F_OP2, "f-op2", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00307   { FR30_F_OP3, "f-op3", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00308   { FR30_F_OP4, "f-op4", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00309   { FR30_F_OP5, "f-op5", 0, 16, 4, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00310   { FR30_F_CC, "f-cc", 0, 16, 4, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00311   { FR30_F_CCC, "f-ccc", 16, 16, 0, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00312   { FR30_F_RJ, "f-Rj", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00313   { FR30_F_RI, "f-Ri", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00314   { FR30_F_RS1, "f-Rs1", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00315   { FR30_F_RS2, "f-Rs2", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00316   { FR30_F_RJC, "f-Rjc", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00317   { FR30_F_RIC, "f-Ric", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00318   { FR30_F_CRJ, "f-CRj", 16, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00319   { FR30_F_CRI, "f-CRi", 16, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00320   { FR30_F_U4, "f-u4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00321   { FR30_F_U4C, "f-u4c", 0, 16, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00322   { FR30_F_I4, "f-i4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00323   { FR30_F_M4, "f-m4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00324   { FR30_F_U8, "f-u8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00325   { FR30_F_I8, "f-i8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00326   { FR30_F_I20_4, "f-i20-4", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00327   { FR30_F_I20_16, "f-i20-16", 16, 16, 0, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00328   { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00329   { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00330   { FR30_F_UDISP6, "f-udisp6", 0, 16, 8, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00331   { FR30_F_DISP8, "f-disp8", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00332   { FR30_F_DISP9, "f-disp9", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00333   { FR30_F_DISP10, "f-disp10", 0, 16, 4, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00334   { FR30_F_S10, "f-s10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00335   { FR30_F_U10, "f-u10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00336   { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00337   { FR30_F_DIR8, "f-dir8", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00338   { FR30_F_DIR9, "f-dir9", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00339   { FR30_F_DIR10, "f-dir10", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00340   { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00341   { FR30_F_REGLIST_HI_ST, "f-reglist_hi_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00342   { FR30_F_REGLIST_LOW_ST, "f-reglist_low_st", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00343   { FR30_F_REGLIST_HI_LD, "f-reglist_hi_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00344   { FR30_F_REGLIST_LOW_LD, "f-reglist_low_ld", 0, 16, 8, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00345   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
00346 };
00347 
00348 #undef A
00349 
00350 
00351 
00352 /* multi ifield declarations */
00353 
00354 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [];
00355 
00356 
00357 /* multi ifield definitions */
00358 
00359 const CGEN_MAYBE_MULTI_IFLD FR30_F_I20_MULTI_IFIELD [] =
00360 {
00361     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_4] } },
00362     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I20_16] } },
00363     { 0, { (const PTR) 0 } }
00364 };
00365 
00366 /* The operand table.  */
00367 
00368 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00369 #define A(a) (1 << CGEN_OPERAND_##a)
00370 #else
00371 #define A(a) (1 << CGEN_OPERAND_a)
00372 #endif
00373 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00374 #define OPERAND(op) FR30_OPERAND_##op
00375 #else
00376 #define OPERAND(op) FR30_OPERAND_op
00377 #endif
00378 
00379 const CGEN_OPERAND fr30_cgen_operand_table[] =
00380 {
00381 /* pc: program counter */
00382   { "pc", FR30_OPERAND_PC, HW_H_PC, 0, 0,
00383     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_NIL] } }, 
00384     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00385 /* Ri: destination register */
00386   { "Ri", FR30_OPERAND_RI, HW_H_GR, 12, 4,
00387     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RI] } }, 
00388     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00389 /* Rj: source register */
00390   { "Rj", FR30_OPERAND_RJ, HW_H_GR, 8, 4,
00391     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJ] } }, 
00392     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00393 /* Ric: target register coproc insn */
00394   { "Ric", FR30_OPERAND_RIC, HW_H_GR, 12, 4,
00395     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RIC] } }, 
00396     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00397 /* Rjc: source register coproc insn */
00398   { "Rjc", FR30_OPERAND_RJC, HW_H_GR, 8, 4,
00399     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RJC] } }, 
00400     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00401 /* CRi: coprocessor register */
00402   { "CRi", FR30_OPERAND_CRI, HW_H_CR, 12, 4,
00403     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRI] } }, 
00404     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00405 /* CRj: coprocessor register */
00406   { "CRj", FR30_OPERAND_CRJ, HW_H_CR, 8, 4,
00407     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CRJ] } }, 
00408     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00409 /* Rs1: dedicated register */
00410   { "Rs1", FR30_OPERAND_RS1, HW_H_DR, 8, 4,
00411     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS1] } }, 
00412     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00413 /* Rs2: dedicated register */
00414   { "Rs2", FR30_OPERAND_RS2, HW_H_DR, 12, 4,
00415     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_RS2] } }, 
00416     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00417 /* R13: General Register 13 */
00418   { "R13", FR30_OPERAND_R13, HW_H_R13, 0, 0,
00419     { 0, { (const PTR) 0 } }, 
00420     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00421 /* R14: General Register 14 */
00422   { "R14", FR30_OPERAND_R14, HW_H_R14, 0, 0,
00423     { 0, { (const PTR) 0 } }, 
00424     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00425 /* R15: General Register 15 */
00426   { "R15", FR30_OPERAND_R15, HW_H_R15, 0, 0,
00427     { 0, { (const PTR) 0 } }, 
00428     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00429 /* ps: Program Status register */
00430   { "ps", FR30_OPERAND_PS, HW_H_PS, 0, 0,
00431     { 0, { (const PTR) 0 } }, 
00432     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00433 /* u4: 4  bit unsigned immediate */
00434   { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
00435     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4] } }, 
00436     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00437 /* u4c: 4  bit unsigned immediate */
00438   { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
00439     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U4C] } }, 
00440     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00441 /* u8: 8  bit unsigned immediate */
00442   { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
00443     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U8] } }, 
00444     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00445 /* i8: 8  bit unsigned immediate */
00446   { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
00447     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I8] } }, 
00448     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00449 /* udisp6: 6  bit unsigned immediate */
00450   { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
00451     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_UDISP6] } }, 
00452     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00453 /* disp8: 8  bit signed   immediate */
00454   { "disp8", FR30_OPERAND_DISP8, HW_H_SINT, 4, 8,
00455     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP8] } }, 
00456     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00457 /* disp9: 9  bit signed   immediate */
00458   { "disp9", FR30_OPERAND_DISP9, HW_H_SINT, 4, 8,
00459     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP9] } }, 
00460     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00461 /* disp10: 10 bit signed   immediate */
00462   { "disp10", FR30_OPERAND_DISP10, HW_H_SINT, 4, 8,
00463     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DISP10] } }, 
00464     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00465 /* s10: 10 bit signed   immediate */
00466   { "s10", FR30_OPERAND_S10, HW_H_SINT, 8, 8,
00467     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_S10] } }, 
00468     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00469 /* u10: 10 bit unsigned immediate */
00470   { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
00471     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_U10] } }, 
00472     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00473 /* i32: 32 bit immediate */
00474   { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
00475     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_I32] } }, 
00476     { 0|A(HASH_PREFIX)|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } }  },
00477 /* m4: 4  bit negative immediate */
00478   { "m4", FR30_OPERAND_M4, HW_H_SINT, 8, 4,
00479     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_M4] } }, 
00480     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00481 /* i20: 20 bit immediate */
00482   { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
00483     { 2, { (const PTR) &FR30_F_I20_MULTI_IFIELD[0] } }, 
00484     { 0|A(HASH_PREFIX)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } }  },
00485 /* dir8: 8  bit direct address */
00486   { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
00487     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR8] } }, 
00488     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00489 /* dir9: 9  bit direct address */
00490   { "dir9", FR30_OPERAND_DIR9, HW_H_UINT, 8, 8,
00491     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR9] } }, 
00492     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00493 /* dir10: 10 bit direct address */
00494   { "dir10", FR30_OPERAND_DIR10, HW_H_UINT, 8, 8,
00495     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_DIR10] } }, 
00496     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00497 /* label9: 9  bit pc relative address */
00498   { "label9", FR30_OPERAND_LABEL9, HW_H_IADDR, 8, 8,
00499     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL9] } }, 
00500     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00501 /* label12: 12 bit pc relative address */
00502   { "label12", FR30_OPERAND_LABEL12, HW_H_IADDR, 5, 11,
00503     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REL12] } }, 
00504     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
00505 /* reglist_low_ld: 8 bit low register mask for ldm */
00506   { "reglist_low_ld", FR30_OPERAND_REGLIST_LOW_LD, HW_H_UINT, 8, 8,
00507     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_LD] } }, 
00508     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00509 /* reglist_hi_ld: 8 bit high register mask for ldm */
00510   { "reglist_hi_ld", FR30_OPERAND_REGLIST_HI_LD, HW_H_UINT, 8, 8,
00511     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_LD] } }, 
00512     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00513 /* reglist_low_st: 8 bit low register mask for stm */
00514   { "reglist_low_st", FR30_OPERAND_REGLIST_LOW_ST, HW_H_UINT, 8, 8,
00515     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_LOW_ST] } }, 
00516     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00517 /* reglist_hi_st: 8 bit high register mask for stm */
00518   { "reglist_hi_st", FR30_OPERAND_REGLIST_HI_ST, HW_H_UINT, 8, 8,
00519     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_REGLIST_HI_ST] } }, 
00520     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00521 /* cc: condition codes */
00522   { "cc", FR30_OPERAND_CC, HW_H_UINT, 4, 4,
00523     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CC] } }, 
00524     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
00525 /* ccc: coprocessor calc */
00526   { "ccc", FR30_OPERAND_CCC, HW_H_UINT, 0, 8,
00527     { 0, { (const PTR) &fr30_cgen_ifld_table[FR30_F_CCC] } }, 
00528     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
00529 /* nbit: negative   bit */
00530   { "nbit", FR30_OPERAND_NBIT, HW_H_NBIT, 0, 0,
00531     { 0, { (const PTR) 0 } }, 
00532     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00533 /* vbit: overflow   bit */
00534   { "vbit", FR30_OPERAND_VBIT, HW_H_VBIT, 0, 0,
00535     { 0, { (const PTR) 0 } }, 
00536     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00537 /* zbit: zero       bit */
00538   { "zbit", FR30_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
00539     { 0, { (const PTR) 0 } }, 
00540     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00541 /* cbit: carry      bit */
00542   { "cbit", FR30_OPERAND_CBIT, HW_H_CBIT, 0, 0,
00543     { 0, { (const PTR) 0 } }, 
00544     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00545 /* ibit: interrupt  bit */
00546   { "ibit", FR30_OPERAND_IBIT, HW_H_IBIT, 0, 0,
00547     { 0, { (const PTR) 0 } }, 
00548     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00549 /* sbit: stack      bit */
00550   { "sbit", FR30_OPERAND_SBIT, HW_H_SBIT, 0, 0,
00551     { 0, { (const PTR) 0 } }, 
00552     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00553 /* tbit: trace trap bit */
00554   { "tbit", FR30_OPERAND_TBIT, HW_H_TBIT, 0, 0,
00555     { 0, { (const PTR) 0 } }, 
00556     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00557 /* d0bit: division 0 bit */
00558   { "d0bit", FR30_OPERAND_D0BIT, HW_H_D0BIT, 0, 0,
00559     { 0, { (const PTR) 0 } }, 
00560     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00561 /* d1bit: division 1 bit */
00562   { "d1bit", FR30_OPERAND_D1BIT, HW_H_D1BIT, 0, 0,
00563     { 0, { (const PTR) 0 } }, 
00564     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00565 /* ccr: condition code bits */
00566   { "ccr", FR30_OPERAND_CCR, HW_H_CCR, 0, 0,
00567     { 0, { (const PTR) 0 } }, 
00568     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00569 /* scr: system condition bits */
00570   { "scr", FR30_OPERAND_SCR, HW_H_SCR, 0, 0,
00571     { 0, { (const PTR) 0 } }, 
00572     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00573 /* ilm: interrupt level mask */
00574   { "ilm", FR30_OPERAND_ILM, HW_H_ILM, 0, 0,
00575     { 0, { (const PTR) 0 } }, 
00576     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
00577 /* sentinel */
00578   { 0, 0, 0, 0, 0,
00579     { 0, { (const PTR) 0 } },
00580     { 0, { { { (1<<MACH_BASE), 0 } } } } }
00581 };
00582 
00583 #undef A
00584 
00585 
00586 /* The instruction table.  */
00587 
00588 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
00589 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
00590 #define A(a) (1 << CGEN_INSN_##a)
00591 #else
00592 #define A(a) (1 << CGEN_INSN_a)
00593 #endif
00594 
00595 static const CGEN_IBASE fr30_cgen_insn_table[MAX_INSNS] =
00596 {
00597   /* Special null first entry.
00598      A `num' value of zero is thus invalid.
00599      Also, the special `invalid' insn resides here.  */
00600   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
00601 /* add $Rj,$Ri */
00602   {
00603     FR30_INSN_ADD, "add", "add", 16,
00604     { 0, { { { (1<<MACH_BASE), 0 } } } }
00605   },
00606 /* add $u4,$Ri */
00607   {
00608     FR30_INSN_ADDI, "addi", "add", 16,
00609     { 0, { { { (1<<MACH_BASE), 0 } } } }
00610   },
00611 /* add2 $m4,$Ri */
00612   {
00613     FR30_INSN_ADD2, "add2", "add2", 16,
00614     { 0, { { { (1<<MACH_BASE), 0 } } } }
00615   },
00616 /* addc $Rj,$Ri */
00617   {
00618     FR30_INSN_ADDC, "addc", "addc", 16,
00619     { 0, { { { (1<<MACH_BASE), 0 } } } }
00620   },
00621 /* addn $Rj,$Ri */
00622   {
00623     FR30_INSN_ADDN, "addn", "addn", 16,
00624     { 0, { { { (1<<MACH_BASE), 0 } } } }
00625   },
00626 /* addn $u4,$Ri */
00627   {
00628     FR30_INSN_ADDNI, "addni", "addn", 16,
00629     { 0, { { { (1<<MACH_BASE), 0 } } } }
00630   },
00631 /* addn2 $m4,$Ri */
00632   {
00633     FR30_INSN_ADDN2, "addn2", "addn2", 16,
00634     { 0, { { { (1<<MACH_BASE), 0 } } } }
00635   },
00636 /* sub $Rj,$Ri */
00637   {
00638     FR30_INSN_SUB, "sub", "sub", 16,
00639     { 0, { { { (1<<MACH_BASE), 0 } } } }
00640   },
00641 /* subc $Rj,$Ri */
00642   {
00643     FR30_INSN_SUBC, "subc", "subc", 16,
00644     { 0, { { { (1<<MACH_BASE), 0 } } } }
00645   },
00646 /* subn $Rj,$Ri */
00647   {
00648     FR30_INSN_SUBN, "subn", "subn", 16,
00649     { 0, { { { (1<<MACH_BASE), 0 } } } }
00650   },
00651 /* cmp $Rj,$Ri */
00652   {
00653     FR30_INSN_CMP, "cmp", "cmp", 16,
00654     { 0, { { { (1<<MACH_BASE), 0 } } } }
00655   },
00656 /* cmp $u4,$Ri */
00657   {
00658     FR30_INSN_CMPI, "cmpi", "cmp", 16,
00659     { 0, { { { (1<<MACH_BASE), 0 } } } }
00660   },
00661 /* cmp2 $m4,$Ri */
00662   {
00663     FR30_INSN_CMP2, "cmp2", "cmp2", 16,
00664     { 0, { { { (1<<MACH_BASE), 0 } } } }
00665   },
00666 /* and $Rj,$Ri */
00667   {
00668     FR30_INSN_AND, "and", "and", 16,
00669     { 0, { { { (1<<MACH_BASE), 0 } } } }
00670   },
00671 /* or $Rj,$Ri */
00672   {
00673     FR30_INSN_OR, "or", "or", 16,
00674     { 0, { { { (1<<MACH_BASE), 0 } } } }
00675   },
00676 /* eor $Rj,$Ri */
00677   {
00678     FR30_INSN_EOR, "eor", "eor", 16,
00679     { 0, { { { (1<<MACH_BASE), 0 } } } }
00680   },
00681 /* and $Rj,@$Ri */
00682   {
00683     FR30_INSN_ANDM, "andm", "and", 16,
00684     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00685   },
00686 /* andh $Rj,@$Ri */
00687   {
00688     FR30_INSN_ANDH, "andh", "andh", 16,
00689     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00690   },
00691 /* andb $Rj,@$Ri */
00692   {
00693     FR30_INSN_ANDB, "andb", "andb", 16,
00694     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00695   },
00696 /* or $Rj,@$Ri */
00697   {
00698     FR30_INSN_ORM, "orm", "or", 16,
00699     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00700   },
00701 /* orh $Rj,@$Ri */
00702   {
00703     FR30_INSN_ORH, "orh", "orh", 16,
00704     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00705   },
00706 /* orb $Rj,@$Ri */
00707   {
00708     FR30_INSN_ORB, "orb", "orb", 16,
00709     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00710   },
00711 /* eor $Rj,@$Ri */
00712   {
00713     FR30_INSN_EORM, "eorm", "eor", 16,
00714     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00715   },
00716 /* eorh $Rj,@$Ri */
00717   {
00718     FR30_INSN_EORH, "eorh", "eorh", 16,
00719     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00720   },
00721 /* eorb $Rj,@$Ri */
00722   {
00723     FR30_INSN_EORB, "eorb", "eorb", 16,
00724     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00725   },
00726 /* bandl $u4,@$Ri */
00727   {
00728     FR30_INSN_BANDL, "bandl", "bandl", 16,
00729     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00730   },
00731 /* borl $u4,@$Ri */
00732   {
00733     FR30_INSN_BORL, "borl", "borl", 16,
00734     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00735   },
00736 /* beorl $u4,@$Ri */
00737   {
00738     FR30_INSN_BEORL, "beorl", "beorl", 16,
00739     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00740   },
00741 /* bandh $u4,@$Ri */
00742   {
00743     FR30_INSN_BANDH, "bandh", "bandh", 16,
00744     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00745   },
00746 /* borh $u4,@$Ri */
00747   {
00748     FR30_INSN_BORH, "borh", "borh", 16,
00749     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00750   },
00751 /* beorh $u4,@$Ri */
00752   {
00753     FR30_INSN_BEORH, "beorh", "beorh", 16,
00754     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00755   },
00756 /* btstl $u4,@$Ri */
00757   {
00758     FR30_INSN_BTSTL, "btstl", "btstl", 16,
00759     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00760   },
00761 /* btsth $u4,@$Ri */
00762   {
00763     FR30_INSN_BTSTH, "btsth", "btsth", 16,
00764     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00765   },
00766 /* mul $Rj,$Ri */
00767   {
00768     FR30_INSN_MUL, "mul", "mul", 16,
00769     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00770   },
00771 /* mulu $Rj,$Ri */
00772   {
00773     FR30_INSN_MULU, "mulu", "mulu", 16,
00774     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00775   },
00776 /* mulh $Rj,$Ri */
00777   {
00778     FR30_INSN_MULH, "mulh", "mulh", 16,
00779     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00780   },
00781 /* muluh $Rj,$Ri */
00782   {
00783     FR30_INSN_MULUH, "muluh", "muluh", 16,
00784     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00785   },
00786 /* div0s $Ri */
00787   {
00788     FR30_INSN_DIV0S, "div0s", "div0s", 16,
00789     { 0, { { { (1<<MACH_BASE), 0 } } } }
00790   },
00791 /* div0u $Ri */
00792   {
00793     FR30_INSN_DIV0U, "div0u", "div0u", 16,
00794     { 0, { { { (1<<MACH_BASE), 0 } } } }
00795   },
00796 /* div1 $Ri */
00797   {
00798     FR30_INSN_DIV1, "div1", "div1", 16,
00799     { 0, { { { (1<<MACH_BASE), 0 } } } }
00800   },
00801 /* div2 $Ri */
00802   {
00803     FR30_INSN_DIV2, "div2", "div2", 16,
00804     { 0, { { { (1<<MACH_BASE), 0 } } } }
00805   },
00806 /* div3 */
00807   {
00808     FR30_INSN_DIV3, "div3", "div3", 16,
00809     { 0, { { { (1<<MACH_BASE), 0 } } } }
00810   },
00811 /* div4s */
00812   {
00813     FR30_INSN_DIV4S, "div4s", "div4s", 16,
00814     { 0, { { { (1<<MACH_BASE), 0 } } } }
00815   },
00816 /* lsl $Rj,$Ri */
00817   {
00818     FR30_INSN_LSL, "lsl", "lsl", 16,
00819     { 0, { { { (1<<MACH_BASE), 0 } } } }
00820   },
00821 /* lsl $u4,$Ri */
00822   {
00823     FR30_INSN_LSLI, "lsli", "lsl", 16,
00824     { 0, { { { (1<<MACH_BASE), 0 } } } }
00825   },
00826 /* lsl2 $u4,$Ri */
00827   {
00828     FR30_INSN_LSL2, "lsl2", "lsl2", 16,
00829     { 0, { { { (1<<MACH_BASE), 0 } } } }
00830   },
00831 /* lsr $Rj,$Ri */
00832   {
00833     FR30_INSN_LSR, "lsr", "lsr", 16,
00834     { 0, { { { (1<<MACH_BASE), 0 } } } }
00835   },
00836 /* lsr $u4,$Ri */
00837   {
00838     FR30_INSN_LSRI, "lsri", "lsr", 16,
00839     { 0, { { { (1<<MACH_BASE), 0 } } } }
00840   },
00841 /* lsr2 $u4,$Ri */
00842   {
00843     FR30_INSN_LSR2, "lsr2", "lsr2", 16,
00844     { 0, { { { (1<<MACH_BASE), 0 } } } }
00845   },
00846 /* asr $Rj,$Ri */
00847   {
00848     FR30_INSN_ASR, "asr", "asr", 16,
00849     { 0, { { { (1<<MACH_BASE), 0 } } } }
00850   },
00851 /* asr $u4,$Ri */
00852   {
00853     FR30_INSN_ASRI, "asri", "asr", 16,
00854     { 0, { { { (1<<MACH_BASE), 0 } } } }
00855   },
00856 /* asr2 $u4,$Ri */
00857   {
00858     FR30_INSN_ASR2, "asr2", "asr2", 16,
00859     { 0, { { { (1<<MACH_BASE), 0 } } } }
00860   },
00861 /* ldi:8 $i8,$Ri */
00862   {
00863     FR30_INSN_LDI8, "ldi8", "ldi:8", 16,
00864     { 0, { { { (1<<MACH_BASE), 0 } } } }
00865   },
00866 /* ldi:20 $i20,$Ri */
00867   {
00868     FR30_INSN_LDI20, "ldi20", "ldi:20", 32,
00869     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00870   },
00871 /* ldi:32 $i32,$Ri */
00872   {
00873     FR30_INSN_LDI32, "ldi32", "ldi:32", 48,
00874     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00875   },
00876 /* ld @$Rj,$Ri */
00877   {
00878     FR30_INSN_LD, "ld", "ld", 16,
00879     { 0, { { { (1<<MACH_BASE), 0 } } } }
00880   },
00881 /* lduh @$Rj,$Ri */
00882   {
00883     FR30_INSN_LDUH, "lduh", "lduh", 16,
00884     { 0, { { { (1<<MACH_BASE), 0 } } } }
00885   },
00886 /* ldub @$Rj,$Ri */
00887   {
00888     FR30_INSN_LDUB, "ldub", "ldub", 16,
00889     { 0, { { { (1<<MACH_BASE), 0 } } } }
00890   },
00891 /* ld @($R13,$Rj),$Ri */
00892   {
00893     FR30_INSN_LDR13, "ldr13", "ld", 16,
00894     { 0, { { { (1<<MACH_BASE), 0 } } } }
00895   },
00896 /* lduh @($R13,$Rj),$Ri */
00897   {
00898     FR30_INSN_LDR13UH, "ldr13uh", "lduh", 16,
00899     { 0, { { { (1<<MACH_BASE), 0 } } } }
00900   },
00901 /* ldub @($R13,$Rj),$Ri */
00902   {
00903     FR30_INSN_LDR13UB, "ldr13ub", "ldub", 16,
00904     { 0, { { { (1<<MACH_BASE), 0 } } } }
00905   },
00906 /* ld @($R14,$disp10),$Ri */
00907   {
00908     FR30_INSN_LDR14, "ldr14", "ld", 16,
00909     { 0, { { { (1<<MACH_BASE), 0 } } } }
00910   },
00911 /* lduh @($R14,$disp9),$Ri */
00912   {
00913     FR30_INSN_LDR14UH, "ldr14uh", "lduh", 16,
00914     { 0, { { { (1<<MACH_BASE), 0 } } } }
00915   },
00916 /* ldub @($R14,$disp8),$Ri */
00917   {
00918     FR30_INSN_LDR14UB, "ldr14ub", "ldub", 16,
00919     { 0, { { { (1<<MACH_BASE), 0 } } } }
00920   },
00921 /* ld @($R15,$udisp6),$Ri */
00922   {
00923     FR30_INSN_LDR15, "ldr15", "ld", 16,
00924     { 0, { { { (1<<MACH_BASE), 0 } } } }
00925   },
00926 /* ld @$R15+,$Ri */
00927   {
00928     FR30_INSN_LDR15GR, "ldr15gr", "ld", 16,
00929     { 0, { { { (1<<MACH_BASE), 0 } } } }
00930   },
00931 /* ld @$R15+,$Rs2 */
00932   {
00933     FR30_INSN_LDR15DR, "ldr15dr", "ld", 16,
00934     { 0, { { { (1<<MACH_BASE), 0 } } } }
00935   },
00936 /* ld @$R15+,$ps */
00937   {
00938     FR30_INSN_LDR15PS, "ldr15ps", "ld", 16,
00939     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
00940   },
00941 /* st $Ri,@$Rj */
00942   {
00943     FR30_INSN_ST, "st", "st", 16,
00944     { 0, { { { (1<<MACH_BASE), 0 } } } }
00945   },
00946 /* sth $Ri,@$Rj */
00947   {
00948     FR30_INSN_STH, "sth", "sth", 16,
00949     { 0, { { { (1<<MACH_BASE), 0 } } } }
00950   },
00951 /* stb $Ri,@$Rj */
00952   {
00953     FR30_INSN_STB, "stb", "stb", 16,
00954     { 0, { { { (1<<MACH_BASE), 0 } } } }
00955   },
00956 /* st $Ri,@($R13,$Rj) */
00957   {
00958     FR30_INSN_STR13, "str13", "st", 16,
00959     { 0, { { { (1<<MACH_BASE), 0 } } } }
00960   },
00961 /* sth $Ri,@($R13,$Rj) */
00962   {
00963     FR30_INSN_STR13H, "str13h", "sth", 16,
00964     { 0, { { { (1<<MACH_BASE), 0 } } } }
00965   },
00966 /* stb $Ri,@($R13,$Rj) */
00967   {
00968     FR30_INSN_STR13B, "str13b", "stb", 16,
00969     { 0, { { { (1<<MACH_BASE), 0 } } } }
00970   },
00971 /* st $Ri,@($R14,$disp10) */
00972   {
00973     FR30_INSN_STR14, "str14", "st", 16,
00974     { 0, { { { (1<<MACH_BASE), 0 } } } }
00975   },
00976 /* sth $Ri,@($R14,$disp9) */
00977   {
00978     FR30_INSN_STR14H, "str14h", "sth", 16,
00979     { 0, { { { (1<<MACH_BASE), 0 } } } }
00980   },
00981 /* stb $Ri,@($R14,$disp8) */
00982   {
00983     FR30_INSN_STR14B, "str14b", "stb", 16,
00984     { 0, { { { (1<<MACH_BASE), 0 } } } }
00985   },
00986 /* st $Ri,@($R15,$udisp6) */
00987   {
00988     FR30_INSN_STR15, "str15", "st", 16,
00989     { 0, { { { (1<<MACH_BASE), 0 } } } }
00990   },
00991 /* st $Ri,@-$R15 */
00992   {
00993     FR30_INSN_STR15GR, "str15gr", "st", 16,
00994     { 0, { { { (1<<MACH_BASE), 0 } } } }
00995   },
00996 /* st $Rs2,@-$R15 */
00997   {
00998     FR30_INSN_STR15DR, "str15dr", "st", 16,
00999     { 0, { { { (1<<MACH_BASE), 0 } } } }
01000   },
01001 /* st $ps,@-$R15 */
01002   {
01003     FR30_INSN_STR15PS, "str15ps", "st", 16,
01004     { 0, { { { (1<<MACH_BASE), 0 } } } }
01005   },
01006 /* mov $Rj,$Ri */
01007   {
01008     FR30_INSN_MOV, "mov", "mov", 16,
01009     { 0, { { { (1<<MACH_BASE), 0 } } } }
01010   },
01011 /* mov $Rs1,$Ri */
01012   {
01013     FR30_INSN_MOVDR, "movdr", "mov", 16,
01014     { 0, { { { (1<<MACH_BASE), 0 } } } }
01015   },
01016 /* mov $ps,$Ri */
01017   {
01018     FR30_INSN_MOVPS, "movps", "mov", 16,
01019     { 0, { { { (1<<MACH_BASE), 0 } } } }
01020   },
01021 /* mov $Ri,$Rs1 */
01022   {
01023     FR30_INSN_MOV2DR, "mov2dr", "mov", 16,
01024     { 0, { { { (1<<MACH_BASE), 0 } } } }
01025   },
01026 /* mov $Ri,$ps */
01027   {
01028     FR30_INSN_MOV2PS, "mov2ps", "mov", 16,
01029     { 0, { { { (1<<MACH_BASE), 0 } } } }
01030   },
01031 /* jmp @$Ri */
01032   {
01033     FR30_INSN_JMP, "jmp", "jmp", 16,
01034     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01035   },
01036 /* jmp:d @$Ri */
01037   {
01038     FR30_INSN_JMPD, "jmpd", "jmp:d", 16,
01039     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01040   },
01041 /* call @$Ri */
01042   {
01043     FR30_INSN_CALLR, "callr", "call", 16,
01044     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01045   },
01046 /* call:d @$Ri */
01047   {
01048     FR30_INSN_CALLRD, "callrd", "call:d", 16,
01049     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01050   },
01051 /* call $label12 */
01052   {
01053     FR30_INSN_CALL, "call", "call", 16,
01054     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01055   },
01056 /* call:d $label12 */
01057   {
01058     FR30_INSN_CALLD, "calld", "call:d", 16,
01059     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01060   },
01061 /* ret */
01062   {
01063     FR30_INSN_RET, "ret", "ret", 16,
01064     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01065   },
01066 /* ret:d */
01067   {
01068     FR30_INSN_RET_D, "ret:d", "ret:d", 16,
01069     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01070   },
01071 /* int $u8 */
01072   {
01073     FR30_INSN_INT, "int", "int", 16,
01074     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01075   },
01076 /* inte */
01077   {
01078     FR30_INSN_INTE, "inte", "inte", 16,
01079     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01080   },
01081 /* reti */
01082   {
01083     FR30_INSN_RETI, "reti", "reti", 16,
01084     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01085   },
01086 /* bra:d $label9 */
01087   {
01088     FR30_INSN_BRAD, "brad", "bra:d", 16,
01089     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01090   },
01091 /* bra $label9 */
01092   {
01093     FR30_INSN_BRA, "bra", "bra", 16,
01094     { 0|A(NOT_IN_DELAY_SLOT)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01095   },
01096 /* bno:d $label9 */
01097   {
01098     FR30_INSN_BNOD, "bnod", "bno:d", 16,
01099     { 0|A(NOT_IN_DELAY_SLOT)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01100   },
01101 /* bno $label9 */
01102   {
01103     FR30_INSN_BNO, "bno", "bno", 16,
01104     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01105   },
01106 /* beq:d $label9 */
01107   {
01108     FR30_INSN_BEQD, "beqd", "beq:d", 16,
01109     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01110   },
01111 /* beq $label9 */
01112   {
01113     FR30_INSN_BEQ, "beq", "beq", 16,
01114     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01115   },
01116 /* bne:d $label9 */
01117   {
01118     FR30_INSN_BNED, "bned", "bne:d", 16,
01119     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01120   },
01121 /* bne $label9 */
01122   {
01123     FR30_INSN_BNE, "bne", "bne", 16,
01124     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01125   },
01126 /* bc:d $label9 */
01127   {
01128     FR30_INSN_BCD, "bcd", "bc:d", 16,
01129     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01130   },
01131 /* bc $label9 */
01132   {
01133     FR30_INSN_BC, "bc", "bc", 16,
01134     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01135   },
01136 /* bnc:d $label9 */
01137   {
01138     FR30_INSN_BNCD, "bncd", "bnc:d", 16,
01139     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01140   },
01141 /* bnc $label9 */
01142   {
01143     FR30_INSN_BNC, "bnc", "bnc", 16,
01144     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01145   },
01146 /* bn:d $label9 */
01147   {
01148     FR30_INSN_BND, "bnd", "bn:d", 16,
01149     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01150   },
01151 /* bn $label9 */
01152   {
01153     FR30_INSN_BN, "bn", "bn", 16,
01154     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01155   },
01156 /* bp:d $label9 */
01157   {
01158     FR30_INSN_BPD, "bpd", "bp:d", 16,
01159     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01160   },
01161 /* bp $label9 */
01162   {
01163     FR30_INSN_BP, "bp", "bp", 16,
01164     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01165   },
01166 /* bv:d $label9 */
01167   {
01168     FR30_INSN_BVD, "bvd", "bv:d", 16,
01169     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01170   },
01171 /* bv $label9 */
01172   {
01173     FR30_INSN_BV, "bv", "bv", 16,
01174     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01175   },
01176 /* bnv:d $label9 */
01177   {
01178     FR30_INSN_BNVD, "bnvd", "bnv:d", 16,
01179     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01180   },
01181 /* bnv $label9 */
01182   {
01183     FR30_INSN_BNV, "bnv", "bnv", 16,
01184     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01185   },
01186 /* blt:d $label9 */
01187   {
01188     FR30_INSN_BLTD, "bltd", "blt:d", 16,
01189     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01190   },
01191 /* blt $label9 */
01192   {
01193     FR30_INSN_BLT, "blt", "blt", 16,
01194     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01195   },
01196 /* bge:d $label9 */
01197   {
01198     FR30_INSN_BGED, "bged", "bge:d", 16,
01199     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01200   },
01201 /* bge $label9 */
01202   {
01203     FR30_INSN_BGE, "bge", "bge", 16,
01204     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01205   },
01206 /* ble:d $label9 */
01207   {
01208     FR30_INSN_BLED, "bled", "ble:d", 16,
01209     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01210   },
01211 /* ble $label9 */
01212   {
01213     FR30_INSN_BLE, "ble", "ble", 16,
01214     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01215   },
01216 /* bgt:d $label9 */
01217   {
01218     FR30_INSN_BGTD, "bgtd", "bgt:d", 16,
01219     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01220   },
01221 /* bgt $label9 */
01222   {
01223     FR30_INSN_BGT, "bgt", "bgt", 16,
01224     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01225   },
01226 /* bls:d $label9 */
01227   {
01228     FR30_INSN_BLSD, "blsd", "bls:d", 16,
01229     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01230   },
01231 /* bls $label9 */
01232   {
01233     FR30_INSN_BLS, "bls", "bls", 16,
01234     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01235   },
01236 /* bhi:d $label9 */
01237   {
01238     FR30_INSN_BHID, "bhid", "bhi:d", 16,
01239     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01240   },
01241 /* bhi $label9 */
01242   {
01243     FR30_INSN_BHI, "bhi", "bhi", 16,
01244     { 0|A(NOT_IN_DELAY_SLOT)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } } } }
01245   },
01246 /* dmov $R13,@$dir10 */
01247   {
01248     FR30_INSN_DMOVR13, "dmovr13", "dmov", 16,
01249     { 0, { { { (1<<MACH_BASE), 0 } } } }
01250   },
01251 /* dmovh $R13,@$dir9 */
01252   {
01253     FR30_INSN_DMOVR13H, "dmovr13h", "dmovh", 16,
01254     { 0, { { { (1<<MACH_BASE), 0 } } } }
01255   },
01256 /* dmovb $R13,@$dir8 */
01257   {
01258     FR30_INSN_DMOVR13B, "dmovr13b", "dmovb", 16,
01259     { 0, { { { (1<<MACH_BASE), 0 } } } }
01260   },
01261 /* dmov @$R13+,@$dir10 */
01262   {
01263     FR30_INSN_DMOVR13PI, "dmovr13pi", "dmov", 16,
01264     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01265   },
01266 /* dmovh @$R13+,@$dir9 */
01267   {
01268     FR30_INSN_DMOVR13PIH, "dmovr13pih", "dmovh", 16,
01269     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01270   },
01271 /* dmovb @$R13+,@$dir8 */
01272   {
01273     FR30_INSN_DMOVR13PIB, "dmovr13pib", "dmovb", 16,
01274     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01275   },
01276 /* dmov @$R15+,@$dir10 */
01277   {
01278     FR30_INSN_DMOVR15PI, "dmovr15pi", "dmov", 16,
01279     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01280   },
01281 /* dmov @$dir10,$R13 */
01282   {
01283     FR30_INSN_DMOV2R13, "dmov2r13", "dmov", 16,
01284     { 0, { { { (1<<MACH_BASE), 0 } } } }
01285   },
01286 /* dmovh @$dir9,$R13 */
01287   {
01288     FR30_INSN_DMOV2R13H, "dmov2r13h", "dmovh", 16,
01289     { 0, { { { (1<<MACH_BASE), 0 } } } }
01290   },
01291 /* dmovb @$dir8,$R13 */
01292   {
01293     FR30_INSN_DMOV2R13B, "dmov2r13b", "dmovb", 16,
01294     { 0, { { { (1<<MACH_BASE), 0 } } } }
01295   },
01296 /* dmov @$dir10,@$R13+ */
01297   {
01298     FR30_INSN_DMOV2R13PI, "dmov2r13pi", "dmov", 16,
01299     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01300   },
01301 /* dmovh @$dir9,@$R13+ */
01302   {
01303     FR30_INSN_DMOV2R13PIH, "dmov2r13pih", "dmovh", 16,
01304     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01305   },
01306 /* dmovb @$dir8,@$R13+ */
01307   {
01308     FR30_INSN_DMOV2R13PIB, "dmov2r13pib", "dmovb", 16,
01309     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01310   },
01311 /* dmov @$dir10,@-$R15 */
01312   {
01313     FR30_INSN_DMOV2R15PD, "dmov2r15pd", "dmov", 16,
01314     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01315   },
01316 /* ldres @$Ri+,$u4 */
01317   {
01318     FR30_INSN_LDRES, "ldres", "ldres", 16,
01319     { 0, { { { (1<<MACH_BASE), 0 } } } }
01320   },
01321 /* stres $u4,@$Ri+ */
01322   {
01323     FR30_INSN_STRES, "stres", "stres", 16,
01324     { 0, { { { (1<<MACH_BASE), 0 } } } }
01325   },
01326 /* copop $u4c,$ccc,$CRj,$CRi */
01327   {
01328     FR30_INSN_COPOP, "copop", "copop", 32,
01329     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01330   },
01331 /* copld $u4c,$ccc,$Rjc,$CRi */
01332   {
01333     FR30_INSN_COPLD, "copld", "copld", 32,
01334     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01335   },
01336 /* copst $u4c,$ccc,$CRj,$Ric */
01337   {
01338     FR30_INSN_COPST, "copst", "copst", 32,
01339     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01340   },
01341 /* copsv $u4c,$ccc,$CRj,$Ric */
01342   {
01343     FR30_INSN_COPSV, "copsv", "copsv", 32,
01344     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01345   },
01346 /* nop */
01347   {
01348     FR30_INSN_NOP, "nop", "nop", 16,
01349     { 0, { { { (1<<MACH_BASE), 0 } } } }
01350   },
01351 /* andccr $u8 */
01352   {
01353     FR30_INSN_ANDCCR, "andccr", "andccr", 16,
01354     { 0, { { { (1<<MACH_BASE), 0 } } } }
01355   },
01356 /* orccr $u8 */
01357   {
01358     FR30_INSN_ORCCR, "orccr", "orccr", 16,
01359     { 0, { { { (1<<MACH_BASE), 0 } } } }
01360   },
01361 /* stilm $u8 */
01362   {
01363     FR30_INSN_STILM, "stilm", "stilm", 16,
01364     { 0, { { { (1<<MACH_BASE), 0 } } } }
01365   },
01366 /* addsp $s10 */
01367   {
01368     FR30_INSN_ADDSP, "addsp", "addsp", 16,
01369     { 0, { { { (1<<MACH_BASE), 0 } } } }
01370   },
01371 /* extsb $Ri */
01372   {
01373     FR30_INSN_EXTSB, "extsb", "extsb", 16,
01374     { 0, { { { (1<<MACH_BASE), 0 } } } }
01375   },
01376 /* extub $Ri */
01377   {
01378     FR30_INSN_EXTUB, "extub", "extub", 16,
01379     { 0, { { { (1<<MACH_BASE), 0 } } } }
01380   },
01381 /* extsh $Ri */
01382   {
01383     FR30_INSN_EXTSH, "extsh", "extsh", 16,
01384     { 0, { { { (1<<MACH_BASE), 0 } } } }
01385   },
01386 /* extuh $Ri */
01387   {
01388     FR30_INSN_EXTUH, "extuh", "extuh", 16,
01389     { 0, { { { (1<<MACH_BASE), 0 } } } }
01390   },
01391 /* ldm0 ($reglist_low_ld) */
01392   {
01393     FR30_INSN_LDM0, "ldm0", "ldm0", 16,
01394     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01395   },
01396 /* ldm1 ($reglist_hi_ld) */
01397   {
01398     FR30_INSN_LDM1, "ldm1", "ldm1", 16,
01399     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01400   },
01401 /* stm0 ($reglist_low_st) */
01402   {
01403     FR30_INSN_STM0, "stm0", "stm0", 16,
01404     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01405   },
01406 /* stm1 ($reglist_hi_st) */
01407   {
01408     FR30_INSN_STM1, "stm1", "stm1", 16,
01409     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01410   },
01411 /* enter $u10 */
01412   {
01413     FR30_INSN_ENTER, "enter", "enter", 16,
01414     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01415   },
01416 /* leave */
01417   {
01418     FR30_INSN_LEAVE, "leave", "leave", 16,
01419     { 0, { { { (1<<MACH_BASE), 0 } } } }
01420   },
01421 /* xchb @$Rj,$Ri */
01422   {
01423     FR30_INSN_XCHB, "xchb", "xchb", 16,
01424     { 0|A(NOT_IN_DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
01425   },
01426 };
01427 
01428 #undef OP
01429 #undef A
01430 
01431 /* Initialize anything needed to be done once, before any cpu_open call.  */
01432 
01433 static void
01434 init_tables (void)
01435 {
01436 }
01437 
01438 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
01439 static void build_hw_table      (CGEN_CPU_TABLE *);
01440 static void build_ifield_table  (CGEN_CPU_TABLE *);
01441 static void build_operand_table (CGEN_CPU_TABLE *);
01442 static void build_insn_table    (CGEN_CPU_TABLE *);
01443 static void fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *);
01444 
01445 /* Subroutine of fr30_cgen_cpu_open to look up a mach via its bfd name.  */
01446 
01447 static const CGEN_MACH *
01448 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
01449 {
01450   while (table->name)
01451     {
01452       if (strcmp (name, table->bfd_name) == 0)
01453        return table;
01454       ++table;
01455     }
01456   abort ();
01457 }
01458 
01459 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
01460 
01461 static void
01462 build_hw_table (CGEN_CPU_TABLE *cd)
01463 {
01464   int i;
01465   int machs = cd->machs;
01466   const CGEN_HW_ENTRY *init = & fr30_cgen_hw_table[0];
01467   /* MAX_HW is only an upper bound on the number of selected entries.
01468      However each entry is indexed by it's enum so there can be holes in
01469      the table.  */
01470   const CGEN_HW_ENTRY **selected =
01471     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
01472 
01473   cd->hw_table.init_entries = init;
01474   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
01475   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
01476   /* ??? For now we just use machs to determine which ones we want.  */
01477   for (i = 0; init[i].name != NULL; ++i)
01478     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
01479        & machs)
01480       selected[init[i].type] = &init[i];
01481   cd->hw_table.entries = selected;
01482   cd->hw_table.num_entries = MAX_HW;
01483 }
01484 
01485 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
01486 
01487 static void
01488 build_ifield_table (CGEN_CPU_TABLE *cd)
01489 {
01490   cd->ifld_table = & fr30_cgen_ifld_table[0];
01491 }
01492 
01493 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.  */
01494 
01495 static void
01496 build_operand_table (CGEN_CPU_TABLE *cd)
01497 {
01498   int i;
01499   int machs = cd->machs;
01500   const CGEN_OPERAND *init = & fr30_cgen_operand_table[0];
01501   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
01502      However each entry is indexed by it's enum so there can be holes in
01503      the table.  */
01504   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
01505 
01506   cd->operand_table.init_entries = init;
01507   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
01508   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
01509   /* ??? For now we just use mach to determine which ones we want.  */
01510   for (i = 0; init[i].name != NULL; ++i)
01511     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
01512        & machs)
01513       selected[init[i].type] = &init[i];
01514   cd->operand_table.entries = selected;
01515   cd->operand_table.num_entries = MAX_OPERANDS;
01516 }
01517 
01518 /* Subroutine of fr30_cgen_cpu_open to build the hardware table.
01519    ??? This could leave out insns not supported by the specified mach/isa,
01520    but that would cause errors like "foo only supported by bar" to become
01521    "unknown insn", so for now we include all insns and require the app to
01522    do the checking later.
01523    ??? On the other hand, parsing of such insns may require their hardware or
01524    operand elements to be in the table [which they mightn't be].  */
01525 
01526 static void
01527 build_insn_table (CGEN_CPU_TABLE *cd)
01528 {
01529   int i;
01530   const CGEN_IBASE *ib = & fr30_cgen_insn_table[0];
01531   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
01532 
01533   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
01534   for (i = 0; i < MAX_INSNS; ++i)
01535     insns[i].base = &ib[i];
01536   cd->insn_table.init_entries = insns;
01537   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
01538   cd->insn_table.num_init_entries = MAX_INSNS;
01539 }
01540 
01541 /* Subroutine of fr30_cgen_cpu_open to rebuild the tables.  */
01542 
01543 static void
01544 fr30_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
01545 {
01546   int i;
01547   CGEN_BITSET *isas = cd->isas;
01548   unsigned int machs = cd->machs;
01549 
01550   cd->int_insn_p = CGEN_INT_INSN_P;
01551 
01552   /* Data derived from the isa spec.  */
01553 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
01554   cd->default_insn_bitsize = UNSET;
01555   cd->base_insn_bitsize = UNSET;
01556   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
01557   cd->max_insn_bitsize = 0;
01558   for (i = 0; i < MAX_ISAS; ++i)
01559     if (cgen_bitset_contains (isas, i))
01560       {
01561        const CGEN_ISA *isa = & fr30_cgen_isa_table[i];
01562 
01563        /* Default insn sizes of all selected isas must be
01564           equal or we set the result to 0, meaning "unknown".  */
01565        if (cd->default_insn_bitsize == UNSET)
01566          cd->default_insn_bitsize = isa->default_insn_bitsize;
01567        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
01568          ; /* This is ok.  */
01569        else
01570          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
01571 
01572        /* Base insn sizes of all selected isas must be equal
01573           or we set the result to 0, meaning "unknown".  */
01574        if (cd->base_insn_bitsize == UNSET)
01575          cd->base_insn_bitsize = isa->base_insn_bitsize;
01576        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
01577          ; /* This is ok.  */
01578        else
01579          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
01580 
01581        /* Set min,max insn sizes.  */
01582        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
01583          cd->min_insn_bitsize = isa->min_insn_bitsize;
01584        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
01585          cd->max_insn_bitsize = isa->max_insn_bitsize;
01586       }
01587 
01588   /* Data derived from the mach spec.  */
01589   for (i = 0; i < MAX_MACHS; ++i)
01590     if (((1 << i) & machs) != 0)
01591       {
01592        const CGEN_MACH *mach = & fr30_cgen_mach_table[i];
01593 
01594        if (mach->insn_chunk_bitsize != 0)
01595        {
01596          if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
01597            {
01598              fprintf (stderr, "fr30_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
01599                      cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
01600              abort ();
01601            }
01602 
01603          cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
01604        }
01605       }
01606 
01607   /* Determine which hw elements are used by MACH.  */
01608   build_hw_table (cd);
01609 
01610   /* Build the ifield table.  */
01611   build_ifield_table (cd);
01612 
01613   /* Determine which operands are used by MACH/ISA.  */
01614   build_operand_table (cd);
01615 
01616   /* Build the instruction table.  */
01617   build_insn_table (cd);
01618 }
01619 
01620 /* Initialize a cpu table and return a descriptor.
01621    It's much like opening a file, and must be the first function called.
01622    The arguments are a set of (type/value) pairs, terminated with
01623    CGEN_CPU_OPEN_END.
01624 
01625    Currently supported values:
01626    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
01627    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
01628    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
01629    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
01630    CGEN_CPU_OPEN_END:     terminates arguments
01631 
01632    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
01633    precluded.
01634 
01635    ??? We only support ISO C stdargs here, not K&R.
01636    Laziness, plus experiment to see if anything requires K&R - eventually
01637    K&R will no longer be supported - e.g. GDB is currently trying this.  */
01638 
01639 CGEN_CPU_DESC
01640 fr30_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
01641 {
01642   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
01643   static int init_p;
01644   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
01645   unsigned int machs = 0; /* 0 = "unspecified" */
01646   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
01647   va_list ap;
01648 
01649   if (! init_p)
01650     {
01651       init_tables ();
01652       init_p = 1;
01653     }
01654 
01655   memset (cd, 0, sizeof (*cd));
01656 
01657   va_start (ap, arg_type);
01658   while (arg_type != CGEN_CPU_OPEN_END)
01659     {
01660       switch (arg_type)
01661        {
01662        case CGEN_CPU_OPEN_ISAS :
01663          isas = va_arg (ap, CGEN_BITSET *);
01664          break;
01665        case CGEN_CPU_OPEN_MACHS :
01666          machs = va_arg (ap, unsigned int);
01667          break;
01668        case CGEN_CPU_OPEN_BFDMACH :
01669          {
01670            const char *name = va_arg (ap, const char *);
01671            const CGEN_MACH *mach =
01672              lookup_mach_via_bfd_name (fr30_cgen_mach_table, name);
01673 
01674            machs |= 1 << mach->num;
01675            break;
01676          }
01677        case CGEN_CPU_OPEN_ENDIAN :
01678          endian = va_arg (ap, enum cgen_endian);
01679          break;
01680        default :
01681          fprintf (stderr, "fr30_cgen_cpu_open: unsupported argument `%d'\n",
01682                  arg_type);
01683          abort (); /* ??? return NULL? */
01684        }
01685       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
01686     }
01687   va_end (ap);
01688 
01689   /* Mach unspecified means "all".  */
01690   if (machs == 0)
01691     machs = (1 << MAX_MACHS) - 1;
01692   /* Base mach is always selected.  */
01693   machs |= 1;
01694   if (endian == CGEN_ENDIAN_UNKNOWN)
01695     {
01696       /* ??? If target has only one, could have a default.  */
01697       fprintf (stderr, "fr30_cgen_cpu_open: no endianness specified\n");
01698       abort ();
01699     }
01700 
01701   cd->isas = cgen_bitset_copy (isas);
01702   cd->machs = machs;
01703   cd->endian = endian;
01704   /* FIXME: for the sparc case we can determine insn-endianness statically.
01705      The worry here is where both data and insn endian can be independently
01706      chosen, in which case this function will need another argument.
01707      Actually, will want to allow for more arguments in the future anyway.  */
01708   cd->insn_endian = endian;
01709 
01710   /* Table (re)builder.  */
01711   cd->rebuild_tables = fr30_cgen_rebuild_tables;
01712   fr30_cgen_rebuild_tables (cd);
01713 
01714   /* Default to not allowing signed overflow.  */
01715   cd->signed_overflow_ok_p = 0;
01716   
01717   return (CGEN_CPU_DESC) cd;
01718 }
01719 
01720 /* Cover fn to fr30_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
01721    MACH_NAME is the bfd name of the mach.  */
01722 
01723 CGEN_CPU_DESC
01724 fr30_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
01725 {
01726   return fr30_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
01727                             CGEN_CPU_OPEN_ENDIAN, endian,
01728                             CGEN_CPU_OPEN_END);
01729 }
01730 
01731 /* Close a cpu table.
01732    ??? This can live in a machine independent file, but there's currently
01733    no place to put this file (there's no libcgen).  libopcodes is the wrong
01734    place as some simulator ports use this but they don't use libopcodes.  */
01735 
01736 void
01737 fr30_cgen_cpu_close (CGEN_CPU_DESC cd)
01738 {
01739   unsigned int i;
01740   const CGEN_INSN *insns;
01741 
01742   if (cd->macro_insn_table.init_entries)
01743     {
01744       insns = cd->macro_insn_table.init_entries;
01745       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
01746        if (CGEN_INSN_RX ((insns)))
01747          regfree (CGEN_INSN_RX (insns));
01748     }
01749 
01750   if (cd->insn_table.init_entries)
01751     {
01752       insns = cd->insn_table.init_entries;
01753       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
01754        if (CGEN_INSN_RX (insns))
01755          regfree (CGEN_INSN_RX (insns));
01756     }  
01757 
01758   if (cd->macro_insn_table.init_entries)
01759     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
01760 
01761   if (cd->insn_table.init_entries)
01762     free ((CGEN_INSN *) cd->insn_table.init_entries);
01763 
01764   if (cd->hw_table.entries)
01765     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
01766 
01767   if (cd->operand_table.entries)
01768     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
01769 
01770   free (cd);
01771 }
01772