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cell-binutils  2.17cvs20070401
dlx-dis.c
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00001 /* Instruction printing code for the DLX Microprocessor
00002    Copyright 2002, 2005 Free Software Foundation, Inc.
00003    Contributed by Kuang Hwa Lin.  Written by Kuang Hwa Lin, 03/2002.
00004 
00005    This program is free software; you can redistribute it and/or modify
00006    it under the terms of the GNU General Public License as published by
00007    the Free Software Foundation; either version 2 of the License, or
00008    (at your option) any later version.
00009 
00010    This program is distributed in the hope that it will be useful,
00011    but WITHOUT ANY WARRANTY; without even the implied warranty of
00012    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00013    GNU General Public License for more details.
00014 
00015    You should have received a copy of the GNU General Public License
00016    along with this program; if not, write to the Free Software
00017    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
00018    MA 02110-1301, USA.  */
00019 
00020 #include "sysdep.h"
00021 #include "dis-asm.h"
00022 #include "opcode/dlx.h"
00023 
00024 #define R_ERROR     0x1
00025 #define R_TYPE      0x2
00026 #define ILD_TYPE    0x3
00027 #define IST_TYPE    0x4
00028 #define IAL_TYPE    0x5
00029 #define IBR_TYPE    0x6
00030 #define IJ_TYPE     0x7
00031 #define IJR_TYPE    0x8
00032 #define NIL         0x9
00033 
00034 #define OPC(x)      ((x >> 26) & 0x3F)
00035 #define FUNC(x)     (x & 0x7FF)
00036 
00037 unsigned char opc, rs1, rs2, rd;
00038 unsigned long imm26, imm16, func, current_insn_addr;
00039 
00040 /* Print one instruction from MEMADDR on INFO->STREAM.
00041    Return the size of the instruction (always 4 on dlx).  */
00042 
00043 static unsigned char
00044 dlx_get_opcode (unsigned long opcode)
00045 {
00046   return (unsigned char) ((opcode >> 26) & 0x3F);
00047 }
00048 
00049 static unsigned char
00050 dlx_get_rs1 (unsigned long opcode)
00051 {
00052   return (unsigned char) ((opcode >> 21) & 0x1F);
00053 }
00054 
00055 static unsigned char
00056 dlx_get_rs2 (unsigned long opcode)
00057 {
00058   return (unsigned char) ((opcode >> 16) & 0x1F);
00059 }
00060 
00061 static unsigned char
00062 dlx_get_rdR (unsigned long opcode)
00063 {
00064   return (unsigned char) ((opcode >> 11) & 0x1F);
00065 }
00066 
00067 static unsigned long
00068 dlx_get_func (unsigned long opcode)
00069 {
00070   return (unsigned char) (opcode & 0x7FF);
00071 }
00072 
00073 static unsigned long
00074 dlx_get_imm16 (unsigned long opcode)
00075 {
00076   return (unsigned long) (opcode & 0xFFFF);
00077 }
00078 
00079 static unsigned long
00080 dlx_get_imm26 (unsigned long opcode)
00081 {
00082   return (unsigned long) (opcode & 0x03FFFFFF);
00083 }
00084 
00085 /* Fill the opcode to the max length.  */
00086 
00087 static void
00088 operand_deliminator (struct disassemble_info *info, char *ptr)
00089 {
00090   int difft = 8 - (int) strlen (ptr);
00091 
00092   while (difft > 0)
00093     {
00094       (*info->fprintf_func) (info->stream, "%c", ' ');
00095       difft -= 1;
00096     }
00097 }
00098 
00099 /* Process the R-type opcode.  */
00100 
00101 static unsigned char
00102 dlx_r_type (struct disassemble_info *info)
00103 {
00104   unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
00105   int r_opc_num = (sizeof r_opc) / (sizeof (char));
00106   struct _r_opcode
00107   {
00108     unsigned long func;
00109     char *name;
00110   }
00111   dlx_r_opcode[] =
00112   {
00113     { NOPF,     "nop"    },  /* NOP                          */
00114     { ADDF,     "add"    },  /* Add                          */
00115     { ADDUF,    "addu"   },  /* Add Unsigned                 */
00116     { SUBF,     "sub"    },  /* SUB                          */
00117     { SUBUF,    "subu"   },  /* Sub Unsigned                 */
00118     { MULTF,    "mult"   },  /* MULTIPLY                     */
00119     { MULTUF,   "multu"  },  /* MULTIPLY Unsigned            */
00120     { DIVF,     "div"    },  /* DIVIDE                       */
00121     { DIVUF,    "divu"   },  /* DIVIDE Unsigned              */
00122     { ANDF,     "and"    },  /* AND                          */
00123     { ORF,      "or"     },  /* OR                           */
00124     { XORF,     "xor"    },  /* Exclusive OR                 */
00125     { SLLF,     "sll"    },  /* SHIFT LEFT LOGICAL           */
00126     { SRAF,     "sra"    },  /* SHIFT RIGHT ARITHMETIC       */
00127     { SRLF,     "srl"    },  /* SHIFT RIGHT LOGICAL          */
00128     { SEQF,     "seq"    },  /* Set if equal                 */
00129     { SNEF,     "sne"    },  /* Set if not equal             */
00130     { SLTF,     "slt"    },  /* Set if less                  */
00131     { SGTF,     "sgt"    },  /* Set if greater               */
00132     { SLEF,     "sle"    },  /* Set if less or equal         */
00133     { SGEF,     "sge"    },  /* Set if greater or equal      */
00134     { SEQUF,    "sequ"   },  /* Set if equal                 */
00135     { SNEUF,    "sneu"   },  /* Set if not equal             */
00136     { SLTUF,    "sltu"   },  /* Set if less                  */
00137     { SGTUF,    "sgtu"   },  /* Set if greater               */
00138     { SLEUF,    "sleu"   },  /* Set if less or equal         */
00139     { SGEUF,    "sgeu"   },  /* Set if greater or equal      */
00140     { MVTSF,    "mvts"   },  /* Move to special register     */
00141     { MVFSF,    "mvfs"   },  /* Move from special register   */
00142     { BSWAPF,   "bswap"  },  /* Byte swap ??                 */
00143     { LUTF,     "lut"    }   /* ????????? ??                 */
00144   };
00145   int dlx_r_opcode_num = (sizeof dlx_r_opcode) / (sizeof dlx_r_opcode[0]);
00146   int idx;
00147 
00148   for (idx = 0; idx < r_opc_num; idx++)
00149     {
00150       if (r_opc[idx] != opc)
00151        continue;
00152       else
00153        break;
00154     }
00155 
00156   if (idx == r_opc_num)
00157     return NIL;
00158 
00159   for (idx = 0 ; idx < dlx_r_opcode_num; idx++)
00160     if (dlx_r_opcode[idx].func == func)
00161       {
00162        (*info->fprintf_func) (info->stream, "%s", dlx_r_opcode[idx].name);
00163 
00164        if (func != NOPF)
00165          {
00166            /* This is not a nop.  */
00167            operand_deliminator (info, dlx_r_opcode[idx].name);
00168            (*info->fprintf_func) (info->stream, "r%d,", (int)rd);
00169            (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
00170            if (func != MVTSF && func != MVFSF)
00171              (*info->fprintf_func) (info->stream, ",r%d", (int)rs2);
00172          }
00173        return (unsigned char) R_TYPE;
00174       }
00175 
00176   return (unsigned char) R_ERROR;
00177 }
00178 
00179 /* Process the memory read opcode.  */
00180 
00181 static unsigned char
00182 dlx_load_type (struct disassemble_info* info)
00183 {
00184   struct _load_opcode
00185   {
00186     unsigned long opcode;
00187     char *name;
00188   }
00189   dlx_load_opcode[] =
00190   {
00191     { OPC(LHIOP),   "lhi" },  /* Load HI to register.           */
00192     { OPC(LBOP),     "lb" },  /* load byte sign extended.       */
00193     { OPC(LBUOP),   "lbu" },  /* load byte unsigned.            */
00194     { OPC(LSBUOP),"ldstbu"},  /* load store byte unsigned.      */
00195     { OPC(LHOP),     "lh" },  /* load halfword sign extended.   */
00196     { OPC(LHUOP),   "lhu" },  /* load halfword unsigned.        */
00197     { OPC(LSHUOP),"ldsthu"},  /* load store halfword unsigned.  */
00198     { OPC(LWOP),     "lw" },  /* load word.                     */
00199     { OPC(LSWOP), "ldstw" }   /* load store word.               */
00200   };
00201   int dlx_load_opcode_num =
00202     (sizeof dlx_load_opcode) / (sizeof dlx_load_opcode[0]);
00203   int idx;
00204 
00205   for (idx = 0 ; idx < dlx_load_opcode_num; idx++)
00206     if (dlx_load_opcode[idx].opcode == opc)
00207       {
00208        if (opc == OPC (LHIOP))
00209          {
00210            (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
00211            operand_deliminator (info, dlx_load_opcode[idx].name);
00212            (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
00213            (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
00214          }
00215        else
00216          {
00217            (*info->fprintf_func) (info->stream, "%s", dlx_load_opcode[idx].name);
00218            operand_deliminator (info, dlx_load_opcode[idx].name);
00219            (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
00220            (*info->fprintf_func) (info->stream, "0x%04x[r%d]", (int)imm16, (int)rs1);
00221          }
00222 
00223        return (unsigned char) ILD_TYPE;
00224     }
00225 
00226   return (unsigned char) NIL;
00227 }
00228 
00229 /* Process the memory store opcode.  */
00230 
00231 static unsigned char
00232 dlx_store_type (struct disassemble_info* info)
00233 {
00234   struct _store_opcode
00235   {
00236     unsigned long opcode;
00237     char *name;
00238   }
00239   dlx_store_opcode[] =
00240   {
00241     { OPC(SBOP),     "sb" },  /* Store byte.      */
00242     { OPC(SHOP),     "sh" },  /* Store halfword.  */
00243     { OPC(SWOP),     "sw" },  /* Store word.      */
00244   };
00245   int dlx_store_opcode_num =
00246     (sizeof dlx_store_opcode) / (sizeof dlx_store_opcode[0]);
00247   int idx;
00248 
00249   for (idx = 0 ; idx < dlx_store_opcode_num; idx++)
00250     if (dlx_store_opcode[idx].opcode == opc)
00251       {
00252        (*info->fprintf_func) (info->stream, "%s", dlx_store_opcode[idx].name);
00253        operand_deliminator (info, dlx_store_opcode[idx].name);
00254        (*info->fprintf_func) (info->stream, "0x%04x[r%d],", (int)imm16, (int)rs1);
00255        (*info->fprintf_func) (info->stream, "r%d", (int)rs2);
00256        return (unsigned char) IST_TYPE;
00257       }
00258 
00259   return (unsigned char) NIL;
00260 }
00261 
00262 /* Process the Arithmetic and Logical I-TYPE opcode.  */
00263 
00264 static unsigned char
00265 dlx_aluI_type (struct disassemble_info* info)
00266 {
00267   struct _aluI_opcode
00268   {
00269     unsigned long opcode;
00270     char *name;
00271   }
00272   dlx_aluI_opcode[] =
00273   {
00274     { OPC(ADDIOP),   "addi"  },  /* Store byte.      */
00275     { OPC(ADDUIOP),  "addui" },  /* Store halfword.  */
00276     { OPC(SUBIOP),   "subi"  },  /* Store word.      */
00277     { OPC(SUBUIOP),  "subui" },  /* Store word.      */
00278     { OPC(ANDIOP),   "andi"  },  /* Store word.      */
00279     { OPC(ORIOP),    "ori"   },  /* Store word.      */
00280     { OPC(XORIOP),   "xori"  },  /* Store word.      */
00281     { OPC(SLLIOP),   "slli"  },  /* Store word.      */
00282     { OPC(SRAIOP),   "srai"  },  /* Store word.      */
00283     { OPC(SRLIOP),   "srli"  },  /* Store word.      */
00284     { OPC(SEQIOP),   "seqi"  },  /* Store word.      */
00285     { OPC(SNEIOP),   "snei"  },  /* Store word.      */
00286     { OPC(SLTIOP),   "slti"  },  /* Store word.      */
00287     { OPC(SGTIOP),   "sgti"  },  /* Store word.      */
00288     { OPC(SLEIOP),   "slei"  },  /* Store word.      */
00289     { OPC(SGEIOP),   "sgei"  },  /* Store word.      */
00290     { OPC(SEQUIOP),  "sequi" },  /* Store word.      */
00291     { OPC(SNEUIOP),  "sneui" },  /* Store word.      */
00292     { OPC(SLTUIOP),  "sltui" },  /* Store word.      */
00293     { OPC(SGTUIOP),  "sgtui" },  /* Store word.      */
00294     { OPC(SLEUIOP),  "sleui" },  /* Store word.      */
00295     { OPC(SGEUIOP),  "sgeui" },  /* Store word.      */
00296 #if 0                                            
00297     { OPC(MVTSOP),   "mvts"  },  /* Store word.      */
00298     { OPC(MVFSOP),   "mvfs"  },  /* Store word.      */
00299 #endif
00300   };
00301   int dlx_aluI_opcode_num =
00302     (sizeof dlx_aluI_opcode) / (sizeof dlx_aluI_opcode[0]);
00303   int idx;
00304 
00305   for (idx = 0 ; idx < dlx_aluI_opcode_num; idx++)
00306     if (dlx_aluI_opcode[idx].opcode == opc)
00307       {
00308        (*info->fprintf_func) (info->stream, "%s", dlx_aluI_opcode[idx].name);
00309        operand_deliminator (info, dlx_aluI_opcode[idx].name);
00310        (*info->fprintf_func) (info->stream, "r%d,", (int)rs2);
00311        (*info->fprintf_func) (info->stream, "r%d,", (int)rs1);
00312        (*info->fprintf_func) (info->stream, "0x%04x", (int)imm16);
00313 
00314        return (unsigned char) IAL_TYPE;
00315       }
00316 
00317   return (unsigned char) NIL;
00318 }
00319 
00320 /* Process the branch instruction.  */
00321 
00322 static unsigned char
00323 dlx_br_type (struct disassemble_info* info)
00324 {
00325   struct _br_opcode
00326   {
00327     unsigned long opcode;
00328     char *name;
00329   }
00330   dlx_br_opcode[] =
00331   {
00332     { OPC(BEQOP), "beqz" }, /* Store byte.  */
00333     { OPC(BNEOP), "bnez" }  /* Store halfword.  */
00334   };
00335   int dlx_br_opcode_num =
00336     (sizeof dlx_br_opcode) / (sizeof dlx_br_opcode[0]);
00337   int idx;
00338 
00339   for (idx = 0 ; idx < dlx_br_opcode_num; idx++)
00340     if (dlx_br_opcode[idx].opcode == opc)
00341       {
00342        if (imm16 & 0x00008000)
00343          imm16 |= 0xFFFF0000;
00344 
00345        imm16 += (current_insn_addr + 4);
00346        (*info->fprintf_func) (info->stream, "%s", dlx_br_opcode[idx].name);
00347        operand_deliminator (info, dlx_br_opcode[idx].name);
00348        (*info->fprintf_func) (info->stream, "r%d,", (int) rs1);
00349        (*info->fprintf_func) (info->stream, "0x%08x", (int) imm16);
00350 
00351        return (unsigned char) IBR_TYPE;
00352       }
00353 
00354   return (unsigned char) NIL;
00355 }
00356 
00357 /* Process the jump instruction.  */
00358 
00359 static unsigned char
00360 dlx_jmp_type (struct disassemble_info* info)
00361 {
00362   struct _jmp_opcode
00363   {
00364     unsigned long opcode;
00365     char *name;
00366   }
00367   dlx_jmp_opcode[] =
00368   {
00369     { OPC(JOP),         "j" },  /* Store byte.      */
00370     { OPC(JALOP),     "jal" },  /* Store halfword.  */
00371     { OPC(BREAKOP), "break" },  /* Store halfword.  */
00372     { OPC(TRAPOP),   "trap" },  /* Store halfword.  */
00373     { OPC(RFEOP),     "rfe" }   /* Store halfword.  */
00374   };
00375   int dlx_jmp_opcode_num =
00376     (sizeof dlx_jmp_opcode) / (sizeof dlx_jmp_opcode[0]);
00377   int idx;
00378 
00379   for (idx = 0 ; idx < dlx_jmp_opcode_num; idx++)
00380     if (dlx_jmp_opcode[idx].opcode == opc)
00381       {
00382        if (imm26 & 0x02000000)
00383          imm26 |= 0xFC000000;
00384 
00385        imm26 += (current_insn_addr + 4);
00386 
00387        (*info->fprintf_func) (info->stream, "%s", dlx_jmp_opcode[idx].name);
00388        operand_deliminator (info, dlx_jmp_opcode[idx].name);
00389        (*info->fprintf_func) (info->stream, "0x%08x", (int)imm26);
00390 
00391        return (unsigned char) IJ_TYPE;
00392       }
00393 
00394   return (unsigned char) NIL;
00395 }
00396 
00397 /* Process the jump register instruction.  */
00398 
00399 static unsigned char
00400 dlx_jr_type (struct disassemble_info* info)
00401 {
00402   struct _jr_opcode
00403   {
00404     unsigned long opcode;
00405     char *name;
00406   }
00407   dlx_jr_opcode[] =
00408   {
00409     { OPC(JROP),   "jr"    },  /* Store byte.  */
00410     { OPC(JALROP), "jalr"  }   /* Store halfword.  */
00411   };
00412   int dlx_jr_opcode_num =
00413     (sizeof dlx_jr_opcode) / (sizeof dlx_jr_opcode[0]);
00414   int idx;
00415 
00416   for (idx = 0 ; idx < dlx_jr_opcode_num; idx++)
00417     if (dlx_jr_opcode[idx].opcode == opc)
00418       {
00419        (*info->fprintf_func) (info->stream, "%s", dlx_jr_opcode[idx].name);
00420        operand_deliminator (info, dlx_jr_opcode[idx].name);
00421        (*info->fprintf_func) (info->stream, "r%d", (int)rs1);
00422        return (unsigned char) IJR_TYPE;
00423       }
00424 
00425   return (unsigned char) NIL;
00426 }
00427 
00428 typedef unsigned char (* dlx_insn) (struct disassemble_info *);
00429 
00430 /* This is the main DLX insn handling routine.  */
00431 
00432 int
00433 print_insn_dlx (bfd_vma memaddr, struct disassemble_info* info)
00434 {
00435   bfd_byte buffer[4];
00436   int insn_idx;
00437   unsigned long insn_word;
00438   unsigned char rtn_code;
00439   unsigned long dlx_insn_type[] =
00440   {
00441     (unsigned long) dlx_r_type,
00442     (unsigned long) dlx_load_type,
00443     (unsigned long) dlx_store_type,
00444     (unsigned long) dlx_aluI_type,
00445     (unsigned long) dlx_br_type,
00446     (unsigned long) dlx_jmp_type,
00447     (unsigned long) dlx_jr_type,
00448     (unsigned long) NULL
00449   };
00450   int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1;
00451   int status =
00452     (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info);
00453 
00454   if (status != 0)
00455     {
00456       (*info->memory_error_func) (status, memaddr, info);
00457       return -1;
00458     }
00459 
00460   /* Now decode the insn    */
00461   insn_word = bfd_getb32 (buffer);
00462   opc  = dlx_get_opcode (insn_word);
00463   rs1  = dlx_get_rs1 (insn_word);
00464   rs2  = dlx_get_rs2 (insn_word);
00465   rd   = dlx_get_rdR (insn_word);
00466   func = dlx_get_func (insn_word);
00467   imm16= dlx_get_imm16 (insn_word);
00468   imm26= dlx_get_imm26 (insn_word);
00469 
00470 #if 0
00471   printf ("print_insn_big_dlx: opc = 0x%02x\n"
00472          "                    rs1 = 0x%02x\n"
00473          "                    rs2 = 0x%02x\n"
00474          "                    rd  = 0x%02x\n"
00475          "                  func  = 0x%08x\n"
00476          "                 imm16  = 0x%08x\n"
00477          "                 imm26  = 0x%08x\n",
00478          opc, rs1, rs2, rd, func, imm16, imm26);
00479 #endif
00480 
00481   /* Scan through all the insn type and print the insn out.  */
00482   rtn_code = 0;
00483   current_insn_addr = (unsigned long) memaddr;
00484 
00485   for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
00486     switch (((dlx_insn) (dlx_insn_type[insn_idx])) (info))
00487       {
00488        /* Found the correct opcode   */
00489       case R_TYPE:
00490       case ILD_TYPE:
00491       case IST_TYPE:
00492       case IAL_TYPE:
00493       case IBR_TYPE:
00494       case IJ_TYPE:
00495       case IJR_TYPE:
00496        return 4;
00497 
00498        /* Wrong insn type check next one. */
00499       default:
00500       case NIL:
00501        continue;
00502 
00503        /* All rest of the return code are not recongnized, treat it as error */
00504        /* we should never get here,  I hope! */
00505       case R_ERROR:
00506        return -1;
00507       }
00508 
00509   if (insn_idx ==  dlx_insn_type_num)
00510     /* Well, does not recoganize this opcode.  */
00511     (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode");
00512 
00513   return 4;
00514 }