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cell-binutils  2.17cvs20070401
Classes | Defines | Typedefs | Enumerations | Functions
dis-asm.h File Reference
#include <stdio.h>
#include "bfd.h"

Go to the source code of this file.

Classes

struct  disassemble_info

Defines

#define INSN_HAS_RELOC   0x80000000
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC)   init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))
#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)   init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))

Typedefs

typedef int(* fprintf_ftype )(void *, const char *,...)
typedef struct disassemble_info disassemble_info
typedef int(* disassembler_ftype )(bfd_vma, disassemble_info *)

Enumerations

enum  dis_insn_type {
  dis_noninsn, dis_nonbranch, dis_branch, dis_condbranch,
  dis_jsr, dis_condjsr, dis_dref, dis_dref2
}

Functions

int print_insn_alpha (bfd_vma, disassemble_info *)
int print_insn_avr (bfd_vma, disassemble_info *)
int print_insn_bfin (bfd_vma, disassemble_info *)
int print_insn_big_arm (bfd_vma, disassemble_info *)
int print_insn_big_mips (bfd_vma, disassemble_info *)
int print_insn_big_or32 (bfd_vma, disassemble_info *)
int print_insn_big_powerpc (bfd_vma, disassemble_info *)
int print_insn_big_score (bfd_vma, disassemble_info *)
int print_insn_crx (bfd_vma, disassemble_info *)
int print_insn_d10v (bfd_vma, disassemble_info *)
int print_insn_d30v (bfd_vma, disassemble_info *)
int print_insn_dlx (bfd_vma, disassemble_info *)
int print_insn_fr30 (bfd_vma, disassemble_info *)
int print_insn_frv (bfd_vma, disassemble_info *)
int print_insn_h8300 (bfd_vma, disassemble_info *)
int print_insn_h8300h (bfd_vma, disassemble_info *)
int print_insn_h8300s (bfd_vma, disassemble_info *)
int print_insn_h8500 (bfd_vma, disassemble_info *)
int print_insn_hppa (bfd_vma, disassemble_info *)
int print_insn_i370 (bfd_vma, disassemble_info *)
int print_insn_i386 (bfd_vma, disassemble_info *)
int print_insn_i386_att (bfd_vma, disassemble_info *)
int print_insn_i386_intel (bfd_vma, disassemble_info *)
int print_insn_i860 (bfd_vma, disassemble_info *)
int print_insn_i960 (bfd_vma, disassemble_info *)
int print_insn_ia64 (bfd_vma, disassemble_info *)
int print_insn_ip2k (bfd_vma, disassemble_info *)
int print_insn_iq2000 (bfd_vma, disassemble_info *)
int print_insn_little_arm (bfd_vma, disassemble_info *)
int print_insn_little_mips (bfd_vma, disassemble_info *)
int print_insn_little_or32 (bfd_vma, disassemble_info *)
int print_insn_little_powerpc (bfd_vma, disassemble_info *)
int print_insn_little_score (bfd_vma, disassemble_info *)
int print_insn_m32c (bfd_vma, disassemble_info *)
int print_insn_m32r (bfd_vma, disassemble_info *)
int print_insn_m68hc11 (bfd_vma, disassemble_info *)
int print_insn_m68hc12 (bfd_vma, disassemble_info *)
int print_insn_m68k (bfd_vma, disassemble_info *)
int print_insn_m88k (bfd_vma, disassemble_info *)
int print_insn_maxq_big (bfd_vma, disassemble_info *)
int print_insn_maxq_little (bfd_vma, disassemble_info *)
int print_insn_mcore (bfd_vma, disassemble_info *)
int print_insn_mep (bfd_vma, disassemble_info *)
int print_insn_mmix (bfd_vma, disassemble_info *)
int print_insn_mn10200 (bfd_vma, disassemble_info *)
int print_insn_mn10300 (bfd_vma, disassemble_info *)
int print_insn_msp430 (bfd_vma, disassemble_info *)
int print_insn_mt (bfd_vma, disassemble_info *)
int print_insn_ns32k (bfd_vma, disassemble_info *)
int print_insn_openrisc (bfd_vma, disassemble_info *)
int print_insn_pdp11 (bfd_vma, disassemble_info *)
int print_insn_pj (bfd_vma, disassemble_info *)
int print_insn_rs6000 (bfd_vma, disassemble_info *)
int print_insn_s390 (bfd_vma, disassemble_info *)
int print_insn_sh (bfd_vma, disassemble_info *)
int print_insn_sh64 (bfd_vma, disassemble_info *)
int print_insn_sh64x_media (bfd_vma, disassemble_info *)
int print_insn_sparc (bfd_vma, disassemble_info *)
int print_insn_spu (bfd_vma, disassemble_info *)
int print_insn_tic30 (bfd_vma, disassemble_info *)
int print_insn_tic4x (bfd_vma, disassemble_info *)
int print_insn_tic54x (bfd_vma, disassemble_info *)
int print_insn_tic80 (bfd_vma, disassemble_info *)
int print_insn_v850 (bfd_vma, disassemble_info *)
int print_insn_vax (bfd_vma, disassemble_info *)
int print_insn_w65 (bfd_vma, disassemble_info *)
int print_insn_xc16x (bfd_vma, disassemble_info *)
int print_insn_xstormy16 (bfd_vma, disassemble_info *)
int print_insn_xtensa (bfd_vma, disassemble_info *)
int print_insn_z80 (bfd_vma, disassemble_info *)
int print_insn_z8001 (bfd_vma, disassemble_info *)
int print_insn_z8002 (bfd_vma, disassemble_info *)
disassembler_ftype arc_get_disassembler (void *)
disassembler_ftype cris_get_disassembler (bfd *)
void print_i386_disassembler_options (FILE *)
void print_mips_disassembler_options (FILE *)
void print_ppc_disassembler_options (FILE *)
void print_arm_disassembler_options (FILE *)
void parse_arm_disassembler_option (char *)
int get_arm_regname_num_options (void)
int set_arm_regname_option (int)
int get_arm_regnames (int, const char **, const char **, const char *const **)
bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *)
disassembler_ftype disassembler (bfd *)
void disassemble_init_for_target (struct disassemble_info *info)
void disassembler_usage (FILE *)
int buffer_read_memory (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *)
void perror_memory (int, bfd_vma, struct disassemble_info *)
void generic_print_address (bfd_vma, struct disassemble_info *)
int generic_symbol_at_address (bfd_vma, struct disassemble_info *)
bfd_boolean generic_symbol_is_valid (asymbol *, struct disassemble_info *)
void init_disassemble_info (struct disassemble_info *info, void *stream, fprintf_ftype fprintf_func)

Class Documentation

struct disassemble_info

Definition at line 62 of file dis-asm.h.

Class Members
void * application_data
fprintf_ftype fprintf_func
void * stream

Define Documentation

#define INIT_DISASSEMBLE_INFO (   INFO,
  STREAM,
  FPRINTF_FUNC 
)    init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))

Definition at line 342 of file dis-asm.h.

#define INIT_DISASSEMBLE_INFO_NO_ARCH (   INFO,
  STREAM,
  FPRINTF_FUNC 
)    init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC))

Definition at line 344 of file dis-asm.h.

#define INSN_HAS_RELOC   0x80000000

Typedef Documentation

Definition at line 210 of file dis-asm.h.

typedef int(* fprintf_ftype)(void *, const char *,...)

Definition at line 38 of file dis-asm.h.


Enumeration Type Documentation

Enumerator:
dis_noninsn 
dis_nonbranch 
dis_branch 
dis_condbranch 
dis_jsr 
dis_condjsr 
dis_dref 
dis_dref2 

Definition at line 40 of file dis-asm.h.

{
  dis_noninsn,                     /* Not a valid instruction */
  dis_nonbranch,            /* Not a branch instruction */
  dis_branch,               /* Unconditional branch */
  dis_condbranch,           /* Conditional branch */
  dis_jsr,                  /* Jump to subroutine */
  dis_condjsr,                     /* Conditional jump to subroutine */
  dis_dref,                 /* Data reference instruction */
  dis_dref2                 /* Two data references in instruction */
};

Function Documentation

Definition at line 1226 of file arc-dis.c.

{
  if (ptr)
    build_ARC_extmap (ptr);
  return decodeInstr;
}

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Definition at line 28 of file dis-buf.c.

{
  unsigned int opb = info->octets_per_byte;
  unsigned int end_addr_offset = length / opb;
  unsigned int max_addr_offset = info->buffer_length / opb; 
  unsigned int octets = (memaddr - info->buffer_vma) * opb;

  if (memaddr < info->buffer_vma
      || memaddr - info->buffer_vma + end_addr_offset > max_addr_offset)
    /* Out of bounds.  Use EIO because GDB uses it.  */
    return EIO;
  memcpy (myaddr, info->buffer + octets, length);

  return 0;
}

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Definition at line 1655 of file cris-dis.c.

{
  /* If there's no bfd in sight, we return what is valid as input in all
     contexts if fed back to the assembler: disassembly *with* register
     prefix.  Unfortunately this will be totally wrong for v32.  */
  if (abfd == NULL)
    return print_insn_cris_with_register_prefix;

  if (bfd_get_symbol_leading_char (abfd) == 0)
    {
      if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
       return print_insn_crisv32_with_register_prefix;
      if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
       return print_insn_crisv10_v32_with_register_prefix;

      /* We default to v10.  This may be specifically specified in the
        bfd mach, but is also the default setting.  */
      return print_insn_cris_with_register_prefix;
    }

  if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
    return print_insn_crisv32_without_register_prefix;
  if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
    return print_insn_crisv10_v32_without_register_prefix;
  return print_insn_cris_without_register_prefix;
}

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Definition at line 465 of file disassemble.c.

{
  if (info == NULL)
    return;

  switch (info->arch)
    {
#ifdef ARCH_arm
    case bfd_arch_arm:
      info->symbol_is_valid = arm_symbol_is_valid;
      info->disassembler_needs_relocs = TRUE;
      break;
#endif
#ifdef ARCH_ia64
    case bfd_arch_ia64:
      info->skip_zeroes = 16;
      break;
#endif
#ifdef ARCH_tic4x
    case bfd_arch_tic4x:
      info->skip_zeroes = 32;
      break;
#endif
#ifdef ARCH_mep
    case bfd_arch_mep:
      info->skip_zeroes = 256;
      info->skip_zeroes_at_end = 0;
      break;
#endif
#ifdef ARCH_m32c
    case bfd_arch_m32c:
      info->endian = BFD_ENDIAN_BIG;
      if (! info->insn_sets)
       {
         info->insn_sets = cgen_bitset_create (ISA_MAX);
         if (info->mach == bfd_mach_m16c)
           cgen_bitset_set (info->insn_sets, ISA_M16C);
         else
           cgen_bitset_set (info->insn_sets, ISA_M32C);
       }
      break;
#endif
    default:
      break;
    }
}

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Definition at line 92 of file disassemble.c.

{
  enum bfd_architecture a = bfd_get_arch (abfd);
  disassembler_ftype disassemble;

  switch (a)
    {
      /* If you add a case to this table, also add it to the
        ARCH_all definition right above this function.  */
#ifdef ARCH_alpha
    case bfd_arch_alpha:
      disassemble = print_insn_alpha;
      break;
#endif
#ifdef ARCH_arc
    case bfd_arch_arc:
      {
       disassemble = arc_get_disassembler (abfd);
       break;
      }
#endif
#ifdef ARCH_arm
    case bfd_arch_arm:
      if (bfd_big_endian (abfd))
       disassemble = print_insn_big_arm;
      else
       disassemble = print_insn_little_arm;
      break;
#endif
#ifdef ARCH_avr
    case bfd_arch_avr:
      disassemble = print_insn_avr;
      break;
#endif
#ifdef ARCH_bfin
    case bfd_arch_bfin:
      disassemble = print_insn_bfin;
      break;
#endif
#ifdef ARCH_cris
    case bfd_arch_cris:
      disassemble = cris_get_disassembler (abfd);
      break;
#endif
#ifdef ARCH_crx
    case bfd_arch_crx:
      disassemble = print_insn_crx;
      break;
#endif
#ifdef ARCH_d10v
    case bfd_arch_d10v:
      disassemble = print_insn_d10v;
      break;
#endif
#ifdef ARCH_d30v
    case bfd_arch_d30v:
      disassemble = print_insn_d30v;
      break;
#endif
#ifdef ARCH_dlx
    case bfd_arch_dlx:
      /* As far as I know we only handle big-endian DLX objects.  */
      disassemble = print_insn_dlx;
      break;
#endif
#ifdef ARCH_h8300
    case bfd_arch_h8300:
      if (bfd_get_mach (abfd) == bfd_mach_h8300h
         || bfd_get_mach (abfd) == bfd_mach_h8300hn)
       disassemble = print_insn_h8300h;
      else if (bfd_get_mach (abfd) == bfd_mach_h8300s
              || bfd_get_mach (abfd) == bfd_mach_h8300sn
              || bfd_get_mach (abfd) == bfd_mach_h8300sx
              || bfd_get_mach (abfd) == bfd_mach_h8300sxn)
       disassemble = print_insn_h8300s;
      else
       disassemble = print_insn_h8300;
      break;
#endif
#ifdef ARCH_h8500
    case bfd_arch_h8500:
      disassemble = print_insn_h8500;
      break;
#endif
#ifdef ARCH_hppa
    case bfd_arch_hppa:
      disassemble = print_insn_hppa;
      break;
#endif
#ifdef ARCH_i370
    case bfd_arch_i370:
      disassemble = print_insn_i370;
      break;
#endif
#ifdef ARCH_i386
    case bfd_arch_i386:
      disassemble = print_insn_i386;
      break;
#endif
#ifdef ARCH_i860
    case bfd_arch_i860:
      disassemble = print_insn_i860;
      break;
#endif
#ifdef ARCH_i960
    case bfd_arch_i960:
      disassemble = print_insn_i960;
      break;
#endif
#ifdef ARCH_ia64
    case bfd_arch_ia64:
      disassemble = print_insn_ia64;
      break;
#endif
#ifdef ARCH_ip2k
    case bfd_arch_ip2k:
      disassemble = print_insn_ip2k;
      break;
#endif
#ifdef ARCH_fr30
    case bfd_arch_fr30:
      disassemble = print_insn_fr30;
      break;
#endif
#ifdef ARCH_m32r
    case bfd_arch_m32r:
      disassemble = print_insn_m32r;
      break;
#endif
#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12)
    case bfd_arch_m68hc11:
      disassemble = print_insn_m68hc11;
      break;
    case bfd_arch_m68hc12:
      disassemble = print_insn_m68hc12;
      break;
#endif
#ifdef ARCH_m68k
    case bfd_arch_m68k:
      disassemble = print_insn_m68k;
      break;
#endif
#ifdef ARCH_m88k
    case bfd_arch_m88k:
      disassemble = print_insn_m88k;
      break;
#endif
#ifdef ARCH_maxq
    case bfd_arch_maxq:
      disassemble = print_insn_maxq_little;
      break;
#endif
#ifdef ARCH_mt
    case bfd_arch_mt:
      disassemble = print_insn_mt;
      break;
#endif
#ifdef ARCH_msp430
    case bfd_arch_msp430:
      disassemble = print_insn_msp430;
      break;
#endif
#ifdef ARCH_ns32k
    case bfd_arch_ns32k:
      disassemble = print_insn_ns32k;
      break;
#endif
#ifdef ARCH_mcore
    case bfd_arch_mcore:
      disassemble = print_insn_mcore;
      break;
#endif
#ifdef ARCH_mep
    case bfd_arch_mep:
      disassemble = print_insn_mep;
      break;
#endif
#ifdef ARCH_mips
    case bfd_arch_mips:
      if (bfd_big_endian (abfd))
       disassemble = print_insn_big_mips;
      else
       disassemble = print_insn_little_mips;
      break;
#endif
#ifdef ARCH_mmix
    case bfd_arch_mmix:
      disassemble = print_insn_mmix;
      break;
#endif
#ifdef ARCH_mn10200
    case bfd_arch_mn10200:
      disassemble = print_insn_mn10200;
      break;
#endif
#ifdef ARCH_mn10300
    case bfd_arch_mn10300:
      disassemble = print_insn_mn10300;
      break;
#endif
#ifdef ARCH_openrisc
    case bfd_arch_openrisc:
      disassemble = print_insn_openrisc;
      break;
#endif
#ifdef ARCH_or32
    case bfd_arch_or32:
      if (bfd_big_endian (abfd))
        disassemble = print_insn_big_or32;
      else
        disassemble = print_insn_little_or32;
      break;
#endif
#ifdef ARCH_pdp11
    case bfd_arch_pdp11:
      disassemble = print_insn_pdp11;
      break;
#endif
#ifdef ARCH_pj
    case bfd_arch_pj:
      disassemble = print_insn_pj;
      break;
#endif
#ifdef ARCH_powerpc
    case bfd_arch_powerpc:
      if (bfd_big_endian (abfd))
       disassemble = print_insn_big_powerpc;
      else
       disassemble = print_insn_little_powerpc;
      break;
#endif
#ifdef ARCH_rs6000
    case bfd_arch_rs6000:
      if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
       disassemble = print_insn_big_powerpc;
      else
       disassemble = print_insn_rs6000;
      break;
#endif
#ifdef ARCH_s390
    case bfd_arch_s390:
      disassemble = print_insn_s390;
      break;
#endif
#ifdef ARCH_score
    case bfd_arch_score:
      if (bfd_big_endian (abfd))
        disassemble = print_insn_big_score;      
      else
        disassemble = print_insn_little_score; 
     break;
#endif
#ifdef ARCH_sh
    case bfd_arch_sh:
      disassemble = print_insn_sh;
      break;
#endif
#ifdef ARCH_sparc
    case bfd_arch_sparc:
      disassemble = print_insn_sparc;
      break;
#endif
#ifdef ARCH_spu
    case bfd_arch_spu:
      disassemble = print_insn_spu;
      break;
#endif
#ifdef ARCH_tic30
    case bfd_arch_tic30:
      disassemble = print_insn_tic30;
      break;
#endif
#ifdef ARCH_tic4x
    case bfd_arch_tic4x:
      disassemble = print_insn_tic4x;
      break;
#endif
#ifdef ARCH_tic54x
    case bfd_arch_tic54x:
      disassemble = print_insn_tic54x;
      break;
#endif
#ifdef ARCH_tic80
    case bfd_arch_tic80:
      disassemble = print_insn_tic80;
      break;
#endif
#ifdef ARCH_v850
    case bfd_arch_v850:
      disassemble = print_insn_v850;
      break;
#endif
#ifdef ARCH_w65
    case bfd_arch_w65:
      disassemble = print_insn_w65;
      break;
#endif
#ifdef ARCH_xstormy16
    case bfd_arch_xstormy16:
      disassemble = print_insn_xstormy16;
      break;
#endif
#ifdef ARCH_xc16x
    case bfd_arch_xc16x:
      disassemble = print_insn_xc16x;
      break;
#endif
#ifdef ARCH_xtensa
    case bfd_arch_xtensa:
      disassemble = print_insn_xtensa;
      break;
#endif
#ifdef ARCH_z80
    case bfd_arch_z80:
      disassemble = print_insn_z80;
      break;
#endif
#ifdef ARCH_z8k
    case bfd_arch_z8k:
      if (bfd_get_mach(abfd) == bfd_mach_z8001)
       disassemble = print_insn_z8001;
      else
       disassemble = print_insn_z8002;
      break;
#endif
#ifdef ARCH_vax
    case bfd_arch_vax:
      disassemble = print_insn_vax;
      break;
#endif
#ifdef ARCH_frv
    case bfd_arch_frv:
      disassemble = print_insn_frv;
      break;
#endif
#ifdef ARCH_iq2000
    case bfd_arch_iq2000:
      disassemble = print_insn_iq2000;
      break;
#endif
#ifdef ARCH_m32c
    case bfd_arch_m32c:
      disassemble = print_insn_m32c;
      break;
#endif
    default:
      return 0;
    }
  return disassemble;
}

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void disassembler_usage ( FILE *  )

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Definition at line 78 of file dis-buf.c.

{
  char buf[30];

  sprintf_vma (buf, addr);
  (*info->fprintf_func) (info->stream, "0x%s", buf);
}

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int get_arm_regname_num_options ( void  ) [abstract]

Definition at line 1498 of file arm-dis.c.

{
  return NUM_ARM_REGNAMES;
}
int get_arm_regnames ( int  ,
const char **  ,
const char **  ,
const char *const **   
)

Definition at line 1512 of file arm-dis.c.

{
  *setname = regnames[option].name;
  *setdescription = regnames[option].description;
  *register_names = regnames[option].reg_names;
  return 16;
}
void init_disassemble_info ( struct disassemble_info info,
void *  stream,
fprintf_ftype  fprintf_func 
)

Definition at line 25 of file dis-init.c.

{
  memset (info, 0, sizeof (*info));

  info->flavour = bfd_target_unknown_flavour;
  info->arch = bfd_arch_unknown;
  info->endian = BFD_ENDIAN_UNKNOWN;
  info->octets_per_byte = 1;
  info->fprintf_func = fprintf_func;
  info->stream = stream;
  info->read_memory_func = buffer_read_memory;
  info->memory_error_func = perror_memory;
  info->print_address_func = generic_print_address;
  info->symbol_at_address_func = generic_symbol_at_address;
  info->symbol_is_valid = generic_symbol_is_valid;
  info->display_endian = BFD_ENDIAN_UNKNOWN;
}

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void parse_arm_disassembler_option ( char *  )

Definition at line 3768 of file arm-dis.c.

{
  if (option == NULL)
    return;

  if (CONST_STRNEQ (option, "reg-names-"))
    {
      int i;

      option += 10;

      for (i = NUM_ARM_REGNAMES; i--;)
       if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
         {
           regname_selected = i;
           break;
         }

      if (i < 0)
       /* XXX - should break 'option' at following delimiter.  */
       fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
    }
  else if (CONST_STRNEQ (option, "force-thumb"))
    force_thumb = 1;
  else if (CONST_STRNEQ (option, "no-force-thumb"))
    force_thumb = 0;
  else
    /* XXX - should break 'option' at following delimiter.  */
    fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);

  return;
}

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void perror_memory ( int  ,
bfd_vma  ,
struct disassemble_info  
)

Definition at line 51 of file dis-buf.c.

{
  if (status != EIO)
    /* Can't happen.  */
    info->fprintf_func (info->stream, _("Unknown error %d\n"), status);
  else
    {
      char buf[30];

      /* Actually, address between memaddr and memaddr + len was
        out of bounds.  */
      sprintf_vma (buf, memaddr);
      info->fprintf_func (info->stream,
                       _("Address 0x%s is out of bounds.\n"), buf);
    }
}

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void print_arm_disassembler_options ( FILE *  )

Definition at line 4190 of file arm-dis.c.

{
  int i;

  fprintf (stream, _("\n\
The following ARM specific disassembler options are supported for use with\n\
the -M switch:\n"));

  for (i = NUM_ARM_REGNAMES; i--;)
    fprintf (stream, "  reg-names-%s %*c%s\n",
            regnames[i].name,
            (int)(14 - strlen (regnames[i].name)), ' ',
            regnames[i].description);

  fprintf (stream, "  force-thumb              Assume all insns are Thumb insns\n");
  fprintf (stream, "  no-force-thumb           Examine preceeding label to determine an insn's type\n\n");
}

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Definition at line 2859 of file i386-dis.c.

{
  fprintf (stream, _("\n\
The following i386/x86-64 specific disassembler options are supported for use\n\
with the -M switch (multiple options should be separated by commas):\n"));

  fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
  fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
  fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
  fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
  fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
  fprintf (stream, _("  addr64      Assume 64bit address size\n"));
  fprintf (stream, _("  addr32      Assume 32bit address size\n"));
  fprintf (stream, _("  addr16      Assume 16bit address size\n"));
  fprintf (stream, _("  data32      Assume 32bit data size\n"));
  fprintf (stream, _("  data16      Assume 16bit data size\n"));
  fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
}

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Definition at line 58 of file alpha-dis.c.

{
  static const struct alpha_opcode *opcode_index[AXP_NOPS+1];
  const char * const * regnames;
  const struct alpha_opcode *opcode, *opcode_end;
  const unsigned char *opindex;
  unsigned insn, op, isa_mask;
  int need_comma;

  /* Initialize the majorop table the first time through */
  if (!opcode_index[0])
    {
      opcode = alpha_opcodes;
      opcode_end = opcode + alpha_num_opcodes;

      for (op = 0; op < AXP_NOPS; ++op)
       {
         opcode_index[op] = opcode;
         while (opcode < opcode_end && op == AXP_OP (opcode->opcode))
           ++opcode;
       }
      opcode_index[op] = opcode;
    }

  if (info->flavour == bfd_target_evax_flavour)
    regnames = vms_regnames;
  else
    regnames = osf_regnames;

  isa_mask = AXP_OPCODE_NOPAL;
  switch (info->mach)
    {
    case bfd_mach_alpha_ev4:
      isa_mask |= AXP_OPCODE_EV4;
      break;
    case bfd_mach_alpha_ev5:
      isa_mask |= AXP_OPCODE_EV5;
      break;
    case bfd_mach_alpha_ev6:
      isa_mask |= AXP_OPCODE_EV6;
      break;
    }

  /* Read the insn into a host word */
  {
    bfd_byte buffer[4];
    int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
    if (status != 0)
      {
       (*info->memory_error_func) (status, memaddr, info);
       return -1;
      }
    insn = bfd_getl32 (buffer);
  }

  /* Get the major opcode of the instruction.  */
  op = AXP_OP (insn);

  /* Find the first match in the opcode table.  */
  opcode_end = opcode_index[op + 1];
  for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode)
    {
      if ((insn ^ opcode->opcode) & opcode->mask)
       continue;

      if (!(opcode->flags & isa_mask))
       continue;

      /* Make two passes over the operands.  First see if any of them
        have extraction functions, and, if they do, make sure the
        instruction is valid.  */
      {
       int invalid = 0;
       for (opindex = opcode->operands; *opindex != 0; opindex++)
         {
           const struct alpha_operand *operand = alpha_operands + *opindex;
           if (operand->extract)
             (*operand->extract) (insn, &invalid);
         }
       if (invalid)
         continue;
      }

      /* The instruction is valid.  */
      goto found;
    }

  /* No instruction found */
  (*info->fprintf_func) (info->stream, ".long %#08x", insn);

  return 4;

found:
  (*info->fprintf_func) (info->stream, "%s", opcode->name);
  if (opcode->operands[0] != 0)
    (*info->fprintf_func) (info->stream, "\t");

  /* Now extract and print the operands.  */
  need_comma = 0;
  for (opindex = opcode->operands; *opindex != 0; opindex++)
    {
      const struct alpha_operand *operand = alpha_operands + *opindex;
      int value;

      /* Operands that are marked FAKE are simply ignored.  We
        already made sure that the extract function considered
        the instruction to be valid.  */
      if ((operand->flags & AXP_OPERAND_FAKE) != 0)
       continue;

      /* Extract the value from the instruction.  */
      if (operand->extract)
       value = (*operand->extract) (insn, (int *) NULL);
      else
       {
         value = (insn >> operand->shift) & ((1 << operand->bits) - 1);
         if (operand->flags & AXP_OPERAND_SIGNED)
           {
             int signbit = 1 << (operand->bits - 1);
             value = (value ^ signbit) - signbit;
           }
       }

      if (need_comma &&
         ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA))
          != AXP_OPERAND_PARENS))
       {
         (*info->fprintf_func) (info->stream, ",");
       }
      if (operand->flags & AXP_OPERAND_PARENS)
       (*info->fprintf_func) (info->stream, "(");

      /* Print the operand as directed by the flags.  */
      if (operand->flags & AXP_OPERAND_IR)
       (*info->fprintf_func) (info->stream, "%s", regnames[value]);
      else if (operand->flags & AXP_OPERAND_FPR)
       (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]);
      else if (operand->flags & AXP_OPERAND_RELATIVE)
       (*info->print_address_func) (memaddr + 4 + value, info);
      else if (operand->flags & AXP_OPERAND_SIGNED)
       (*info->fprintf_func) (info->stream, "%d", value);
      else
       (*info->fprintf_func) (info->stream, "%#x", value);

      if (operand->flags & AXP_OPERAND_PARENS)
       (*info->fprintf_func) (info->stream, ")");
      need_comma = 1;
    }

  return 4;
}

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Definition at line 257 of file avr-dis.c.

{
  unsigned int insn, insn2;
  const struct avr_opcodes_s *opcode;
  static unsigned int *maskptr;
  void *stream = info->stream;
  fprintf_ftype prin = info->fprintf_func;
  static unsigned int *avr_bin_masks;
  static int initialized;
  int cmd_len = 2;
  int ok = 0;
  char op1[20], op2[20], comment1[40], comment2[40];
  int sym_op1 = 0, sym_op2 = 0;
  bfd_vma sym_addr1, sym_addr2;


  if (!initialized)
    {
      unsigned int nopcodes;

      /* PR 4045: Try to avoid duplicating the 0x prefix that
        objdump_print_addr() will put on addresses when there
        is no symbol table available.  */
      if (info->symtab_size == 0)
       comment_start = " ";

      nopcodes = sizeof (avr_opcodes) / sizeof (struct avr_opcodes_s);
      
      avr_bin_masks = xmalloc (nopcodes * sizeof (unsigned int));

      for (opcode = avr_opcodes, maskptr = avr_bin_masks;
          opcode->name;
          opcode++, maskptr++)
       {
         char * s;
         unsigned int bin = 0;
         unsigned int mask = 0;
       
         for (s = opcode->opcode; *s; ++s)
           {
             bin <<= 1;
             mask <<= 1;
             bin |= (*s == '1');
             mask |= (*s == '1' || *s == '0');
           }
         assert (s - opcode->opcode == 16);
         assert (opcode->bin_opcode == bin);
         *maskptr = mask;
       }

      initialized = 1;
    }

  insn = avrdis_opcode (addr, info);
  
  for (opcode = avr_opcodes, maskptr = avr_bin_masks;
       opcode->name;
       opcode++, maskptr++)
    if ((insn & *maskptr) == opcode->bin_opcode)
      break;
  
  /* Special case: disassemble `ldd r,b+0' as `ld r,b', and
     `std b+0,r' as `st b,r' (next entry in the table).  */

  if (AVR_DISP0_P (insn))
    opcode++;

  op1[0] = 0;
  op2[0] = 0;
  comment1[0] = 0;
  comment2[0] = 0;

  if (opcode->name)
    {
      char *op = opcode->constraints;

      insn2 = 0;
      ok = 1;

      if (opcode->insn_size > 1)
       {
         insn2 = avrdis_opcode (addr + 2, info);
         cmd_len = 4;
       }

      if (*op && *op != '?')
       {
         int regs = REGISTER_P (*op);

         ok = avr_operand (insn, insn2, addr, *op, op1, comment1, 0, &sym_op1, &sym_addr1);

         if (ok && *(++op) == ',')
           ok = avr_operand (insn, insn2, addr, *(++op), op2,
                           *comment1 ? comment2 : comment1, regs, &sym_op2, &sym_addr2);
       }
    }

  if (!ok)
    {
      /* Unknown opcode, or invalid combination of operands.  */
      sprintf (op1, "0x%04x", insn);
      op2[0] = 0;
      sprintf (comment1, "????");
      comment2[0] = 0;
    }

  (*prin) (stream, "%s", ok ? opcode->name : ".word");

  if (*op1)
      (*prin) (stream, "\t%s", op1);

  if (*op2)
    (*prin) (stream, ", %s", op2);

  if (*comment1)
    (*prin) (stream, "\t; %s", comment1);

  if (sym_op1)
    info->print_address_func (sym_addr1, info);

  if (*comment2)
    (*prin) (stream, " %s", comment2);

  if (sym_op2)
    info->print_address_func (sym_addr2, info);

  return cmd_len;
}

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Definition at line 4418 of file bfin-dis.c.

{
  bfd_byte buf[2];
  unsigned short iw0;
  int status;
  int count = 0;

  status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
  iw0 = bfd_getl16 (buf);

  count += _print_insn_bfin (pc, outf);

  /* Proper display of multiple issue instructions.  */

  if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
      && ((iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
    {
      outf->fprintf_func (outf->stream, " || ");
      count += _print_insn_bfin (pc + 4, outf);
      outf->fprintf_func (outf->stream, " || ");
      count += _print_insn_bfin (pc + 6, outf);
    }
  if (count == 0)
    {
      outf->fprintf_func (outf->stream, "ILLEGAL");
      return 2;
    }
  outf->fprintf_func (outf->stream, ";");
  return count;
}

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Definition at line 4178 of file arm-dis.c.

{
  return print_insn (pc, info, FALSE);
}

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Definition at line 2033 of file mips-dis.c.

{
  return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
}

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Definition at line 310 of file or32-dis.c.

{
  info->private_data = find_bytes_big;

  return print_insn (memaddr, info);
}

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Definition at line 107 of file ppc-dis.c.

{
  int dialect = (char *) info->private_data - (char *) 0;
  return print_insn_powerpc (memaddr, info, 1, dialect);
}

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Definition at line 495 of file score-dis.c.

{
  return print_insn (pc, info, FALSE);
}

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Definition at line 716 of file crx-dis.c.

{
  int is_decoded;     /* Nonzero means instruction has a match.  */

  /* Initialize global variables.  */
  cst4flag = 0;
  size_changed = 0;

  /* Retrieve the encoding from current memory location.  */
  get_words_at_PC (memaddr, info);
  /* Find a matching opcode in table.  */
  is_decoded = match_opcode ();
  /* If found, print the instruction's mnemonic and arguments.  */
  if (is_decoded > 0 && (words[0] << 16 || words[1]) != 0)
    {
      info->fprintf_func (info->stream, "%s", instruction->mnemonic);
      if ((currInsn.nargs = get_number_of_operands ()) != 0)
       info->fprintf_func (info->stream, "\t");
      make_instruction ();
      print_arguments (&currInsn, memaddr, info);
      return currInsn.size;
    }

  /* No match found.  */
  info->fprintf_func (info->stream,"%s ",ILLEGAL);
  return 2;
}

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Definition at line 265 of file d10v-dis.c.

{
  int status;
  bfd_byte buffer[4];
  unsigned long insn;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  insn = bfd_getb32 (buffer);

  status = insn & FM11;
  switch (status)
    {
    case 0:
      dis_2_short (insn, memaddr, info, 2);
      break;
    case FM01:
      dis_2_short (insn, memaddr, info, 0);
      break;
    case FM10:
      dis_2_short (insn, memaddr, info, 1);
      break;
    case FM11:
      dis_long (insn, memaddr, info);
      break;
    }
  return 4;
}

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Definition at line 320 of file d30v-dis.c.

{
  int status, result;
  bfd_byte buffer[12];
  unsigned long in1, in2;
  struct d30v_insn insn;
  long long num;

  insn.form = NULL;

  info->bytes_per_line = 8;
  info->bytes_per_chunk = 4;
  info->display_endian = BFD_ENDIAN_BIG;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  in1 = bfd_getb32 (buffer);

  status = (*info->read_memory_func) (memaddr + 4, buffer, 4, info);
  if (status != 0)
    {
      info->bytes_per_line = 8;
      if (!(result = lookup_opcode (&insn, in1, 0)))
       (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
       print_insn (info, memaddr, (long long) in1, &insn, 0, result);
      return 4;
    }
  in2 = bfd_getb32 (buffer);

  if (in1 & in2 & FM01)
    {
      /* LONG instruction.  */
      if (!(result = lookup_opcode (&insn, in1, 1)))
       {
         (*info->fprintf_func) (info->stream, ".long\t0x%lx,0x%lx", in1, in2);
         return 8;
       }
      num = (long long) in1 << 32 | in2;
      print_insn (info, memaddr, num, &insn, 1, result);
    }
  else
    {
      num = in1;
      if (!(result = lookup_opcode (&insn, in1, 0)))
       (*info->fprintf_func) (info->stream, ".long\t0x%lx", in1);
      else
       print_insn (info, memaddr, num, &insn, 0, result);

      switch (((in1 >> 31) << 1) | (in2 >> 31))
       {
       case 0:
         (*info->fprintf_func) (info->stream, "\t||\t");
         break;
       case 1:
         (*info->fprintf_func) (info->stream, "\t->\t");
         break;
       case 2:
         (*info->fprintf_func) (info->stream, "\t<-\t");
       default:
         break;
       }

      insn.form = NULL;
      num = in2;
      if (!(result = lookup_opcode (&insn, in2, 0)))
       (*info->fprintf_func) (info->stream, ".long\t0x%lx", in2);
      else
       print_insn (info, memaddr, num, &insn, 0, result);
    }
  return 8;
}

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Definition at line 433 of file dlx-dis.c.

{
  bfd_byte buffer[4];
  int insn_idx;
  unsigned long insn_word;
  unsigned char rtn_code;
  unsigned long dlx_insn_type[] =
  {
    (unsigned long) dlx_r_type,
    (unsigned long) dlx_load_type,
    (unsigned long) dlx_store_type,
    (unsigned long) dlx_aluI_type,
    (unsigned long) dlx_br_type,
    (unsigned long) dlx_jmp_type,
    (unsigned long) dlx_jr_type,
    (unsigned long) NULL
  };
  int dlx_insn_type_num = ((sizeof dlx_insn_type) / (sizeof (unsigned long))) - 1;
  int status =
    (*info->read_memory_func) (memaddr, (bfd_byte *) &buffer[0], 4, info);

  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  /* Now decode the insn    */
  insn_word = bfd_getb32 (buffer);
  opc  = dlx_get_opcode (insn_word);
  rs1  = dlx_get_rs1 (insn_word);
  rs2  = dlx_get_rs2 (insn_word);
  rd   = dlx_get_rdR (insn_word);
  func = dlx_get_func (insn_word);
  imm16= dlx_get_imm16 (insn_word);
  imm26= dlx_get_imm26 (insn_word);

#if 0
  printf ("print_insn_big_dlx: opc = 0x%02x\n"
         "                    rs1 = 0x%02x\n"
         "                    rs2 = 0x%02x\n"
         "                    rd  = 0x%02x\n"
         "                  func  = 0x%08x\n"
         "                 imm16  = 0x%08x\n"
         "                 imm26  = 0x%08x\n",
         opc, rs1, rs2, rd, func, imm16, imm26);
#endif

  /* Scan through all the insn type and print the insn out.  */
  rtn_code = 0;
  current_insn_addr = (unsigned long) memaddr;

  for (insn_idx = 0; dlx_insn_type[insn_idx] != 0x0; insn_idx++)
    switch (((dlx_insn) (dlx_insn_type[insn_idx])) (info))
      {
       /* Found the correct opcode   */
      case R_TYPE:
      case ILD_TYPE:
      case IST_TYPE:
      case IAL_TYPE:
      case IBR_TYPE:
      case IJ_TYPE:
      case IJR_TYPE:
       return 4;

       /* Wrong insn type check next one. */
      default:
      case NIL:
       continue;

       /* All rest of the return code are not recongnized, treat it as error */
       /* we should never get here,  I hope! */
      case R_ERROR:
       return -1;
      }

  if (insn_idx ==  dlx_insn_type_num)
    /* Well, does not recoganize this opcode.  */
    (*info->fprintf_func) (info->stream, "<%s>", "Unrecognized Opcode");

  return 4;
}

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Definition at line 617 of file fr30-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_fr30
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = fr30_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      fr30_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 714 of file frv-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_frv
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = frv_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      frv_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 723 of file h8300-dis.c.

{
  return bfd_h8_disassemble (addr, info, 0);
}

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Definition at line 729 of file h8300-dis.c.

{
  return bfd_h8_disassemble (addr, info, 1);
}

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Definition at line 735 of file h8300-dis.c.

{
  return bfd_h8_disassemble (addr, info, 2);
}

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Definition at line 75 of file h8500-dis.c.

{
  const h8500_opcode_info *opcode;
  void *stream = info->stream;
  fprintf_ftype func = info->fprintf_func;
  struct private priv;
  bfd_byte *buffer = priv.the_buffer;

  info->private_data = (PTR) & priv;
  priv.max_fetched = priv.the_buffer;
  priv.insn_start = addr;
  if (setjmp (priv.bailout) != 0)
    /* Error return.  */
    return -1;

  /* Run down the table to find the one which matches.  */
  for (opcode = h8500_table; opcode->name; opcode++)
    {
      int byte;
      int rn = 0;
      int rd = 0;
      int rs = 0;
      int disp = 0;
      int abs = 0;
      int imm = 0;
      int pcrel = 0;
      int qim = 0;
      int i;
      int cr = 0;

      for (byte = 0; byte < opcode->length; byte++)
       {
         FETCH_DATA (info, buffer + byte + 1);
         if ((buffer[byte] & opcode->bytes[byte].mask)
             != (opcode->bytes[byte].contents))
           goto next;

         else
           {
             /* Extract any info parts.  */
             switch (opcode->bytes[byte].insert)
              {
              case 0:
              case FP:
                break;
              default:
                /* xgettext:c-format */
                func (stream, _("can't cope with insert %d\n"),
                     opcode->bytes[byte].insert);
                break;
              case RN:
                rn = buffer[byte] & 0x7;
                break;
              case RS:
                rs = buffer[byte] & 0x7;
                break;
              case CRB:
                cr = buffer[byte] & 0x7;
                if (cr == 0)
                  goto next;
                break;
              case CRW:
                cr = buffer[byte] & 0x7;
                if (cr != 0)
                  goto next;
                break;
              case DISP16:
                FETCH_DATA (info, buffer + byte + 2);
                disp = (buffer[byte] << 8) | (buffer[byte + 1]);
                break;
              case FPIND_D8:
              case DISP8:
                disp = ((char) (buffer[byte]));
                break;
              case RD:
              case RDIND:
                rd = buffer[byte] & 0x7;
                break;
              case ABS24:
                FETCH_DATA (info, buffer + byte + 3);
                abs =
                  (buffer[byte] << 16)
                  | (buffer[byte + 1] << 8)
                  | (buffer[byte + 2]);
                break;
              case ABS16:
                FETCH_DATA (info, buffer + byte + 2);
                abs = (buffer[byte] << 8) | (buffer[byte + 1]);
                break;
              case ABS8:
                abs = (buffer[byte]);
                break;
              case IMM16:
                FETCH_DATA (info, buffer + byte + 2);
                imm = (buffer[byte] << 8) | (buffer[byte + 1]);
                break;
              case IMM4:
                imm = (buffer[byte]) & 0xf;
                break;
              case IMM8:
              case RLIST:
                imm = (buffer[byte]);
                break;
              case PCREL16:
                FETCH_DATA (info, buffer + byte + 2);
                pcrel = (buffer[byte] << 8) | (buffer[byte + 1]);
                break;
              case PCREL8:
                pcrel = (buffer[byte]);
                break;
              case QIM:
                switch (buffer[byte] & 0x7)
                  {
                  case 0:
                    qim = 1;
                    break;
                  case 1:
                    qim = 2;
                    break;
                  case 4:
                    qim = -1;
                    break;
                  case 5:
                    qim = -2;
                    break;
                  }
                break;

              }
           }
       }
      /* We get here when all the masks have passed so we can output
        the operands.  */
      FETCH_DATA (info, buffer + opcode->length);
      (func) (stream, "%s\t", opcode->name);
      for (i = 0; i < opcode->nargs; i++)
       {
         if (i)
           (func) (stream, ",");
         switch (opcode->arg_type[i])
           {
           case FP:
             func (stream, "fp");
             break;
           case RNIND_D16:
             func (stream, "@(0x%x:16,r%d)", disp, rn);
             break;
           case RNIND_D8:
             func (stream, "@(0x%x:8 (%d),r%d)", disp & 0xff, disp, rn);
             break;
           case RDIND_D16:
             func (stream, "@(0x%x:16,r%d)", disp, rd);
             break;
           case RDIND_D8:
             func (stream, "@(0x%x:8 (%d), r%d)", disp & 0xff, disp, rd);
             break;
           case FPIND_D8:
             func (stream, "@(0x%x:8 (%d), fp)", disp & 0xff, disp);
             break;
           case CRB:
           case CRW:
             func (stream, "%s", crname[cr]);
             break;
           case RN:
             func (stream, "r%d", rn);
             break;
           case RD:
             func (stream, "r%d", rd);
             break;
           case RS:
             func (stream, "r%d", rs);
             break;
           case RNDEC:
             func (stream, "@-r%d", rn);
             break;
           case RNINC:
             func (stream, "@r%d+", rn);
             break;
           case RNIND:
             func (stream, "@r%d", rn);
             break;
           case RDIND:
             func (stream, "@r%d", rd);
             break;
           case SPINC:
             func (stream, "@sp+");
             break;
           case SPDEC:
             func (stream, "@-sp");
             break;
           case ABS24:
             func (stream, "@0x%0x:24", abs);
             break;
           case ABS16:
             func (stream, "@0x%0x:16", abs & 0xffff);
             break;
           case ABS8:
             func (stream, "@0x%0x:8", abs & 0xff);
             break;
           case IMM16:
             func (stream, "#0x%0x:16", imm & 0xffff);
             break;
           case RLIST:
             {
              int i;
              int nc = 0;

              func (stream, "(");
              for (i = 0; i < 8; i++)
                {
                  if (imm & (1 << i))
                    {
                     func (stream, "r%d", i);
                     if (nc)
                       func (stream, ",");
                     nc = 1;
                    }
                }
              func (stream, ")");
             }
             break;
           case IMM8:
             func (stream, "#0x%0x:8", imm & 0xff);
             break;
           case PCREL16:
             func (stream, "0x%0x:16",
                  (int)(pcrel + addr + opcode->length) & 0xffff);
             break;
           case PCREL8:
             func (stream, "#0x%0x:8",
                  (int)((char) pcrel + addr + opcode->length) & 0xffff);
             break;
           case QIM:
             func (stream, "#%d:q", qim);
             break;
           case IMM4:
             func (stream, "#%d:4", imm);
             break;
           }
       }
      return opcode->length;
    next:
      ;
    }

  /* Couldn't understand anything.  */
  /* xgettext:c-format */
  func (stream, _("%02x\t\t*unknown*"), buffer[0]);
  return 1;
}

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Definition at line 357 of file hppa-dis.c.

{
  bfd_byte buffer[4];
  unsigned int insn, i;

  {
    int status =
      (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
    if (status != 0)
      {
       (*info->memory_error_func) (status, memaddr, info);
       return -1;
      }
  }

  insn = bfd_getb32 (buffer);

  for (i = 0; i < NUMOPCODES; ++i)
    {
      const struct pa_opcode *opcode = &pa_opcodes[i];

      if ((insn & opcode->mask) == opcode->match)
       {
         const char *s;
#ifndef BFD64
         if (opcode->arch == pa20w)
           continue;
#endif
         (*info->fprintf_func) (info->stream, "%s", opcode->name);

         if (!strchr ("cfCY?-+nHNZFIuv{", opcode->args[0]))
           (*info->fprintf_func) (info->stream, " ");
         for (s = opcode->args; *s != '\0'; ++s)
           {
             switch (*s)
              {
              case 'x':
                fput_reg (GET_FIELD (insn, 11, 15), info);
                break;
              case 'a':
              case 'b':
                fput_reg (GET_FIELD (insn, 6, 10), info);
                break;
              case '^':
                fput_creg (GET_FIELD (insn, 6, 10), info);
                break;
              case 't':
                fput_reg (GET_FIELD (insn, 27, 31), info);
                break;

                /* Handle floating point registers.  */
              case 'f':
                switch (*++s)
                  {
                  case 't':
                    fput_fp_reg (GET_FIELD (insn, 27, 31), info);
                    break;
                  case 'T':
                    if (GET_FIELD (insn, 25, 25))
                     fput_fp_reg_r (GET_FIELD (insn, 27, 31), info);
                    else
                     fput_fp_reg (GET_FIELD (insn, 27, 31), info);
                    break;
                  case 'a':
                    if (GET_FIELD (insn, 25, 25))
                     fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
                    else
                     fput_fp_reg (GET_FIELD (insn, 6, 10), info);
                    break;

                    /* 'fA' will not generate a space before the regsiter
                      name.  Normally that is fine.  Except that it
                      causes problems with xmpyu which has no FP format
                      completer.  */
                  case 'X':
                    fputs_filtered (" ", info);
                    /* FALLTHRU */

                  case 'A':
                    if (GET_FIELD (insn, 24, 24))
                     fput_fp_reg_r (GET_FIELD (insn, 6, 10), info);
                    else
                     fput_fp_reg (GET_FIELD (insn, 6, 10), info);
                    break;
                  case 'b':
                    if (GET_FIELD (insn, 25, 25))
                     fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
                    else
                     fput_fp_reg (GET_FIELD (insn, 11, 15), info);
                    break;
                  case 'B':
                    if (GET_FIELD (insn, 19, 19))
                     fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
                    else
                     fput_fp_reg (GET_FIELD (insn, 11, 15), info);
                    break;
                  case 'C':
                    {
                     int reg = GET_FIELD (insn, 21, 22);
                     reg |= GET_FIELD (insn, 16, 18) << 2;
                     if (GET_FIELD (insn, 23, 23) != 0)
                       fput_fp_reg_r (reg, info);
                     else
                       fput_fp_reg (reg, info);
                     break;
                    }
                  case 'i':
                    {
                     int reg = GET_FIELD (insn, 6, 10);

                     reg |= (GET_FIELD (insn, 26, 26) << 4);
                     fput_fp_reg (reg, info);
                     break;
                    }
                  case 'j':
                    {
                     int reg = GET_FIELD (insn, 11, 15);

                     reg |= (GET_FIELD (insn, 26, 26) << 4);
                     fput_fp_reg (reg, info);
                     break;
                    }
                  case 'k':
                    {
                     int reg = GET_FIELD (insn, 27, 31);

                     reg |= (GET_FIELD (insn, 26, 26) << 4);
                     fput_fp_reg (reg, info);
                     break;
                    }
                  case 'l':
                    {
                     int reg = GET_FIELD (insn, 21, 25);

                     reg |= (GET_FIELD (insn, 26, 26) << 4);
                     fput_fp_reg (reg, info);
                     break;
                    }
                  case 'm':
                    {
                     int reg = GET_FIELD (insn, 16, 20);

                     reg |= (GET_FIELD (insn, 26, 26) << 4);
                     fput_fp_reg (reg, info);
                     break;
                    }

                    /* 'fe' will not generate a space before the register
                      name.  Normally that is fine.  Except that it
                      causes problems with fstw fe,y(b) which has no FP
                      format completer.  */
                  case 'E':
                    fputs_filtered (" ", info);
                    /* FALLTHRU */

                  case 'e':
                    if (GET_FIELD (insn, 30, 30))
                     fput_fp_reg_r (GET_FIELD (insn, 11, 15), info);
                    else
                     fput_fp_reg (GET_FIELD (insn, 11, 15), info);
                    break;
                  case 'x':
                    fput_fp_reg (GET_FIELD (insn, 11, 15), info);
                    break;
                  }
                break;

              case '5':
                fput_const (extract_5_load (insn), info);
                break;
              case 's':
                {
                  int space = GET_FIELD (insn, 16, 17);
                  /* Zero means implicit addressing, not use of sr0.  */
                  if (space != 0)
                    (*info->fprintf_func) (info->stream, "sr%d", space);
                }
                break;

              case 'S':
                (*info->fprintf_func) (info->stream, "sr%d",
                                    extract_3 (insn));
                break;

                /* Handle completers.  */
              case 'c':
                switch (*++s)
                  {
                  case 'x':
                    (*info->fprintf_func)
                     (info->stream, "%s",
                      index_compl_names[GET_COMPL (insn)]);
                    break;
                  case 'X':
                    (*info->fprintf_func)
                     (info->stream, "%s ",
                      index_compl_names[GET_COMPL (insn)]);
                    break;
                  case 'm':
                    (*info->fprintf_func)
                     (info->stream, "%s",
                      short_ldst_compl_names[GET_COMPL (insn)]);
                    break;
                  case 'M':
                    (*info->fprintf_func)
                     (info->stream, "%s ",
                      short_ldst_compl_names[GET_COMPL (insn)]);
                    break;
                  case 'A':
                    (*info->fprintf_func)
                     (info->stream, "%s ",
                      short_bytes_compl_names[GET_COMPL (insn)]);
                    break;
                  case 's':
                    (*info->fprintf_func)
                     (info->stream, "%s",
                      short_bytes_compl_names[GET_COMPL (insn)]);
                    break;
                  case 'c':
                  case 'C':
                    switch (GET_FIELD (insn, 20, 21))
                     {
                     case 1:
                       (*info->fprintf_func) (info->stream, ",bc ");
                       break;
                     case 2:
                       (*info->fprintf_func) (info->stream, ",sl ");
                       break;
                     default:
                       (*info->fprintf_func) (info->stream, " ");
                     }
                    break;
                  case 'd':
                    switch (GET_FIELD (insn, 20, 21))
                     {
                     case 1:
                       (*info->fprintf_func) (info->stream, ",co ");
                       break;
                     default:
                       (*info->fprintf_func) (info->stream, " ");
                     }
                    break;
                  case 'o':
                    (*info->fprintf_func) (info->stream, ",o");
                    break;
                  case 'g':
                    (*info->fprintf_func) (info->stream, ",gate");
                    break;
                  case 'p':
                    (*info->fprintf_func) (info->stream, ",l,push");
                    break;
                  case 'P':
                    (*info->fprintf_func) (info->stream, ",pop");
                    break;
                  case 'l':
                  case 'L':
                    (*info->fprintf_func) (info->stream, ",l");
                    break;
                  case 'w':
                    (*info->fprintf_func)
                     (info->stream, "%s ",
                      read_write_names[GET_FIELD (insn, 25, 25)]);
                    break;
                  case 'W':
                    (*info->fprintf_func) (info->stream, ",w ");
                    break;
                  case 'r':
                    if (GET_FIELD (insn, 23, 26) == 5)
                     (*info->fprintf_func) (info->stream, ",r");
                    break;
                  case 'Z':
                    if (GET_FIELD (insn, 26, 26))
                     (*info->fprintf_func) (info->stream, ",m ");
                    else
                     (*info->fprintf_func) (info->stream, " ");
                    break;
                  case 'i':
                    if (GET_FIELD (insn, 25, 25))
                     (*info->fprintf_func) (info->stream, ",i");
                    break;
                  case 'z':
                    if (!GET_FIELD (insn, 21, 21))
                     (*info->fprintf_func) (info->stream, ",z");
                    break;
                  case 'a':
                    (*info->fprintf_func)
                     (info->stream, "%s",
                      add_compl_names[GET_FIELD (insn, 20, 21)]);
                    break;
                  case 'Y':
                    (*info->fprintf_func)
                     (info->stream, ",dc%s",
                      add_compl_names[GET_FIELD (insn, 20, 21)]);
                    break;
                  case 'y':
                    (*info->fprintf_func)
                     (info->stream, ",c%s",
                      add_compl_names[GET_FIELD (insn, 20, 21)]);
                    break;
                  case 'v':
                    if (GET_FIELD (insn, 20, 20))
                     (*info->fprintf_func) (info->stream, ",tsv");
                    break;
                  case 't':
                    (*info->fprintf_func) (info->stream, ",tc");
                    if (GET_FIELD (insn, 20, 20))
                     (*info->fprintf_func) (info->stream, ",tsv");
                    break;
                  case 'B':
                    (*info->fprintf_func) (info->stream, ",db");
                    if (GET_FIELD (insn, 20, 20))
                     (*info->fprintf_func) (info->stream, ",tsv");
                    break;
                  case 'b':
                    (*info->fprintf_func) (info->stream, ",b");
                    if (GET_FIELD (insn, 20, 20))
                     (*info->fprintf_func) (info->stream, ",tsv");
                    break;
                  case 'T':
                    if (GET_FIELD (insn, 25, 25))
                     (*info->fprintf_func) (info->stream, ",tc");
                    break;
                  case 'S':
                    /* EXTRD/W has a following condition.  */
                    if (*(s + 1) == '?')
                     (*info->fprintf_func)
                       (info->stream, "%s",
                        signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
                    else
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        signed_unsigned_names[GET_FIELD (insn, 21, 21)]);
                    break;
                  case 'h':
                    (*info->fprintf_func)
                     (info->stream, "%s",
                      mix_half_names[GET_FIELD (insn, 17, 17)]);
                    break;
                  case 'H':
                    (*info->fprintf_func)
                     (info->stream, "%s ",
                      saturation_names[GET_FIELD (insn, 24, 25)]);
                    break;
                  case '*':
                    (*info->fprintf_func)
                     (info->stream, ",%d%d%d%d ",
                      GET_FIELD (insn, 17, 18), GET_FIELD (insn, 20, 21),
                      GET_FIELD (insn, 22, 23), GET_FIELD (insn, 24, 25));
                    break;

                  case 'q':
                    {
                     int m, a;

                     m = GET_FIELD (insn, 28, 28);
                     a = GET_FIELD (insn, 29, 29);

                     if (m && !a)
                       fputs_filtered (",ma ", info);
                     else if (m && a)
                       fputs_filtered (",mb ", info);
                     else
                       fputs_filtered (" ", info);
                     break;
                    }

                  case 'J':
                    {
                     int opc = GET_FIELD (insn, 0, 5);

                     if (opc == 0x16 || opc == 0x1e)
                       {
                         if (GET_FIELD (insn, 29, 29) == 0)
                           fputs_filtered (",ma ", info);
                         else
                           fputs_filtered (",mb ", info);
                       }
                     else
                       fputs_filtered (" ", info);
                     break;
                    }

                  case 'e':
                    {
                     int opc = GET_FIELD (insn, 0, 5);

                     if (opc == 0x13 || opc == 0x1b)
                       {
                         if (GET_FIELD (insn, 18, 18) == 1)
                           fputs_filtered (",mb ", info);
                         else
                           fputs_filtered (",ma ", info);
                       }
                     else if (opc == 0x17 || opc == 0x1f)
                       {
                         if (GET_FIELD (insn, 31, 31) == 1)
                           fputs_filtered (",ma ", info);
                         else
                           fputs_filtered (",mb ", info);
                       }
                     else
                       fputs_filtered (" ", info);

                     break;
                    }
                  }
                break;

                /* Handle conditions.  */
              case '?':
                {
                  s++;
                  switch (*s)
                    {
                    case 'f':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        float_comp_names[GET_FIELD (insn, 27, 31)]);
                     break;

                     /* These four conditions are for the set of instructions
                        which distinguish true/false conditions by opcode
                        rather than by the 'f' bit (sigh): comb, comib,
                        addb, addib.  */
                    case 't':
                     fputs_filtered
                       (compare_cond_names[GET_FIELD (insn, 16, 18)], info);
                     break;
                    case 'n':
                     fputs_filtered
                       (compare_cond_names[GET_FIELD (insn, 16, 18)
                                         + GET_FIELD (insn, 4, 4) * 8],
                        info);
                     break;
                    case 'N':
                     fputs_filtered
                       (compare_cond_64_names[GET_FIELD (insn, 16, 18)
                                           + GET_FIELD (insn, 2, 2) * 8],
                        info);
                     break;
                    case 'Q':
                     fputs_filtered
                       (cmpib_cond_64_names[GET_FIELD (insn, 16, 18)],
                        info);
                     break;
                    case '@':
                     fputs_filtered
                       (add_cond_names[GET_FIELD (insn, 16, 18)
                                     + GET_FIELD (insn, 4, 4) * 8],
                        info);
                     break;
                    case 's':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        compare_cond_names[GET_COND (insn)]);
                     break;
                    case 'S':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        compare_cond_64_names[GET_COND (insn)]);
                     break;
                    case 'a':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        add_cond_names[GET_COND (insn)]);
                     break;
                    case 'A':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        add_cond_64_names[GET_COND (insn)]);
                     break;
                    case 'd':
                     (*info->fprintf_func)
                       (info->stream, "%s",
                        add_cond_names[GET_FIELD (insn, 16, 18)]);
                     break;

                    case 'W':
                     (*info->fprintf_func)
                       (info->stream, "%s",
                        wide_add_cond_names[GET_FIELD (insn, 16, 18) +
                                          GET_FIELD (insn, 4, 4) * 8]);
                     break;

                    case 'l':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        logical_cond_names[GET_COND (insn)]);
                     break;
                    case 'L':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        logical_cond_64_names[GET_COND (insn)]);
                     break;
                    case 'u':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        unit_cond_names[GET_COND (insn)]);
                     break;
                    case 'U':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        unit_cond_64_names[GET_COND (insn)]);
                     break;
                    case 'y':
                    case 'x':
                    case 'b':
                     (*info->fprintf_func)
                       (info->stream, "%s",
                        shift_cond_names[GET_FIELD (insn, 16, 18)]);

                     /* If the next character in args is 'n', it will handle
                        putting out the space.  */
                     if (s[1] != 'n')
                       (*info->fprintf_func) (info->stream, " ");
                     break;
                    case 'X':
                     (*info->fprintf_func)
                       (info->stream, "%s ",
                        shift_cond_64_names[GET_FIELD (insn, 16, 18)]);
                     break;
                    case 'B':
                     (*info->fprintf_func)
                       (info->stream, "%s",
                        bb_cond_64_names[GET_FIELD (insn, 16, 16)]);

                     /* If the next character in args is 'n', it will handle
                        putting out the space.  */
                     if (s[1] != 'n')
                       (*info->fprintf_func) (info->stream, " ");
                     break;
                    }
                  break;
                }

              case 'V':
                fput_const (extract_5_store (insn), info);
                break;
              case 'r':
                fput_const (extract_5r_store (insn), info);
                break;
              case 'R':
                fput_const (extract_5R_store (insn), info);
                break;
              case 'U':
                fput_const (extract_10U_store (insn), info);
                break;
              case 'B':
              case 'Q':
                fput_const (extract_5Q_store (insn), info);
                break;
              case 'i':
                fput_const (extract_11 (insn), info);
                break;
              case 'j':
                fput_const (extract_14 (insn), info);
                break;
              case 'k':
                fputs_filtered ("L%", info);
                fput_const (extract_21 (insn), info);
                break;
              case '<':
              case 'l':
                /* 16-bit long disp., PA2.0 wide only.  */
                fput_const (extract_16 (insn), info);
                break;
              case 'n':
                if (insn & 0x2)
                  (*info->fprintf_func) (info->stream, ",n ");
                else
                  (*info->fprintf_func) (info->stream, " ");
                break;
              case 'N':
                if ((insn & 0x20) && s[1])
                  (*info->fprintf_func) (info->stream, ",n ");
                else if (insn & 0x20)
                  (*info->fprintf_func) (info->stream, ",n");
                else if (s[1])
                  (*info->fprintf_func) (info->stream, " ");
                break;
              case 'w':
                (*info->print_address_func)
                  (memaddr + 8 + extract_12 (insn), info);
                break;
              case 'W':
                /* 17 bit PC-relative branch.  */
                (*info->print_address_func)
                  ((memaddr + 8 + extract_17 (insn)), info);
                break;
              case 'z':
                /* 17 bit displacement.  This is an offset from a register
                   so it gets disasssembled as just a number, not any sort
                   of address.  */
                fput_const (extract_17 (insn), info);
                break;

              case 'Z':
                /* addil %r1 implicit output.  */
                fputs_filtered ("r1", info);
                break;

              case 'Y':
                /* be,l %sr0,%r31 implicit output.  */
                fputs_filtered ("sr0,r31", info);
                break;

              case '@':
                (*info->fprintf_func) (info->stream, "0");
                break;

              case '.':
                (*info->fprintf_func) (info->stream, "%d",
                                    GET_FIELD (insn, 24, 25));
                break;
              case '*':
                (*info->fprintf_func) (info->stream, "%d",
                                    GET_FIELD (insn, 22, 25));
                break;
              case '!':
                fputs_filtered ("sar", info);
                break;
              case 'p':
                (*info->fprintf_func) (info->stream, "%d",
                                    31 - GET_FIELD (insn, 22, 26));
                break;
              case '~':
                {
                  int num;
                  num = GET_FIELD (insn, 20, 20) << 5;
                  num |= GET_FIELD (insn, 22, 26);
                  (*info->fprintf_func) (info->stream, "%d", 63 - num);
                  break;
                }
              case 'P':
                (*info->fprintf_func) (info->stream, "%d",
                                    GET_FIELD (insn, 22, 26));
                break;
              case 'q':
                {
                  int num;
                  num = GET_FIELD (insn, 20, 20) << 5;
                  num |= GET_FIELD (insn, 22, 26);
                  (*info->fprintf_func) (info->stream, "%d", num);
                  break;
                }
              case 'T':
                (*info->fprintf_func) (info->stream, "%d",
                                    32 - GET_FIELD (insn, 27, 31));
                break;
              case '%':
                {
                  int num;
                  num = (GET_FIELD (insn, 23, 23) + 1) * 32;
                  num -= GET_FIELD (insn, 27, 31);
                  (*info->fprintf_func) (info->stream, "%d", num);
                  break;
                }
              case '|':
                {
                  int num;
                  num = (GET_FIELD (insn, 19, 19) + 1) * 32;
                  num -= GET_FIELD (insn, 27, 31);
                  (*info->fprintf_func) (info->stream, "%d", num);
                  break;
                }
              case '$':
                fput_const (GET_FIELD (insn, 20, 28), info);
                break;
              case 'A':
                fput_const (GET_FIELD (insn, 6, 18), info);
                break;
              case 'D':
                fput_const (GET_FIELD (insn, 6, 31), info);
                break;
              case 'v':
                (*info->fprintf_func) (info->stream, ",%d",
                                    GET_FIELD (insn, 23, 25));
                break;
              case 'O':
                fput_const ((GET_FIELD (insn, 6,20) << 5 |
                            GET_FIELD (insn, 27, 31)), info);
                break;
              case 'o':
                fput_const (GET_FIELD (insn, 6, 20), info);
                break;
              case '2':
                fput_const ((GET_FIELD (insn, 6, 22) << 5 |
                            GET_FIELD (insn, 27, 31)), info);
                break;
              case '1':
                fput_const ((GET_FIELD (insn, 11, 20) << 5 |
                            GET_FIELD (insn, 27, 31)), info);
                break;
              case '0':
                fput_const ((GET_FIELD (insn, 16, 20) << 5 |
                            GET_FIELD (insn, 27, 31)), info);
                break;
              case 'u':
                (*info->fprintf_func) (info->stream, ",%d",
                                    GET_FIELD (insn, 23, 25));
                break;
              case 'F':
                /* If no destination completer and not before a completer
                   for fcmp, need a space here.  */
                if (s[1] == 'G' || s[1] == '?')
                  fputs_filtered
                    (float_format_names[GET_FIELD (insn, 19, 20)], info);
                else
                  (*info->fprintf_func)
                    (info->stream, "%s ",
                     float_format_names[GET_FIELD (insn, 19, 20)]);
                break;
              case 'G':
                (*info->fprintf_func)
                  (info->stream, "%s ",
                   float_format_names[GET_FIELD (insn, 17, 18)]);
                break;
              case 'H':
                if (GET_FIELD (insn, 26, 26) == 1)
                  (*info->fprintf_func) (info->stream, "%s ",
                                      float_format_names[0]);
                else
                  (*info->fprintf_func) (info->stream, "%s ",
                                      float_format_names[1]);
                break;
              case 'I':
                /* If no destination completer and not before a completer
                   for fcmp, need a space here.  */
                if (s[1] == '?')
                  fputs_filtered
                    (float_format_names[GET_FIELD (insn, 20, 20)], info);
                else
                  (*info->fprintf_func)
                    (info->stream, "%s ",
                     float_format_names[GET_FIELD (insn, 20, 20)]);
                break;

              case 'J':
                fput_const (extract_14 (insn), info);
                break;

              case '#':
                {
                  int sign = GET_FIELD (insn, 31, 31);
                  int imm10 = GET_FIELD (insn, 18, 27);
                  int disp;

                  if (sign)
                    disp = (-1 << 10) | imm10;
                  else
                    disp = imm10;

                  disp <<= 3;
                  fput_const (disp, info);
                  break;
                }
              case 'K':
              case 'd':
                {
                  int sign = GET_FIELD (insn, 31, 31);
                  int imm11 = GET_FIELD (insn, 18, 28);
                  int disp;

                  if (sign)
                    disp = (-1 << 11) | imm11;
                  else
                    disp = imm11;

                  disp <<= 2;
                  fput_const (disp, info);
                  break;
                }

              case '>':
              case 'y':
                {
                  /* 16-bit long disp., PA2.0 wide only.  */
                  int disp = extract_16 (insn);
                  disp &= ~3;
                  fput_const (disp, info);
                  break;
                }

              case '&':
                {
                  /* 16-bit long disp., PA2.0 wide only.  */
                  int disp = extract_16 (insn);
                  disp &= ~7;
                  fput_const (disp, info);
                  break;
                }

              case '_':
                break; /* Dealt with by '{' */

              case '{':
                {
                  int sub = GET_FIELD (insn, 14, 16);
                  int df = GET_FIELD (insn, 17, 18);
                  int sf = GET_FIELD (insn, 19, 20);
                  const char * const * source = float_format_names;
                  const char * const * dest = float_format_names;
                  char *t = "";

                  if (sub == 4)
                    {
                     fputs_filtered (",UND ", info);
                     break;
                    }
                  if ((sub & 3) == 3)
                    t = ",t";
                  if ((sub & 3) == 1)
                    source = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;
                  if (sub & 2)
                    dest = sub & 4 ? fcnv_ufixed_names : fcnv_fixed_names;

                  (*info->fprintf_func) (info->stream, "%s%s%s ",
                                      t, source[sf], dest[df]);
                  break;
                }

              case 'm':
                {
                  int y = GET_FIELD (insn, 16, 18);

                  if (y != 1)
                    fput_const ((y ^ 1) - 1, info);
                }
                break;

              case 'h':
                {
                  int cbit;

                  cbit = GET_FIELD (insn, 16, 18);

                  if (cbit > 0)
                    (*info->fprintf_func) (info->stream, ",%d", cbit - 1);
                  break;
                }

              case '=':
                {
                  int cond = GET_FIELD (insn, 27, 31);

                  switch (cond)
                    {
                    case  0: fputs_filtered (" ", info); break;
                    case  1: fputs_filtered ("acc ", info); break;
                    case  2: fputs_filtered ("rej ", info); break;
                    case  5: fputs_filtered ("acc8 ", info); break;
                    case  6: fputs_filtered ("rej8 ", info); break;
                    case  9: fputs_filtered ("acc6 ", info); break;
                    case 13: fputs_filtered ("acc4 ", info); break;
                    case 17: fputs_filtered ("acc2 ", info); break;
                    default: break;
                    }
                  break;
                }

              case 'X':
                (*info->print_address_func)
                  (memaddr + 8 + extract_22 (insn), info);
                break;
              case 'L':
                fputs_filtered (",rp", info);
                break;
              default:
                (*info->fprintf_func) (info->stream, "%c", *s);
                break;
              }
           }
         return sizeof (insn);
       }
    }
  (*info->fprintf_func) (info->stream, "#%8x", insn);
  return sizeof (insn);
}

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Definition at line 32 of file i370-dis.c.

{
  bfd_byte buffer[8];
  int status;
  i370_insn_t insn;
  const struct i370_opcode *opcode;
  const struct i370_opcode *opcode_end;

  status = (*info->read_memory_func) (memaddr, buffer, 6, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  /* Cast the bytes into the insn (in a host-endian indep way).  */
  insn.i[0] = (buffer[0] << 24) & 0xff000000;
  insn.i[0] |= (buffer[1] << 16) & 0xff0000;
  insn.i[0] |= (buffer[2] << 8) & 0xff00;
  insn.i[0] |= buffer[3]  & 0xff;
  insn.i[1] = (buffer[4] << 24) & 0xff000000;
  insn.i[1] |= (buffer[5] << 16) & 0xff0000;

  /* Find the first match in the opcode table.  We could speed this up
     a bit by doing a binary search on the major opcode.  */
  opcode_end = i370_opcodes + i370_num_opcodes;
  for (opcode = i370_opcodes; opcode < opcode_end; opcode++)
    {
      const unsigned char *opindex;
      const struct i370_operand *operand;
      i370_insn_t masked;
      int invalid;

      /* Mask off operands, and look for a match ... */
      masked = insn;
      if (2 == opcode->len)
        {
          masked.i[0] >>= 16;
          masked.i[0] &= 0xffff;
        }
      masked.i[0] &= opcode->mask.i[0];
      if (masked.i[0] != opcode->opcode.i[0])
       continue;

      if (6 == opcode->len)
        {
          masked.i[1] &= opcode->mask.i[1];
          if (masked.i[1] != opcode->opcode.i[1])
           continue;
        }

      /* Found a match.  adjust a tad.  */
      if (2 == opcode->len)
        {
          insn.i[0] >>= 16;
          insn.i[0] &= 0xffff;
        }

      /* Make two passes over the operands.  First see if any of them
         have extraction functions, and, if they do, make sure the
         instruction is valid.  */
      invalid = 0;
      for (opindex = opcode->operands; *opindex != 0; opindex++)
        {
          operand = i370_operands + *opindex;
          if (operand->extract)
            (*operand->extract) (insn, &invalid);
        }
      if (invalid)
       continue;

      /* The instruction is valid.  */
      (*info->fprintf_func) (info->stream, "%s", opcode->name);
      if (opcode->operands[0] != 0)
        (*info->fprintf_func) (info->stream, "\t");

      /* Now extract and print the operands.  */
      for (opindex = opcode->operands; *opindex != 0; opindex++)
        {
          long value;

          operand = i370_operands + *opindex;

          /* Extract the value from the instruction.  */
          if (operand->extract)
            value = (*operand->extract) (insn, (int *) NULL);
          else
           value = (insn.i[0] >> operand->shift) & ((1 << operand->bits) - 1);

          /* Print the operand as directed by the flags.  */
          if ((operand->flags & I370_OPERAND_OPTIONAL) != 0)
            {
              if (value)
                (*info->fprintf_func) (info->stream, "(r%ld)", value);
            }
          else if ((operand->flags & I370_OPERAND_SBASE) != 0)
            {
              (*info->fprintf_func) (info->stream, "(r%ld)", value);
            }
          else if ((operand->flags & I370_OPERAND_INDEX) != 0)
            {
              if (value)
                (*info->fprintf_func) (info->stream, "(r%ld,", value);
              else
                (*info->fprintf_func) (info->stream, "(,");
            }
          else if ((operand->flags & I370_OPERAND_LENGTH) != 0)
            {
              (*info->fprintf_func) (info->stream, "(%ld,", value);
            }
          else if ((operand->flags & I370_OPERAND_BASE) != 0)
            (*info->fprintf_func) (info->stream, "r%ld)", value);
          else if ((operand->flags & I370_OPERAND_GPR) != 0)
            (*info->fprintf_func) (info->stream, "r%ld,", value);
          else if ((operand->flags & I370_OPERAND_FPR) != 0)
            (*info->fprintf_func) (info->stream, "f%ld,", value);
          else if ((operand->flags & I370_OPERAND_RELATIVE) != 0)
            (*info->fprintf_func) (info->stream, "%ld", value);
          else
            (*info->fprintf_func) (info->stream, " %ld, ", value);
        }

      return opcode->len;
    }

  /* We could not find a match.  */
  (*info->fprintf_func) (info->stream, ".short 0x%02x%02x", buffer[0], buffer[1]);

  return 2;
}

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Definition at line 2851 of file i386-dis.c.

{
  intel_syntax = -1;

  return print_insn (pc, info);
}

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Definition at line 2835 of file i386-dis.c.

{
  intel_syntax = 0;

  return print_insn (pc, info);
}

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Definition at line 2843 of file i386-dis.c.

{
  intel_syntax = 1;

  return print_insn (pc, info);
}

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Definition at line 90 of file i860-dis.c.

{
  bfd_byte buff[4];
  unsigned int insn, i;
  int status;
  const struct i860_opcode *opcode = 0;

  status = (*info->read_memory_func) (memaddr, buff, sizeof (buff), info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  /* Note that i860 instructions are always accessed as little endian
     data, regardless of the endian mode of the i860.  */
  insn = bfd_getl32 (buff);

  status = 0;
  i = 0;
  while (i860_opcodes[i].name != NULL)
    {
      opcode = &i860_opcodes[i];
      if ((insn & opcode->match) == opcode->match
         && (insn & opcode->lose) == 0)
       {
         status = 1;
         break;
       }
      ++i;
    }

  if (status == 0)
    {
      /* Instruction not in opcode table.  */
      (*info->fprintf_func) (info->stream, ".long %#08x", insn);
    }
  else
    {
      const char *s;
      int val;

      /* If this a flop (or a shrd) and its dual bit is set,
         prefix with 'd.'.  */     
      if (((insn & 0xfc000000) == 0x48000000
           || (insn & 0xfc000000) == 0xb0000000)
          && (insn & 0x200))
       (*info->fprintf_func) (info->stream, "d.%s\t", opcode->name);
      else
       (*info->fprintf_func) (info->stream, "%s\t", opcode->name);

      for (s = opcode->args; *s; s++)
       {
         switch (*s)
           {
           /* Integer register (src1).  */
           case '1':
             (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
                                 grnames[(insn >> 11) & 0x1f]);
             break;

           /* Integer register (src2).  */
           case '2':
             (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
                                 grnames[(insn >> 21) & 0x1f]);
             break;

           /* Integer destination register.  */
           case 'd':
             (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
                                 grnames[(insn >> 16) & 0x1f]);
             break;

           /* Floating-point register (src1).  */
           case 'e':
             (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
                                 frnames[(insn >> 11) & 0x1f]);
             break;

           /* Floating-point register (src2).  */
           case 'f':
             (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
                                 frnames[(insn >> 21) & 0x1f]);
             break;

           /* Floating-point destination register.  */
           case 'g':
             (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
                                 frnames[(insn >> 16) & 0x1f]);
             break;

           /* Control register.  */
           case 'c':
             (*info->fprintf_func) (info->stream, "%s%s", I860_REG_PREFIX,
                                 crnames[(insn >> 21) & 0xf]);
             break;

           /* 16-bit immediate (sign extend, except for bitwise ops).  */
           case 'i':
             if (BITWISE_OP ((insn & 0xfc000000) >> 26))
              (*info->fprintf_func) (info->stream, "0x%04x",
                                   (unsigned int) (insn & 0xffff));
             else
              (*info->fprintf_func) (info->stream, "%d",
                                   sign_ext ((insn & 0xffff), 16));
             break;

           /* 16-bit immediate, aligned (2^0, ld.b).  */
           case 'I':
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext ((insn & 0xffff), 16));
             break;

           /* 16-bit immediate, aligned (2^1, ld.s).  */
           case 'J':
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext ((insn & 0xfffe), 16));
             break;

           /* 16-bit immediate, aligned (2^2, ld.l, {p}fld.l, fst.l).  */
           case 'K':
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext ((insn & 0xfffc), 16));
             break;

           /* 16-bit immediate, aligned (2^3, {p}fld.d, fst.d).  */
           case 'L':
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext ((insn & 0xfff8), 16));
             break;

           /* 16-bit immediate, aligned (2^4, {p}fld.q, fst.q).  */
           case 'M':
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext ((insn & 0xfff0), 16));
             break;

           /* 5-bit immediate (zero extend).  */
           case '5':
             (*info->fprintf_func) (info->stream, "%d",
                                 ((insn >> 11) & 0x1f));
             break;

           /* Split 16 bit immediate (20..16:10..0).  */
           case 's':
             val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext (val, 16));
             break;

           /* Split 16 bit immediate, aligned. (2^0, st.b).  */
           case 'S':
             val = ((insn >> 5) & 0xf800) | (insn & 0x07ff);
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext (val, 16));
             break;

           /* Split 16 bit immediate, aligned. (2^1, st.s).  */
           case 'T':
             val = ((insn >> 5) & 0xf800) | (insn & 0x07fe);
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext (val, 16));
             break;

           /* Split 16 bit immediate, aligned. (2^2, st.l).  */
           case 'U':
             val = ((insn >> 5) & 0xf800) | (insn & 0x07fc);
             (*info->fprintf_func) (info->stream, "%d",
                                 sign_ext (val, 16));
             break;

           /* 26-bit PC relative immediate (lbroff).  */
           case 'l':
             val = sign_ext ((insn & 0x03ffffff), 26);
             print_br_address (info, memaddr, val);
             break;

           /* 16-bit PC relative immediate (sbroff).  */
           case 'r':
             val = sign_ext ((((insn >> 5) & 0xf800) | (insn & 0x07ff)), 16);
             print_br_address (info, memaddr, val);
             break;

           default:
             (*info->fprintf_func) (info->stream, "%c", *s);
             break;
           }
       }
    }

  return sizeof (insn);
}

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Definition at line 51 of file i960-dis.c.

{
  unsigned int word1, word2 = 0xdeadbeef;
  bfd_byte buffer[8];
  int status;

  info = info_arg;
  stream = info->stream;

  /* Read word1.  Only read word2 if the instruction
     needs it, to prevent reading past the end of a section.  */

  status = (*info->read_memory_func) (memaddr, (bfd_byte *) buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  word1 = bfd_getl32 (buffer);

  /* Divide instruction set into classes based on high 4 bits of opcode.  */
  switch ( (word1 >> 28) & 0xf )
    {
    default:
      break;
    case 0x8:
    case 0x9:
    case 0xa:
    case 0xb:
    case 0xc:
      /* Read word2.  */
      status = (*info->read_memory_func)
       (memaddr + 4, (bfd_byte *) (buffer + 4), 4, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      word2 = bfd_getl32 (buffer + 4);
      break;
    }

  return pinsn( memaddr, word1, word2 );
}

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Definition at line 69 of file ia64-dis.c.

{
  ia64_insn t0, t1, slot[3], template, s_bit, insn;
  int slotnum, j, status, need_comma, retval, slot_multiplier;
  const struct ia64_operand *odesc;
  const struct ia64_opcode *idesc;
  const char *err, *str, *tname;
  BFD_HOST_U_64_BIT value;
  bfd_byte bundle[16];
  enum ia64_unit unit;
  char regname[16];

  if (info->bytes_per_line == 0)
    info->bytes_per_line = 6;
  info->display_endian = info->endian;

  slot_multiplier = info->bytes_per_line;
  retval = slot_multiplier;

  slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
  if (slotnum > 2)
    return -1;

  memaddr -= (memaddr & 0xf);
  status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  /* bundles are always in little-endian byte order */
  t0 = bfd_getl64 (bundle);
  t1 = bfd_getl64 (bundle + 8);
  s_bit = t0 & 1;
  template = (t0 >> 1) & 0xf;
  slot[0] = (t0 >>  5) & 0x1ffffffffffLL;
  slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
  slot[2] = (t1 >> 23) & 0x1ffffffffffLL;

  tname = ia64_templ_desc[template].name;
  if (slotnum == 0)
    (*info->fprintf_func) (info->stream, "[%s] ", tname);
  else
    (*info->fprintf_func) (info->stream, "      ");

  unit = ia64_templ_desc[template].exec_unit[slotnum];

  if (template == 2 && slotnum == 1)
    {
      /* skip L slot in MLI template: */
      slotnum = 2;
      retval += slot_multiplier;
    }

  insn = slot[slotnum];

  if (unit == IA64_UNIT_NIL)
    goto decoding_failed;

  idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
  if (idesc == NULL)
    goto decoding_failed;

  /* print predicate, if any: */

  if ((idesc->flags & IA64_OPCODE_NO_PRED)
      || (insn & 0x3f) == 0)
    (*info->fprintf_func) (info->stream, "      ");
  else
    (*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));

  /* now the actual instruction: */

  (*info->fprintf_func) (info->stream, "%s", idesc->name);
  if (idesc->operands[0])
    (*info->fprintf_func) (info->stream, " ");

  need_comma = 0;
  for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
    {
      odesc = elf64_ia64_operands + idesc->operands[j];

      if (need_comma)
       (*info->fprintf_func) (info->stream, ",");

      if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
       {
         /* special case of 64 bit immediate load: */
         value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
           | (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
           | (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
       }
      else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
        {
          /* 62-bit immediate for nop.x/break.x */
          value = ((slot[1] & 0x1ffffffffffLL) << 21)
            | (((insn >> 36) & 0x1) << 20)
            | ((insn >> 6) & 0xfffff);
        }
      else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
       {
         /* 60-bit immediate for long branches. */
         value = (((insn >> 13) & 0xfffff)
                 | (((insn >> 36) & 1) << 59)
                 | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4;
       }
      else
       {
         err = (*odesc->extract) (odesc, insn, &value);
         if (err)
           {
             (*info->fprintf_func) (info->stream, "%s", err);
             goto done;
           }
       }

       switch (odesc->class)
         {
         case IA64_OPND_CLASS_CST:
           (*info->fprintf_func) (info->stream, "%s", odesc->str);
           break;

         case IA64_OPND_CLASS_REG:
           if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
             {
              switch (value)
                {
                case 0: case 1: case 2: case 3:
                case 4: case 5: case 6: case 7:
                  sprintf (regname, "ar.k%u", (unsigned int) value);
                  break;
                case 16:    strcpy (regname, "ar.rsc"); break;
                case 17:    strcpy (regname, "ar.bsp"); break;
                case 18:    strcpy (regname, "ar.bspstore"); break;
                case 19:    strcpy (regname, "ar.rnat"); break;
                case 32:    strcpy (regname, "ar.ccv"); break;
                case 36:    strcpy (regname, "ar.unat"); break;
                case 40:    strcpy (regname, "ar.fpsr"); break;
                case 44:    strcpy (regname, "ar.itc"); break;
                case 64:    strcpy (regname, "ar.pfs"); break;
                case 65:    strcpy (regname, "ar.lc"); break;
                case 66:    strcpy (regname, "ar.ec"); break;
                default:
                  sprintf (regname, "ar%u", (unsigned int) value);
                  break;
                }
              (*info->fprintf_func) (info->stream, "%s", regname);
             }
           else
             (*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
           break;

         case IA64_OPND_CLASS_IND:
           (*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
           break;

         case IA64_OPND_CLASS_ABS:
           str = 0;
           if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
             switch (value)
              {
              case 0x0: str = "@brcst"; break;
              case 0x8: str = "@mix"; break;
              case 0x9: str = "@shuf"; break;
              case 0xa: str = "@alt"; break;
              case 0xb: str = "@rev"; break;
              }

           if (str)
             (*info->fprintf_func) (info->stream, "%s", str);
           else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
             (*info->fprintf_func) (info->stream, "%lld", (long long) value);
           else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
             (*info->fprintf_func) (info->stream, "%llu", (long long) value);
           else
             (*info->fprintf_func) (info->stream, "0x%llx", (long long) value);
           break;

         case IA64_OPND_CLASS_REL:
           (*info->print_address_func) (memaddr + value, info);
           break;
         }

      need_comma = 1;
      if (j + 1 == idesc->num_outputs)
       {
         (*info->fprintf_func) (info->stream, "=");
         need_comma = 0;
       }
    }
  if (slotnum + 1 == ia64_templ_desc[template].group_boundary 
      || ((slotnum == 2) && s_bit))
    (*info->fprintf_func) (info->stream, ";;");

 done:
  ia64_free_opcode ((struct ia64_opcode *)idesc);
 failed:
  if (slotnum == 2)
    retval += 16 - 3*slot_multiplier;
  return retval;

 decoding_failed:
  (*info->fprintf_func) (info->stream, "      data8 %#011llx", (long long) insn);
  goto failed;
}

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Definition at line 606 of file ip2k-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_ip2k
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = ip2k_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      ip2k_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 507 of file iq2000-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_iq2000
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      iq2000_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 4184 of file arm-dis.c.

{
  return print_insn (pc, info, TRUE);
}

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Definition at line 2039 of file mips-dis.c.

{
  return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
}

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Definition at line 320 of file or32-dis.c.

{
  info->private_data = find_bytes_little;
  return print_insn (memaddr, info);
}

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Definition at line 116 of file ppc-dis.c.

{
  int dialect = (char *) info->private_data - (char *) 0;
  return print_insn_powerpc (memaddr, info, 0, dialect);
}

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Definition at line 501 of file score-dis.c.

{
  return print_insn (pc, info, TRUE);
}

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Definition at line 1209 of file m32c-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_m32c
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      m32c_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 574 of file m32r-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_m32r
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      m32r_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 730 of file m68hc11-dis.c.

{
  return print_insn (memaddr, info, cpu6811);
}

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Definition at line 736 of file m68hc11-dis.c.

{
  return print_insn (memaddr, info, cpu6812);
}

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Definition at line 1470 of file m68k-dis.c.

{
  unsigned int arch_mask;
  struct private priv;
  int val;

  bfd_byte *buffer = priv.the_buffer;

  info->private_data = (PTR) &priv;
  /* Tell objdump to use two bytes per chunk
     and six bytes per line for displaying raw data.  */
  info->bytes_per_chunk = 2;
  info->bytes_per_line = 6;
  info->display_endian = BFD_ENDIAN_BIG;
  priv.max_fetched = priv.the_buffer;
  priv.insn_start = memaddr;

  if (setjmp (priv.bailout) != 0)
    /* Error return.  */
    return -1;

  arch_mask = bfd_m68k_mach_to_features (info->mach);
  if (!arch_mask)
    {
      /* First try printing an m680x0 instruction.  Try printing a Coldfire
        one if that fails.  */
      val = m68k_scan_mask (memaddr, info, m68k_mask);
      if (val)
       return val;

      val = m68k_scan_mask (memaddr, info, mcf_mask);
      if (val)
       return val;
    }
  else
    {
      val = m68k_scan_mask (memaddr, info, arch_mask);
      if (val)
       return val;
    }

  /* Handle undefined instructions.  */
  info->fprintf_func (info->stream, "0%o", (buffer[0] << 8) + buffer[1]);
  return 2;
}

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Definition at line 747 of file m88k-dis.c.

{
  bfd_byte buffer[4];
  int status;

  /* Instruction addresses may have low two bits set. Clear them.  */
  memaddr &=~ (bfd_vma) 3;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  return m88kdis (memaddr, bfd_getb32 (buffer), info);
}

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Definition at line 714 of file maxq-dis.c.

{
  return print_insn (memaddr, info, BFD_ENDIAN_LITTLE);
}

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Definition at line 88 of file mcore-dis.c.

{
  unsigned char ibytes[4];
  fprintf_ftype fprintf = info->fprintf_func;
  void *stream = info->stream;
  unsigned short inst;
  const mcore_opcode_info *op;
  int status;

  info->bytes_per_chunk = 2;

  status = info->read_memory_func (memaddr, ibytes, 2, info);

  if (status != 0)
    {
      info->memory_error_func (status, memaddr, info);
      return -1;
    }

  if (info->endian == BFD_ENDIAN_BIG)
    inst = (ibytes[0] << 8) | ibytes[1];
  else if (info->endian == BFD_ENDIAN_LITTLE)
    inst = (ibytes[1] << 8) | ibytes[0];
  else
    abort ();

  /* Just a linear search of the table.  */
  for (op = mcore_table; op->name != 0; op++)
    if (op->inst == (inst & imsk[op->opclass]))
      break;

  if (op->name == 0)
    fprintf (stream, ".short 0x%04x", inst);
  else
    {
      const char *name = grname[inst & 0x0F];

      fprintf (stream, "%s", op->name);

      switch (op->opclass)
       {
       case O0:
         break;

       case OT:
         fprintf (stream, "\t%d", inst & 0x3);
         break;

       case O1:
       case JMP:
       case JSR:
         fprintf (stream, "\t%s", name);
         break;

       case OC:
         fprintf (stream, "\t%s, %s", name, crname[(inst >> 4) & 0x1F]);
         break;

       case O1R1:
         fprintf (stream, "\t%s, r1", name);
         break;

       case MULSH:
       case O2:
         fprintf (stream, "\t%s, %s", name, grname[(inst >> 4) & 0xF]);
         break;

       case X1:
         fprintf (stream, "\tr1, %s", name);
         break;

       case OI:
         fprintf (stream, "\t%s, %d", name, ((inst >> 4) & 0x1F) + 1);
         break;

       case RM:
         fprintf (stream, "\t%s-r15, (r0)", name);
         break;

       case RQ:
         fprintf (stream, "\tr4-r7, (%s)", name);
         break;

       case OB:
       case OBRa:
       case OBRb:
       case OBRc:
       case SI:
       case SIa:
       case OMa:
       case OMb:
       case OMc:
         fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x1F);
         break;

       case I7:
         fprintf (stream, "\t%s, %d", name, (inst >> 4) & 0x7F);
         break;

       case LS:
         fprintf (stream, "\t%s, (%s, %d)", grname[(inst >> 8) & 0xF],
                 name, ((inst >> 4) & 0xF) << isiz[(inst >> 13) & 3]);
         break;

       case BR:
         {
           long val = inst & 0x3FF;

           if (inst & 0x400)
             val |= 0xFFFFFC00;

           fprintf (stream, "\t0x%lx", (long)(memaddr + 2 + (val << 1)));

           if (strcmp (op->name, "bsr") == 0)
             {
              /* For bsr, we'll try to get a symbol for the target.  */
              val = memaddr + 2 + (val << 1);

              if (info->print_address_func && val != 0)
                {
                  fprintf (stream, "\t// ");
                  info->print_address_func (val, info);
                }
             }
         }
         break;

       case BL:
         {
           long val;
           val = (inst & 0x000F);
           fprintf (stream, "\t%s, 0x%lx",
                   grname[(inst >> 4) & 0xF], (long)(memaddr - (val << 1)));
         }
         break;

       case LR:
         {
           unsigned long val;

           val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;

           status = info->read_memory_func (val, ibytes, 4, info);
           if (status != 0)
             {
              info->memory_error_func (status, memaddr, info);
              break;
             }

           if (info->endian == BFD_ENDIAN_LITTLE)
             val = (ibytes[3] << 24) | (ibytes[2] << 16)
              | (ibytes[1] << 8) | (ibytes[0]);
           else
             val = (ibytes[0] << 24) | (ibytes[1] << 16)
              | (ibytes[2] << 8) | (ibytes[3]);

           /* Removed [] around literal value to match ABI syntax 12/95.  */
           fprintf (stream, "\t%s, 0x%lX", grname[(inst >> 8) & 0xF], val);

           if (val == 0)
             fprintf (stream, "\t// from address pool at 0x%lx",
                     (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
         }
         break;

       case LJ:
         {
           unsigned long val;

           val = (memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC;

           status = info->read_memory_func (val, ibytes, 4, info);
           if (status != 0)
             {
              info->memory_error_func (status, memaddr, info);
              break;
             }

           if (info->endian == BFD_ENDIAN_LITTLE)
             val = (ibytes[3] << 24) | (ibytes[2] << 16)
              | (ibytes[1] << 8) | (ibytes[0]);
           else
             val = (ibytes[0] << 24) | (ibytes[1] << 16)
              | (ibytes[2] << 8) | (ibytes[3]);

           /* Removed [] around literal value to match ABI syntax 12/95.  */
           fprintf (stream, "\t0x%lX", val);
           /* For jmpi/jsri, we'll try to get a symbol for the target.  */
           if (info->print_address_func && val != 0)
             {
              fprintf (stream, "\t// ");
              info->print_address_func (val, info);
             }
           else
             {
              fprintf (stream, "\t// from address pool at 0x%lx",
                      (long)(memaddr + 2 + ((inst & 0xFF) << 2)) & 0xFFFFFFFC);
             }
         }
         break;

       case OPSR:
         {
           static char *fields[] = {
             "af", "ie",    "fe",    "fe,ie",
             "ee", "ee,ie", "ee,fe", "ee,fe,ie"
           };

           fprintf (stream, "\t%s", fields[inst & 0x7]);
         }
         break;

       default:
         /* If the disassembler lags the instruction set.  */
         fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
         break;
       }
    }

  /* Say how many bytes we consumed.  */
  return 2;
}

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Definition at line 1094 of file mep-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_mep
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      mep_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 247 of file mmix-dis.c.

{
  unsigned char buffer[4];
  unsigned long insn;
  unsigned int x, y, z;
  const struct mmix_opcode *opcodep;
  int status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  struct mmix_dis_info *minfop;

  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  /* FIXME: Is -1 suitable?  */
  if (info->private_data == NULL
      && ! initialize_mmix_dis_info (info))
    return -1;

  minfop = (struct mmix_dis_info *) info->private_data;
  x = buffer[1];
  y = buffer[2];
  z = buffer[3];

  insn = bfd_getb32 (buffer);

  opcodep = get_opcode (insn);

  if (opcodep == NULL)
    {
      (*info->fprintf_func) (info->stream, _("*unknown*"));
      return 4;
    }

  (*info->fprintf_func) (info->stream, "%s ", opcodep->name);

  /* Present bytes in the order they are laid out in memory.  */
  info->display_endian = BFD_ENDIAN_BIG;

  info->insn_info_valid = 1;
  info->bytes_per_chunk = 4;
  info->branch_delay_insns = 0;
  info->target = 0;
  switch (opcodep->type)
    {
    case mmix_type_normal:
    case mmix_type_memaccess_block:
      info->insn_type = dis_nonbranch;
      break;

    case mmix_type_branch:
      info->insn_type = dis_branch;
      break;

    case mmix_type_condbranch:
      info->insn_type = dis_condbranch;
      break;

    case mmix_type_memaccess_octa:
      info->insn_type = dis_dref;
      info->data_size = 8;
      break;

    case mmix_type_memaccess_tetra:
      info->insn_type = dis_dref;
      info->data_size = 4;
      break;

    case mmix_type_memaccess_wyde:
      info->insn_type = dis_dref;
      info->data_size = 2;
      break;

    case mmix_type_memaccess_byte:
      info->insn_type = dis_dref;
      info->data_size = 1;
      break;

    case mmix_type_jsr:
      info->insn_type = dis_jsr;
      break;

    default:
      BAD_CASE(opcodep->type);
    }

  switch (opcodep->operands)
    {
    case mmix_operands_regs:
      /*  All registers: "$X,$Y,$Z".  */
      (*info->fprintf_func) (info->stream, "%s,%s,%s",
                          minfop->reg_name[x],
                          minfop->reg_name[y],
                          minfop->reg_name[z]);
      break;

    case mmix_operands_reg_yz:
      /* Like SETH - "$X,YZ".  */
      (*info->fprintf_func) (info->stream, "%s,0x%x",
                          minfop->reg_name[x], y * 256 + z);
      break;

    case mmix_operands_regs_z_opt:
    case mmix_operands_regs_z:
    case mmix_operands_pushgo:
      /* The regular "$X,$Y,$Z|Z".  */
      if (insn & INSN_IMMEDIATE_BIT)
       (*info->fprintf_func) (info->stream, "%s,%s,%d",
                            minfop->reg_name[x], minfop->reg_name[y], z);
      else
       (*info->fprintf_func) (info->stream, "%s,%s,%s",
                            minfop->reg_name[x],
                            minfop->reg_name[y],
                            minfop->reg_name[z]);
      break;

    case mmix_operands_jmp:
      /* Address; only JMP.  */
      {
       bfd_signed_vma offset = (x * 65536 + y * 256 + z) * 4;

       if (insn & INSN_BACKWARD_OFFSET_BIT)
         offset -= (256 * 65536) * 4;

       info->target = memaddr + offset;
       (*info->print_address_func) (memaddr + offset, info);
      }
      break;

    case mmix_operands_roundregs_z:
      /* Two registers, like FLOT, possibly with rounding: "$X,$Z|Z"
        "$X,ROUND_MODE,$Z|Z".  */
      if (y != 0)
       {
         if (insn & INSN_IMMEDIATE_BIT)
           (*info->fprintf_func) (info->stream, "%s,%s,%d",
                               minfop->reg_name[x],
                               ROUND_MODE (y), z);
         else
           (*info->fprintf_func) (info->stream, "%s,%s,%s",
                               minfop->reg_name[x],
                               ROUND_MODE (y),
                               minfop->reg_name[z]);
       }
      else
       {
         if (insn & INSN_IMMEDIATE_BIT)
           (*info->fprintf_func) (info->stream, "%s,%d",
                               minfop->reg_name[x], z);
         else
           (*info->fprintf_func) (info->stream, "%s,%s",
                               minfop->reg_name[x],
                               minfop->reg_name[z]);
       }
      break;

    case mmix_operands_pop:
      /* Like POP - "X,YZ".  */
      (*info->fprintf_func) (info->stream, "%d,%d", x, y*256 + z);
      break;

    case mmix_operands_roundregs:
      /* Two registers, possibly with rounding: "$X,$Z" or
        "$X,ROUND_MODE,$Z".  */
      if (y != 0)
       (*info->fprintf_func) (info->stream, "%s,%s,%s",
                            minfop->reg_name[x],
                            ROUND_MODE (y),
                            minfop->reg_name[z]);
      else
       (*info->fprintf_func) (info->stream, "%s,%s",
                            minfop->reg_name[x],
                            minfop->reg_name[z]);
      break;

    case mmix_operands_sync:
       /* Like SYNC - "XYZ".  */
      (*info->fprintf_func) (info->stream, "%u",
                          x * 65536 + y * 256 + z);
      break;

    case mmix_operands_x_regs_z:
      /* Like SYNCD - "X,$Y,$Z|Z".  */
      if (insn & INSN_IMMEDIATE_BIT)
       (*info->fprintf_func) (info->stream, "%d,%s,%d",
                            x, minfop->reg_name[y], z);
      else
       (*info->fprintf_func) (info->stream, "%d,%s,%s",
                            x, minfop->reg_name[y],
                            minfop->reg_name[z]);
      break;

    case mmix_operands_neg:
      /* Like NEG and NEGU - "$X,Y,$Z|Z".  */
      if (insn & INSN_IMMEDIATE_BIT)
       (*info->fprintf_func) (info->stream, "%s,%d,%d",
                            minfop->reg_name[x], y, z);
      else
       (*info->fprintf_func) (info->stream, "%s,%d,%s",
                            minfop->reg_name[x], y,
                            minfop->reg_name[z]);
      break;

    case mmix_operands_pushj:
    case mmix_operands_regaddr:
      /* Like GETA or branches - "$X,Address".  */
      {
       bfd_signed_vma offset = (y * 256 + z) * 4;

       if (insn & INSN_BACKWARD_OFFSET_BIT)
         offset -= 65536 * 4;

       info->target = memaddr + offset;

       (*info->fprintf_func) (info->stream, "%s,", minfop->reg_name[x]);
       (*info->print_address_func) (memaddr + offset, info);
      }
      break;

    case mmix_operands_get:
      /* GET - "X,spec_reg".  */
      (*info->fprintf_func) (info->stream, "%s,%s",
                          minfop->reg_name[x],
                          minfop->spec_reg_name[z]);
      break;

    case mmix_operands_put:
      /* PUT - "spec_reg,$Z|Z".  */
      if (insn & INSN_IMMEDIATE_BIT)
       (*info->fprintf_func) (info->stream, "%s,%d",
                            minfop->spec_reg_name[x], z);
      else
       (*info->fprintf_func) (info->stream, "%s,%s",
                            minfop->spec_reg_name[x],
                            minfop->reg_name[z]);
      break;

    case mmix_operands_set:
      /*  Two registers, "$X,$Y".  */
      (*info->fprintf_func) (info->stream, "%s,%s",
                          minfop->reg_name[x],
                          minfop->reg_name[y]);
      break;

    case mmix_operands_save:
      /* SAVE - "$X,0".  */
      (*info->fprintf_func) (info->stream, "%s,0", minfop->reg_name[x]);
      break;

    case mmix_operands_unsave:
      /* UNSAVE - "0,$Z".  */
      (*info->fprintf_func) (info->stream, "0,%s", minfop->reg_name[z]);
      break;

    case mmix_operands_xyz_opt:
      /* Like SWYM or TRAP - "X,Y,Z".  */
      (*info->fprintf_func) (info->stream, "%d,%d,%d", x, y, z);
      break;

    case mmix_operands_resume:
      /* Just "Z", like RESUME.  */
      (*info->fprintf_func) (info->stream, "%d", z);
      break;

    default:
      (*info->fprintf_func) (info->stream, _("*unknown operands type: %d*"),
                          opcodep->operands);
      break;
    }

  return 4;
}

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Definition at line 160 of file m10200-dis.c.

{
  int status;
  bfd_byte buffer[4];
  unsigned long insn;
  unsigned long extension = 0;
  unsigned int consume;

  /* First figure out how big the opcode is.  */
  status = (*info->read_memory_func) (memaddr, buffer, 1, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  insn = *(unsigned char *) buffer;

  /* These are one byte insns.  */
  if ((insn & 0xf0) == 0x00
      || (insn & 0xf0) == 0x10
      || (insn & 0xf0) == 0x20
      || (insn & 0xf0) == 0x30
      || ((insn & 0xf0) == 0x80
         && (insn & 0x0c) >> 2 != (insn & 0x03))
      || (insn & 0xf0) == 0x90
      || (insn & 0xf0) == 0xa0
      || (insn & 0xf0) == 0xb0
      || (insn & 0xff) == 0xeb
      || (insn & 0xff) == 0xf6
      || (insn & 0xff) == 0xfe
      || (insn & 0xff) == 0xff)
    {
      extension = 0;
      consume = 1;
    }

  /* These are two byte insns.  */
  else if ((insn & 0xf0) == 0x40
          || (insn & 0xf0) == 0x50
          || (insn & 0xf0) == 0x60
          || (insn & 0xf0) == 0x70
          || (insn & 0xf0) == 0x80
          || (insn & 0xfc) == 0xd0
          || (insn & 0xfc) == 0xd4
          || (insn & 0xfc) == 0xd8
          || (insn & 0xfc) == 0xe0
          || (insn & 0xfc) == 0xe4
          || (insn & 0xff) == 0xe8
          || (insn & 0xff) == 0xe9
          || (insn & 0xff) == 0xea
          || (insn & 0xff) == 0xf0
          || (insn & 0xff) == 0xf1
          || (insn & 0xff) == 0xf2
          || (insn & 0xff) == 0xf3)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
          return -1;
       }
      insn = bfd_getb16 (buffer);
      consume = 2;
    }

  /* These are three byte insns with a 16bit operand in little
     endian form.  */
  else if ((insn & 0xf0) == 0xc0
          || (insn & 0xfc) == 0xdc
          || (insn & 0xfc) == 0xec
          || (insn & 0xff) == 0xf8
          || (insn & 0xff) == 0xf9
          || (insn & 0xff) == 0xfa
          || (insn & 0xff) == 0xfb
          || (insn & 0xff) == 0xfc
          || (insn & 0xff) == 0xfd)
    {
      status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn <<= 16;
      insn |= bfd_getl16 (buffer);
      extension = 0;
      consume = 3;
    }
  /* These are three byte insns too, but we don't have to mess with
     endianness stuff.  */
  else if ((insn & 0xff) == 0xf5)
    {
      status = (*info->read_memory_func) (memaddr + 1, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn <<= 16;
      insn |= bfd_getb16 (buffer);
      extension = 0;
      consume = 3;
    }

  /* These are four byte insns.  */
  else if ((insn & 0xff) == 0xf7)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn = bfd_getb16 (buffer);
      insn <<= 16;
      status = (*info->read_memory_func) (memaddr + 2, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn |= bfd_getl16 (buffer);
      extension = 0;
      consume = 4;
    }

  /* These are five byte insns.  */
  else if ((insn & 0xff) == 0xf4)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn = bfd_getb16 (buffer);
      insn <<= 16;

      status = (*info->read_memory_func) (memaddr + 4, buffer, 1, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn |= (*(unsigned char *)buffer << 8) & 0xff00;

      status = (*info->read_memory_func) (memaddr + 3, buffer, 1, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn |= (*(unsigned char *)buffer) & 0xff;

      status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      extension = (*(unsigned char *)buffer) & 0xff;
      consume = 5;
    }
  else
    {
      (*info->fprintf_func) (info->stream, _("unknown\t0x%02lx"), insn);
      return 1;
    }

  disassemble (memaddr, info, insn, extension, consume);

  return consume;
}

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Definition at line 584 of file m10300-dis.c.

{
  int status;
  bfd_byte buffer[4];
  unsigned long insn;
  unsigned int consume;

  /* First figure out how big the opcode is.  */
  status = (*info->read_memory_func) (memaddr, buffer, 1, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }
  insn = *(unsigned char *) buffer;

  /* These are one byte insns.  */
  if ((insn & 0xf3) == 0x00
      || (insn & 0xf0) == 0x10
      || (insn & 0xfc) == 0x3c
      || (insn & 0xf3) == 0x41
      || (insn & 0xf3) == 0x40
      || (insn & 0xfc) == 0x50
      || (insn & 0xfc) == 0x54
      || (insn & 0xf0) == 0x60
      || (insn & 0xf0) == 0x70
      || ((insn & 0xf0) == 0x80
         && (insn & 0x0c) >> 2 != (insn & 0x03))
      || ((insn & 0xf0) == 0x90
         && (insn & 0x0c) >> 2 != (insn & 0x03))
      || ((insn & 0xf0) == 0xa0
         && (insn & 0x0c) >> 2 != (insn & 0x03))
      || ((insn & 0xf0) == 0xb0
         && (insn & 0x0c) >> 2 != (insn & 0x03))
      || (insn & 0xff) == 0xcb
      || (insn & 0xfc) == 0xd0
      || (insn & 0xfc) == 0xd4
      || (insn & 0xfc) == 0xd8
      || (insn & 0xf0) == 0xe0
      || (insn & 0xff) == 0xff)
    {
      consume = 1;
    }

  /* These are two byte insns.  */
  else if ((insn & 0xf0) == 0x80
          || (insn & 0xf0) == 0x90
          || (insn & 0xf0) == 0xa0
          || (insn & 0xf0) == 0xb0
          || (insn & 0xfc) == 0x20
          || (insn & 0xfc) == 0x28
          || (insn & 0xf3) == 0x43
          || (insn & 0xf3) == 0x42
          || (insn & 0xfc) == 0x58
          || (insn & 0xfc) == 0x5c
          || ((insn & 0xf0) == 0xc0
              && (insn & 0xff) != 0xcb
              && (insn & 0xff) != 0xcc
              && (insn & 0xff) != 0xcd)
          || (insn & 0xff) == 0xf0
          || (insn & 0xff) == 0xf1
          || (insn & 0xff) == 0xf2
          || (insn & 0xff) == 0xf3
          || (insn & 0xff) == 0xf4
          || (insn & 0xff) == 0xf5
          || (insn & 0xff) == 0xf6)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn = bfd_getb16 (buffer);
      consume = 2;
    }

  /* These are three byte insns.  */
  else if ((insn & 0xff) == 0xf8
          || (insn & 0xff) == 0xcc
          || (insn & 0xff) == 0xf9
          || (insn & 0xf3) == 0x01
          || (insn & 0xf3) == 0x02
          || (insn & 0xf3) == 0x03
          || (insn & 0xfc) == 0x24
          || (insn & 0xfc) == 0x2c
          || (insn & 0xfc) == 0x30
          || (insn & 0xfc) == 0x34
          || (insn & 0xfc) == 0x38
          || (insn & 0xff) == 0xde
          || (insn & 0xff) == 0xdf
          || (insn & 0xff) == 0xf9
          || (insn & 0xff) == 0xcc)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 2, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn = bfd_getb16 (buffer);
      insn <<= 8;
      status = (*info->read_memory_func) (memaddr + 2, buffer, 1, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn |= *(unsigned char *) buffer;
      consume = 3;
    }

  /* These are four byte insns.  */
  else if ((insn & 0xff) == 0xfa
          || (insn & 0xff) == 0xf7
          || (insn & 0xff) == 0xfb)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn = bfd_getb32 (buffer);
      consume = 4;
    }

  /* These are five byte insns.  */
  else if ((insn & 0xff) == 0xcd
          || (insn & 0xff) == 0xdc)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      insn = bfd_getb32 (buffer);
      consume = 5;
    }

  /* These are six byte insns.  */
  else if ((insn & 0xff) == 0xfd
          || (insn & 0xff) == 0xfc)
    {
      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }

      insn = bfd_getb32 (buffer);
      consume = 6;
    }

  /* Else its a seven byte insns (in theory).  */
  else
    {
      status = (*info->read_memory_func) (memaddr, buffer, 4, info);
      if (status != 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }

      insn = bfd_getb32 (buffer);
      consume = 7;
      /* Handle the 5-byte extended instruction codes.  */
      if ((insn & 0xfff80000) == 0xfe800000)
       consume = 5;
    }

  disassemble (memaddr, info, insn, consume);

  return consume;
}

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Definition at line 665 of file msp430-dis.c.

{
  void *stream = info->stream;
  fprintf_ftype prin = info->fprintf_func;
  struct msp430_opcode_s *opcode;
  char op1[32], op2[32], comm1[64], comm2[64];
  int cmd_len = 0;
  unsigned short insn;
  int cycles = 0;
  char *bc = "";
  char dinfo[32];           /* Debug purposes.  */

  insn = msp430dis_opcode (addr, info);
  sprintf (dinfo, "0x%04x", insn);

  if (((int) addr & 0xffff) > 0xffdf)
    {
      (*prin) (stream, "interrupt service routine at 0x%04x", 0xffff & insn);
      return 2;
    }

  *comm1 = 0;
  *comm2 = 0;

  for (opcode = msp430_opcodes; opcode->name; opcode++)
    {
      if ((insn & opcode->bin_mask) == opcode->bin_opcode
         && opcode->bin_opcode != 0x9300)
       {
         *op1 = 0;
         *op2 = 0;
         *comm1 = 0;
         *comm2 = 0;

         /* r0 as destination. Ad should be zero.  */
         if (opcode->insn_opnumb == 3 && (insn & 0x000f) == 0
             && (0x0080 & insn) == 0)
           {
             cmd_len =
              msp430_branchinstr (info, opcode, addr, insn, op1, comm1,
                                &cycles);
             if (cmd_len)
              break;
           }

         switch (opcode->insn_opnumb)
           {
           case 0:
             cmd_len = msp430_nooperands (opcode, addr, insn, comm1, &cycles);
             break;
           case 2:
             cmd_len =
              msp430_doubleoperand (info, opcode, addr, insn, op1, op2,
                                  comm1, comm2, &cycles);
             if (insn & BYTE_OPERATION)
              bc = ".b";
             break;
           case 1:
             cmd_len =
              msp430_singleoperand (info, opcode, addr, insn, op1, comm1,
                                  &cycles);
             if (insn & BYTE_OPERATION && opcode->fmt != 3)
              bc = ".b";
             break;
           default:
             break;
           }
       }

      if (cmd_len)
       break;
    }

  dinfo[5] = 0;

  if (cmd_len < 1)
    {
      /* Unknown opcode, or invalid combination of operands.  */
      (*prin) (stream, ".word      0x%04x;       ????", PS (insn));
      return 2;
    }

  (*prin) (stream, "%s%s", opcode->name, bc);

  if (*op1)
    (*prin) (stream, "\t%s", op1);
  if (*op2)
    (*prin) (stream, ",");

  if (strlen (op1) < 7)
    (*prin) (stream, "\t");
  if (!strlen (op1))
    (*prin) (stream, "\t");

  if (*op2)
    (*prin) (stream, "%s", op2);
  if (strlen (op2) < 8)
    (*prin) (stream, "\t");

  if (*comm1 || *comm2)
    (*prin) (stream, ";");
  else if (cycles)
    {
      if (*op2)
       (*prin) (stream, ";");
      else
       {
         if (strlen (op1) < 7)
           (*prin) (stream, ";");
         else
           (*prin) (stream, "\t;");
       }
    }
  if (*comm1)
    (*prin) (stream, "%s", comm1);
  if (*comm1 && *comm2)
    (*prin) (stream, ",");
  if (*comm2)
    (*prin) (stream, " %s", comm2);
  return cmd_len;
}

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Definition at line 608 of file mt-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_mt
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = mt_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      mt_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 734 of file ns32k-dis.c.

{
  unsigned int i;
  const char *d;
  unsigned short first_word;
  int ioffset;              /* Bits into instruction.  */
  int aoffset;              /* Bits into arguments.  */
  char arg_bufs[MAX_ARGS+1][ARG_LEN];
  int argnum;
  int maxarg;
  struct private priv;
  bfd_byte *buffer = priv.the_buffer;
  dis_info = info;

  info->private_data = & priv;
  priv.max_fetched = priv.the_buffer;
  priv.insn_start = memaddr;
  if (setjmp (priv.bailout) != 0)
    /* Error return.  */
    return -1;

  /* Look for 8bit opcodes first. Other wise, fetching two bytes could take
     us over the end of accessible data unnecessarilly.  */
  FETCH_DATA (info, buffer + 1);
  for (i = 0; i < NOPCODES; i++)
    if (ns32k_opcodes[i].opcode_id_size <= 8
       && ((buffer[0]
            & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1))
           == ns32k_opcodes[i].opcode_seed))
      break;
  if (i == NOPCODES)
    {
      /* Maybe it is 9 to 16 bits big.  */
      FETCH_DATA (info, buffer + 2);
      first_word = read_memory_integer(buffer, 2);

      for (i = 0; i < NOPCODES; i++)
       if ((first_word
            & (((unsigned long) 1 << ns32k_opcodes[i].opcode_id_size) - 1))
           == ns32k_opcodes[i].opcode_seed)
         break;

      /* Handle undefined instructions.  */
      if (i == NOPCODES)
       {
         (*dis_info->fprintf_func)(dis_info->stream, "0%o", buffer[0]);
         return 1;
       }
    }

  (*dis_info->fprintf_func)(dis_info->stream, "%s", ns32k_opcodes[i].name);

  ioffset = ns32k_opcodes[i].opcode_size;
  aoffset = ns32k_opcodes[i].opcode_size;
  d = ns32k_opcodes[i].operands;

  if (*d)
    {
      /* Offset in bits of the first thing beyond each index byte.
        Element 0 is for operand A and element 1 is for operand B.
        The rest are irrelevant, but we put them here so we don't
        index outside the array.  */
      int index_offset[MAX_ARGS];

      /* 0 for operand A, 1 for operand B, greater for other args.  */
      int whicharg = 0;
      
      (*dis_info->fprintf_func)(dis_info->stream, "\t");

      maxarg = 0;

      /* First we have to find and keep track of the index bytes,
        if we are using scaled indexed addressing mode, since the index
        bytes occur right after the basic instruction, not as part
        of the addressing extension.  */
      if (Is_gen(d[1]))
       {
         int addr_mode = bit_extract (buffer, ioffset - 5, 5);

         if (Adrmod_is_index (addr_mode))
           {
             aoffset += 8;
             index_offset[0] = aoffset;
           }
       }

      if (d[2] && Is_gen(d[3]))
       {
         int addr_mode = bit_extract (buffer, ioffset - 10, 5);

         if (Adrmod_is_index (addr_mode))
           {
             aoffset += 8;
             index_offset[1] = aoffset;
           }
       }

      while (*d)
       {
         argnum = *d - '1';
         d++;
         if (argnum > maxarg && argnum < MAX_ARGS)
           maxarg = argnum;
         ioffset = print_insn_arg (*d, ioffset, &aoffset, buffer,
                                memaddr, arg_bufs[argnum],
                                index_offset[whicharg]);
         d++;
         whicharg++;
       }
      for (argnum = 0; argnum <= maxarg; argnum++)
       {
         bfd_vma addr;
         char *ch;

         for (ch = arg_bufs[argnum]; *ch;)
           {
             if (*ch == NEXT_IS_ADDR)
              {
                ++ch;
                addr = bfd_scan_vma (ch, NULL, 16);
                (*dis_info->print_address_func) (addr, dis_info);
                while (*ch && *ch != NEXT_IS_ADDR)
                  ++ch;
                if (*ch)
                  ++ch;
              }
             else
              (*dis_info->fprintf_func)(dis_info->stream, "%c", *ch++);
           }
         if (argnum < maxarg)
           (*dis_info->fprintf_func)(dis_info->stream, ", ");
       }
    }
  return aoffset / 8;
}

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Definition at line 453 of file openrisc-dis.c.

{
  static cpu_desc_list *cd_list = 0;
  cpu_desc_list *cl = 0;
  static CGEN_CPU_DESC cd = 0;
  static CGEN_BITSET *prev_isa;
  static int prev_mach;
  static int prev_endian;
  int length;
  CGEN_BITSET *isa;
  int mach;
  int endian = (info->endian == BFD_ENDIAN_BIG
              ? CGEN_ENDIAN_BIG
              : CGEN_ENDIAN_LITTLE);
  enum bfd_architecture arch;

  /* ??? gdb will set mach but leave the architecture as "unknown" */
#ifndef CGEN_BFD_ARCH
#define CGEN_BFD_ARCH bfd_arch_openrisc
#endif
  arch = info->arch;
  if (arch == bfd_arch_unknown)
    arch = CGEN_BFD_ARCH;
   
  /* There's no standard way to compute the machine or isa number
     so we leave it to the target.  */
#ifdef CGEN_COMPUTE_MACH
  mach = CGEN_COMPUTE_MACH (info);
#else
  mach = info->mach;
#endif

#ifdef CGEN_COMPUTE_ISA
  {
    static CGEN_BITSET *permanent_isa;

    if (!permanent_isa)
      permanent_isa = cgen_bitset_create (MAX_ISAS);
    isa = permanent_isa;
    cgen_bitset_clear (isa);
    cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
  }
#else
  isa = info->insn_sets;
#endif

  /* If we've switched cpu's, try to find a handle we've used before */
  if (cd
      && (cgen_bitset_compare (isa, prev_isa) != 0
         || mach != prev_mach
         || endian != prev_endian))
    {
      cd = 0;
      for (cl = cd_list; cl; cl = cl->next)
       {
         if (cgen_bitset_compare (cl->isa, isa) == 0 &&
             cl->mach == mach &&
             cl->endian == endian)
           {
             cd = cl->cd;
             prev_isa = cd->isas;
             break;
           }
       }
    } 

  /* If we haven't initialized yet, initialize the opcode table.  */
  if (! cd)
    {
      const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
      const char *mach_name;

      if (!arch_type)
       abort ();
      mach_name = arch_type->printable_name;

      prev_isa = cgen_bitset_copy (isa);
      prev_mach = mach;
      prev_endian = endian;
      cd = openrisc_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
                             CGEN_CPU_OPEN_BFDMACH, mach_name,
                             CGEN_CPU_OPEN_ENDIAN, prev_endian,
                             CGEN_CPU_OPEN_END);
      if (!cd)
       abort ();

      /* Save this away for future reference.  */
      cl = xmalloc (sizeof (struct cpu_desc_list));
      cl->cd = cd;
      cl->isa = prev_isa;
      cl->mach = mach;
      cl->endian = endian;
      cl->next = cd_list;
      cd_list = cl;

      openrisc_cgen_init_dis (cd);
    }

  /* We try to have as much common code as possible.
     But at this point some targets need to take over.  */
  /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
     but if not possible try to move this hook elsewhere rather than
     have two hooks.  */
  length = CGEN_PRINT_INSN (cd, pc, info);
  if (length > 0)
    return length;
  if (length < 0)
    return -1;

  (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
  return cd->default_insn_bitsize / 8;
}

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Definition at line 190 of file pdp11-dis.c.

{
  bfd_vma start_memaddr = memaddr;
  int opcode;
  int src, dst;
  int i;

  info->bytes_per_line = 6;
  info->bytes_per_chunk = 2;
  info->display_endian = BFD_ENDIAN_LITTLE;

  if (read_word (memaddr, &opcode, info) != 0)
    return -1;
  memaddr += 2;

  src = (opcode >> 6) & 0x3f;
  dst = opcode & 0x3f;

  for (i = 0; i < pdp11_num_opcodes; i++)
    {
#define OP pdp11_opcodes[i]
      if ((opcode & OP.mask) == OP.opcode)
       switch (OP.type)
         {
         case PDP11_OPCODE_NO_OPS:
           FPRINTF (F, OP.name);
           goto done;
         case PDP11_OPCODE_REG:
           FPRINTF (F, OP.name);
           FPRINTF (F, AFTER_INSTRUCTION);
           print_reg (dst, info);
           goto done;
         case PDP11_OPCODE_OP:
           FPRINTF (F, OP.name);
           FPRINTF (F, AFTER_INSTRUCTION);
           if (strcmp (OP.name, "jmp") == 0)
             dst |= JUMP;
           if (print_operand (&memaddr, dst, info) < 0)
             return -1;
           goto done;
         case PDP11_OPCODE_FOP:
           FPRINTF (F, OP.name);
           FPRINTF (F, AFTER_INSTRUCTION);
           if (strcmp (OP.name, "jmp") == 0)
             dst |= JUMP;
           if (print_foperand (&memaddr, dst, info) < 0)
             return -1;
           goto done;
         case PDP11_OPCODE_REG_OP:
           FPRINTF (F, OP.name);
           FPRINTF (F, AFTER_INSTRUCTION);
           print_reg (src, info);
           FPRINTF (F, OPERAND_SEPARATOR);
           if (strcmp (OP.name, "jsr") == 0)
             dst |= JUMP;
           if (print_operand (&memaddr, dst, info) < 0)
             return -1;
           goto done;
         case PDP11_OPCODE_REG_OP_REV:
           FPRINTF (F, OP.name);
           FPRINTF (F, AFTER_INSTRUCTION);
           if (print_operand (&memaddr, dst, info) < 0)
             return -1;
           FPRINTF (F, OPERAND_SEPARATOR);
           print_reg (src, info);
           goto done;
         case PDP11_OPCODE_AC_FOP:
           {
             int ac = (opcode & 0xe0) >> 6;
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             print_freg (ac, info);
             FPRINTF (F, OPERAND_SEPARATOR);
             if (print_foperand (&memaddr, dst, info) < 0)
              return -1;
             goto done;
           }
         case PDP11_OPCODE_FOP_AC:
           {
             int ac = (opcode & 0xe0) >> 6;
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             if (print_foperand (&memaddr, dst, info) < 0)
              return -1;
             FPRINTF (F, OPERAND_SEPARATOR);
             print_freg (ac, info);
             goto done;
           }
         case PDP11_OPCODE_AC_OP:
           {
             int ac = (opcode & 0xe0) >> 6;
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             print_freg (ac, info);
             FPRINTF (F, OPERAND_SEPARATOR);
             if (print_operand (&memaddr, dst, info) < 0)
              return -1;
             goto done;
           }
         case PDP11_OPCODE_OP_AC:
           {
             int ac = (opcode & 0xe0) >> 6;
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             if (print_operand (&memaddr, dst, info) < 0)
              return -1;
             FPRINTF (F, OPERAND_SEPARATOR);
             print_freg (ac, info);
             goto done;
           }
         case PDP11_OPCODE_OP_OP:
           FPRINTF (F, OP.name);
           FPRINTF (F, AFTER_INSTRUCTION);
           if (print_operand (&memaddr, src, info) < 0)
             return -1;
           FPRINTF (F, OPERAND_SEPARATOR);
           if (print_operand (&memaddr, dst, info) < 0)
             return -1;
           goto done;
         case PDP11_OPCODE_DISPL:
           {
             int displ = (opcode & 0xff) << 8;
             bfd_vma address = memaddr + (sign_extend (displ) >> 7);
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             (*info->print_address_func) (address, info);
             goto done;
           }
         case PDP11_OPCODE_REG_DISPL:
           {
             int displ = (opcode & 0x3f) << 10;
             bfd_vma address = memaddr - (displ >> 9);

             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             print_reg (src, info);
             FPRINTF (F, OPERAND_SEPARATOR);
             (*info->print_address_func) (address, info);
             goto done;
           }
         case PDP11_OPCODE_IMM8:
           {
             int code = opcode & 0xff;
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             FPRINTF (F, "%o", code);
             goto done;
           }
         case PDP11_OPCODE_IMM6:
           {
             int code = opcode & 0x3f;
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             FPRINTF (F, "%o", code);
             goto done;
           }
         case PDP11_OPCODE_IMM3:
           {
             int code = opcode & 7;
             FPRINTF (F, OP.name);
             FPRINTF (F, AFTER_INSTRUCTION);
             FPRINTF (F, "%o", code);
             goto done;
           }
         case PDP11_OPCODE_ILLEGAL:
           {
             FPRINTF (F, ".word");
             FPRINTF (F, AFTER_INSTRUCTION);
             FPRINTF (F, "%o", opcode);
             goto done;
           }
         default:
           /* TODO: is this a proper way of signalling an error? */
           FPRINTF (F, "<internal error: unrecognized instruction type>");
           return -1;
         }
#undef OP
    }
 done:

  return memaddr - start_memaddr;
}

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Definition at line 42 of file pj-dis.c.

{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  unsigned char opcode;
  int status;

  if ((status = info->read_memory_func (addr, &opcode, 1, info)))
    goto fail;

  if (opcode == 0xff)
    {
      unsigned char byte_2;

      if ((status = info->read_memory_func (addr + 1, &byte_2, 1, info)))
       goto fail;
      fprintf_fn (stream, "%s\t", pj_opc_info[opcode + byte_2].u.name);
      return 2;
    }
  else
    {
      char *sep = "\t";
      int insn_start = addr;
      const pj_opc_info_t *op = &pj_opc_info[opcode];
      int a;

      addr++;
      fprintf_fn (stream, "%s", op->u.name);

      /* The tableswitch instruction is followed by the default
        address, low value, high value and the destinations.  */

      if (strcmp (op->u.name, "tableswitch") == 0)
       {
         int lowval;
         int highval;
         int val;

         addr = (addr + 3) & ~3;
         if ((status = get_int (addr, &val, info)))
           goto fail;

         fprintf_fn (stream, " default: ");
         (*info->print_address_func) (val + insn_start, info);
         addr += 4;

         if ((status = get_int (addr, &lowval, info)))
           goto fail;
         addr += 4;

         if ((status = get_int (addr, &highval, info)))
           goto fail;
         addr += 4;

         while (lowval <= highval)
           {
             if ((status = get_int (addr, &val, info)))
              goto fail;
             fprintf_fn (stream, " %d:[", lowval);
             (*info->print_address_func) (val + insn_start, info);
             fprintf_fn (stream, " ]");
             addr += 4;
             lowval++;
           }
         return addr - insn_start;
       }

      /* The lookupswitch instruction is followed by the default
        address, element count and pairs of values and
        addresses.  */
      if (strcmp (op->u.name, "lookupswitch") == 0)
       {
         int count;
         int val;

         addr = (addr + 3) & ~3;
         if ((status = get_int (addr, &val, info)))
           goto fail;
         addr += 4;

         fprintf_fn (stream, " default: ");
         (*info->print_address_func) (val + insn_start, info);

         if ((status = get_int (addr, &count, info)))
           goto fail;
         addr += 4;

         while (count--)
           {
             if ((status = get_int (addr, &val, info)))
              goto fail;
             addr += 4;
             fprintf_fn (stream, " %d:[", val);

             if ((status = get_int (addr, &val, info)))
              goto fail;
             addr += 4;

             (*info->print_address_func) (val + insn_start, info);
             fprintf_fn (stream, " ]");
           }
         return addr - insn_start;
       }

      for (a = 0; op->arg[a]; a++)
       {
         unsigned char data[4];
         int val = 0;
         int i;
         int size = ASIZE (op->arg[a]);

         if ((status = info->read_memory_func (addr, data, size, info)))
           goto fail;

         val = (UNS (op->arg[0]) || ((data[0] & 0x80) == 0)) ? 0 : -1;

         for (i = 0; i < size; i++)
           val = (val << 8) | (data[i] & 0xff);

         if (PCREL (op->arg[a]))
           (*info->print_address_func) (val + insn_start, info);
         else
           fprintf_fn (stream, "%s%d", sep, val);

         sep = ",";
         addr += size;
       }
      return op->len;
    }

 fail:
  info->memory_error_func (status, addr, info);
  return -1;
}

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Definition at line 125 of file ppc-dis.c.

{
  return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
}

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Definition at line 107 of file s390-dis.c.

{
  bfd_byte buffer[6];
  const struct s390_opcode *opcode;
  const struct s390_opcode *opcode_end;
  unsigned int value;
  int status, opsize, bufsize;
  char separator;

  if (init_flag == 0)
    init_disasm (info);

  /* The output looks better if we put 6 bytes on a line.  */
  info->bytes_per_line = 6;

  /* Every S390 instruction is max 6 bytes long.  */
  memset (buffer, 0, 6);
  status = (*info->read_memory_func) (memaddr, buffer, 6, info);
  if (status != 0)
    {
      for (bufsize = 0; bufsize < 6; bufsize++)
       if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0)
         break;
      if (bufsize <= 0)
       {
         (*info->memory_error_func) (status, memaddr, info);
         return -1;
       }
      /* Opsize calculation looks strange but it works
        00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes,
        11xxxxxx -> 6 bytes.  */
      opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
      status = opsize > bufsize;
    }
  else
    {
      bufsize = 6;
      opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1;
    }

  if (status == 0)
    {
      /* Find the first match in the opcode table.  */
      opcode_end = s390_opcodes + s390_num_opcodes;
      for (opcode = s390_opcodes + opc_index[(int) buffer[0]];
          (opcode < opcode_end) && (buffer[0] == opcode->opcode[0]);
          opcode++)
       {
         const struct s390_operand *operand;
         const unsigned char *opindex;

         /* Check architecture.  */
         if (!(opcode->modes & current_arch_mask))
           continue;
         /* Check signature of the opcode.  */
         if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1]
             || (buffer[2] & opcode->mask[2]) != opcode->opcode[2]
             || (buffer[3] & opcode->mask[3]) != opcode->opcode[3]
             || (buffer[4] & opcode->mask[4]) != opcode->opcode[4]
             || (buffer[5] & opcode->mask[5]) != opcode->opcode[5])
           continue;

         /* The instruction is valid.  */
         if (opcode->operands[0] != 0)
           (*info->fprintf_func) (info->stream, "%s\t", opcode->name);
         else
           (*info->fprintf_func) (info->stream, "%s", opcode->name);

         /* Extract the operands.  */
         separator = 0;
         for (opindex = opcode->operands; *opindex != 0; opindex++)
           {
             unsigned int value;

             operand = s390_operands + *opindex;
             value = s390_extract_operand (buffer, operand);

             if ((operand->flags & S390_OPERAND_INDEX) && value == 0)
              continue;
             if ((operand->flags & S390_OPERAND_BASE) &&
                value == 0 && separator == '(')
              {
                separator = ',';
                continue;
              }

             if (separator)
              (*info->fprintf_func) (info->stream, "%c", separator);

             if (operand->flags & S390_OPERAND_GPR)
              (*info->fprintf_func) (info->stream, "%%r%i", value);
             else if (operand->flags & S390_OPERAND_FPR)
              (*info->fprintf_func) (info->stream, "%%f%i", value);
             else if (operand->flags & S390_OPERAND_AR)
              (*info->fprintf_func) (info->stream, "%%a%i", value);
             else if (operand->flags & S390_OPERAND_CR)
              (*info->fprintf_func) (info->stream, "%%c%i", value);
             else if (operand->flags & S390_OPERAND_PCREL)
              (*info->print_address_func) (memaddr + (int) value, info);
             else if (operand->flags & S390_OPERAND_SIGNED)
              (*info->fprintf_func) (info->stream, "%i", (int) value);
             else
              (*info->fprintf_func) (info->stream, "%u", value);

             if (operand->flags & S390_OPERAND_DISP)
              {
                separator = '(';
              }
             else if (operand->flags & S390_OPERAND_BASE)
              {
                (*info->fprintf_func) (info->stream, ")");
                separator = ',';
              }
             else
              separator = ',';
           }

         /* Found instruction, printed it, return its size.  */
         return opsize;
       }
      /* No matching instruction found, fall through to hex print.  */
    }

  if (bufsize >= 4)
    {
      value = (unsigned int) buffer[0];
      value = (value << 8) + (unsigned int) buffer[1];
      value = (value << 8) + (unsigned int) buffer[2];
      value = (value << 8) + (unsigned int) buffer[3];
      (*info->fprintf_func) (info->stream, ".long\t0x%08x", value);
      return 4;
    }
  else if (bufsize >= 2)
    {
      value = (unsigned int) buffer[0];
      value = (value << 8) + (unsigned int) buffer[1];
      (*info->fprintf_func) (info->stream, ".short\t0x%04x", value);
      return 2;
    }
  else
    {
      value = (unsigned int) buffer[0];
      (*info->fprintf_func) (info->stream, ".byte\t0x%02x", value);
      return 1;
    }
}

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Definition at line 382 of file sh-dis.c.

{
  fprintf_ftype fprintf_fn = info->fprintf_func;
  void *stream = info->stream;
  unsigned char insn[4];
  unsigned char nibs[8];
  int status;
  bfd_vma relmask = ~(bfd_vma) 0;
  const sh_opcode_info *op;
  unsigned int target_arch;
  int allow_op32;

  switch (info->mach)
    {
    case bfd_mach_sh:
      target_arch = arch_sh1;
      /* SH coff object files lack information about the machine type, so
         we end up with bfd_mach_sh unless it was set explicitly (which
        could have happended if this is a call from gdb or the simulator.)  */
      if (info->symbols
         && bfd_asymbol_flavour(*info->symbols) == bfd_target_coff_flavour)
       target_arch = arch_sh4;
      break;
    case bfd_mach_sh5:
#ifdef INCLUDE_SHMEDIA
      status = print_insn_sh64 (memaddr, info);
      if (status != -2)
       return status;
#endif
      /* When we get here for sh64, it's because we want to disassemble
        SHcompact, i.e. arch_sh4.  */
      target_arch = arch_sh4;
      break;
    default:
      target_arch = sh_get_arch_from_bfd_mach (info->mach);
    }

  status = info->read_memory_func (memaddr, insn, 2, info);

  if (status != 0)
    {
      info->memory_error_func (status, memaddr, info);
      return -1;
    }

  if (info->endian == BFD_ENDIAN_LITTLE)
    {
      nibs[0] = (insn[1] >> 4) & 0xf;
      nibs[1] = insn[1] & 0xf;

      nibs[2] = (insn[0] >> 4) & 0xf;
      nibs[3] = insn[0] & 0xf;
    }
  else
    {
      nibs[0] = (insn[0] >> 4) & 0xf;
      nibs[1] = insn[0] & 0xf;

      nibs[2] = (insn[1] >> 4) & 0xf;
      nibs[3] = insn[1] & 0xf;
    }
  status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
  if (status != 0)
    allow_op32 = 0;
  else
    {
      allow_op32 = 1;

      if (info->endian == BFD_ENDIAN_LITTLE)
       {
         nibs[4] = (insn[3] >> 4) & 0xf;
         nibs[5] = insn[3] & 0xf;

         nibs[6] = (insn[2] >> 4) & 0xf;
         nibs[7] = insn[2] & 0xf;
       }
      else
       {
         nibs[4] = (insn[2] >> 4) & 0xf;
         nibs[5] = insn[2] & 0xf;

         nibs[6] = (insn[3] >> 4) & 0xf;
         nibs[7] = insn[3] & 0xf;
       }
    }

  if (nibs[0] == 0xf && (nibs[1] & 4) == 0
      && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
    {
      if (nibs[1] & 8)
       {
         int field_b;

         status = info->read_memory_func (memaddr + 2, insn, 2, info);

         if (status != 0)
           {
             info->memory_error_func (status, memaddr + 2, info);
             return -1;
           }

         if (info->endian == BFD_ENDIAN_LITTLE)
           field_b = insn[1] << 8 | insn[0];
         else
           field_b = insn[0] << 8 | insn[1];

         print_insn_ppi (field_b, info);
         print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
         return 4;
       }
      print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
      return 2;
    }
  for (op = sh_table; op->name; op++)
    {
      int n;
      int imm = 0;
      int rn = 0;
      int rm = 0;
      int rb = 0;
      int disp_pc;
      bfd_vma disp_pc_addr = 0;
      int disp = 0;
      int has_disp = 0;
      int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;

      if (!allow_op32
         && SH_MERGE_ARCH_SET (op->arch, arch_op32))
       goto fail;

      if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
       goto fail;
      for (n = 0; n < max_n; n++)
       {
         int i = op->nibbles[n];

         if (i < 16)
           {
             if (nibs[n] == i)
              continue;
             goto fail;
           }
         switch (i)
           {
           case BRANCH_8:
             imm = (nibs[2] << 4) | (nibs[3]);
             if (imm & 0x80)
              imm |= ~0xff;
             imm = ((char) imm) * 2 + 4;
             goto ok;
           case BRANCH_12:
             imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
             if (imm & 0x800)
              imm |= ~0xfff;
             imm = imm * 2 + 4;
             goto ok;
           case IMM0_3c:
             if (nibs[3] & 0x8)
              goto fail;
             imm = nibs[3] & 0x7;
             break;
           case IMM0_3s:
             if (!(nibs[3] & 0x8))
              goto fail;
             imm = nibs[3] & 0x7;
             break;
           case IMM0_3Uc:
             if (nibs[2] & 0x8)
              goto fail;
             imm = nibs[2] & 0x7;
             break;
           case IMM0_3Us:
             if (!(nibs[2] & 0x8))
              goto fail;
             imm = nibs[2] & 0x7;
             break;
           case DISP0_12:
           case DISP1_12:
             disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
             has_disp = 1;
             goto ok;
           case DISP0_12BY2:
           case DISP1_12BY2:
             disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
             relmask = ~(bfd_vma) 1;
             has_disp = 1;
             goto ok;
           case DISP0_12BY4:
           case DISP1_12BY4:
             disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
             relmask = ~(bfd_vma) 3;
             has_disp = 1;
             goto ok;
           case DISP0_12BY8:
           case DISP1_12BY8:
             disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
             relmask = ~(bfd_vma) 7;
             has_disp = 1;
             goto ok;
           case IMM0_20_4:
             break;
           case IMM0_20:
             imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
                   | (nibs[6] << 4) | nibs[7]);
             if (imm & 0x80000)
              imm -= 0x100000;
             goto ok;
           case IMM0_20BY8:
             imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
                   | (nibs[6] << 4) | nibs[7]);
             imm <<= 8;
             if (imm & 0x8000000)
              imm -= 0x10000000;
             goto ok;
           case IMM0_4:
           case IMM1_4:
             imm = nibs[3];
             goto ok;
           case IMM0_4BY2:
           case IMM1_4BY2:
             imm = nibs[3] << 1;
             goto ok;
           case IMM0_4BY4:
           case IMM1_4BY4:
             imm = nibs[3] << 2;
             goto ok;
           case IMM0_8:
           case IMM1_8:
             imm = (nibs[2] << 4) | nibs[3];
             disp = imm;
             has_disp = 1;
             if (imm & 0x80)
              imm -= 0x100;
             goto ok;
           case PCRELIMM_8BY2:
             imm = ((nibs[2] << 4) | nibs[3]) << 1;
             relmask = ~(bfd_vma) 1;
             goto ok;
           case PCRELIMM_8BY4:
             imm = ((nibs[2] << 4) | nibs[3]) << 2;
             relmask = ~(bfd_vma) 3;
             goto ok;
           case IMM0_8BY2:
           case IMM1_8BY2:
             imm = ((nibs[2] << 4) | nibs[3]) << 1;
             goto ok;
           case IMM0_8BY4:
           case IMM1_8BY4:
             imm = ((nibs[2] << 4) | nibs[3]) << 2;
             goto ok;
           case REG_N_D:
             if ((nibs[n] & 1) != 0)
              goto fail;
             /* Fall through.  */
           case REG_N:
             rn = nibs[n];
             break;
           case REG_M:
             rm = nibs[n];
             break;
           case REG_N_B01:
             if ((nibs[n] & 0x3) != 1 /* binary 01 */)
              goto fail;
             rn = (nibs[n] & 0xc) >> 2;
             break;
           case REG_NM:
             rn = (nibs[n] & 0xc) >> 2;
             rm = (nibs[n] & 0x3);
             break;
           case REG_B:
             rb = nibs[n] & 0x07;
             break;
           case SDT_REG_N:
             /* sh-dsp: single data transfer.  */
             rn = nibs[n];
             if ((rn & 0xc) != 4)
              goto fail;
             rn = rn & 0x3;
             rn |= (!(rn & 2)) << 2;
             break;
           case PPI:
           case REPEAT:
             goto fail;
           default:
             abort ();
           }
       }

    ok:
      /* sh2a has D_REG but not X_REG.  We don't know the pattern
        doesn't match unless we check the output args to see if they
        make sense.  */
      if (target_arch == arch_sh2a
         && ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
             || (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
       goto fail;

      fprintf_fn (stream, "%s\t", op->name);
      disp_pc = 0;
      for (n = 0; n < 3 && op->arg[n] != A_END; n++)
       {
         if (n && op->arg[1] != A_END)
           fprintf_fn (stream, ",");
         switch (op->arg[n])
           {
           case A_IMM:
             fprintf_fn (stream, "#%d", imm);
             break;
           case A_R0:
             fprintf_fn (stream, "r0");
             break;
           case A_REG_N:
             fprintf_fn (stream, "r%d", rn);
             break;
           case A_INC_N:
           case AS_INC_N:
             fprintf_fn (stream, "@r%d+", rn);
             break;
           case A_DEC_N:
           case AS_DEC_N:
             fprintf_fn (stream, "@-r%d", rn);
             break;
           case A_IND_N:
           case AS_IND_N:
             fprintf_fn (stream, "@r%d", rn);
             break;
           case A_DISP_REG_N:
             fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
             break;
           case AS_PMOD_N:
             fprintf_fn (stream, "@r%d+r8", rn);
             break;
           case A_REG_M:
             fprintf_fn (stream, "r%d", rm);
             break;
           case A_INC_M:
             fprintf_fn (stream, "@r%d+", rm);
             break;
           case A_DEC_M:
             fprintf_fn (stream, "@-r%d", rm);
             break;
           case A_IND_M:
             fprintf_fn (stream, "@r%d", rm);
             break;
           case A_DISP_REG_M:
             fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
             break;
           case A_REG_B:
             fprintf_fn (stream, "r%d_bank", rb);
             break;
           case A_DISP_PC:
             disp_pc = 1;
             disp_pc_addr = imm + 4 + (memaddr & relmask);
             (*info->print_address_func) (disp_pc_addr, info);
             break;
           case A_IND_R0_REG_N:
             fprintf_fn (stream, "@(r0,r%d)", rn);
             break;
           case A_IND_R0_REG_M:
             fprintf_fn (stream, "@(r0,r%d)", rm);
             break;
           case A_DISP_GBR:
             fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
             break;
           case A_TBR:
             fprintf_fn (stream, "tbr");
             break;
           case A_DISP2_TBR:
             fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
             break;
           case A_INC_R15:
             fprintf_fn (stream, "@r15+");
             break;
           case A_DEC_R15:
             fprintf_fn (stream, "@-r15");
             break;
           case A_R0_GBR:
             fprintf_fn (stream, "@(r0,gbr)");
             break;
           case A_BDISP12:
           case A_BDISP8:
             (*info->print_address_func) (imm + memaddr, info);
             break;
           case A_SR:
             fprintf_fn (stream, "sr");
             break;
           case A_GBR:
             fprintf_fn (stream, "gbr");
             break;
           case A_VBR:
             fprintf_fn (stream, "vbr");
             break;
           case A_DSR:
             fprintf_fn (stream, "dsr");
             break;
           case A_MOD:
             fprintf_fn (stream, "mod");
             break;
           case A_RE:
             fprintf_fn (stream, "re");
             break;
           case A_RS:
             fprintf_fn (stream, "rs");
             break;
           case A_A0:
             fprintf_fn (stream, "a0");
             break;
           case A_X0:
             fprintf_fn (stream, "x0");
             break;
           case A_X1:
             fprintf_fn (stream, "x1");
             break;
           case A_Y0:
             fprintf_fn (stream, "y0");
             break;
           case A_Y1:
             fprintf_fn (stream, "y1");
             break;
           case DSP_REG_M:
             print_dsp_reg (rm, fprintf_fn, stream);
             break;
           case A_SSR:
             fprintf_fn (stream, "ssr");
             break;
           case A_SPC:
             fprintf_fn (stream, "spc");
             break;
           case A_MACH:
             fprintf_fn (stream, "mach");
             break;
           case A_MACL:
             fprintf_fn (stream, "macl");
             break;
           case A_PR:
             fprintf_fn (stream, "pr");
             break;
           case A_SGR:
             fprintf_fn (stream, "sgr");
             break;
           case A_DBR:
             fprintf_fn (stream, "dbr");
             break;
           case F_REG_N:
             fprintf_fn (stream, "fr%d", rn);
             break;
           case F_REG_M:
             fprintf_fn (stream, "fr%d", rm);
             break;
           case DX_REG_N:
             if (rn & 1)
              {
                fprintf_fn (stream, "xd%d", rn & ~1);
                break;
              }
           case D_REG_N:
             fprintf_fn (stream, "dr%d", rn);
             break;
           case DX_REG_M:
             if (rm & 1)
              {
                fprintf_fn (stream, "xd%d", rm & ~1);
                break;
              }
           case D_REG_M:
             fprintf_fn (stream, "dr%d", rm);
             break;
           case FPSCR_M:
           case FPSCR_N:
             fprintf_fn (stream, "fpscr");
             break;
           case FPUL_M:
           case FPUL_N:
             fprintf_fn (stream, "fpul");
             break;
           case F_FR0:
             fprintf_fn (stream, "fr0");
             break;
           case V_REG_N:
             fprintf_fn (stream, "fv%d", rn * 4);
             break;
           case V_REG_M:
             fprintf_fn (stream, "fv%d", rm * 4);
             break;
           case XMTRX_M4:
             fprintf_fn (stream, "xmtrx");
             break;
           default:
             abort ();
           }
       }

#if 0
      /* This code prints instructions in delay slots on the same line
         as the instruction which needs the delay slots.  This can be
         confusing, since other disassembler don't work this way, and
         it means that the instructions are not all in a line.  So I
         disabled it.  Ian.  */
      if (!(info->flags & 1)
         && (op->name[0] == 'j'
             || (op->name[0] == 'b'
                && (op->name[1] == 'r'
                    || op->name[1] == 's'))
             || (op->name[0] == 'r' && op->name[1] == 't')
             || (op->name[0] == 'b' && op->name[2] == '.')))
       {
         info->flags |= 1;
         fprintf_fn (stream, "\t(slot ");
         print_insn_sh (memaddr + 2, info);
         info->flags &= ~1;
         fprintf_fn (stream, ")");
         return 4;
       }
#endif

      if (disp_pc && strcmp (op->name, "mova") != 0)
       {
         int size;
         bfd_byte bytes[4];

         if (relmask == ~(bfd_vma) 1)
           size = 2;
         else
           size = 4;
         status = info->read_memory_func (disp_pc_addr, bytes, size, info);
         if (status == 0)
           {
             unsigned int val;

             if (size == 2)
              {
                if (info->endian == BFD_ENDIAN_LITTLE)
                  val = bfd_getl16 (bytes);
                else
                  val = bfd_getb16 (bytes);
              }
             else
              {
                if (info->endian == BFD_ENDIAN_LITTLE)
                  val = bfd_getl32 (bytes);
                else
                  val = bfd_getb32 (bytes);
              }
             if ((*info->symbol_at_address_func) (val, info))
              {
                fprintf_fn (stream, "\t! ");
                (*info->print_address_func) (val, info);
              }
             else
              fprintf_fn (stream, "\t! %x", val);
           }
       }

      return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
    fail:
      ;

    }
  fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
  return 2;
}

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Definition at line 541 of file sh64-dis.c.

{
  enum bfd_endian endian = info->endian;
  enum sh64_elf_cr_type cr_type;

  if (info->private_data == NULL && ! init_sh64_disasm_info (info))
    return -1;

  cr_type = sh64_get_contents_type_disasm (memaddr, info);
  if (cr_type != CRT_SH5_ISA16)
    {
      int length = 4 - (memaddr % 4);
      info->display_endian = endian;

      /* If we got an uneven address to indicate SHmedia, adjust it.  */
      if (cr_type == CRT_SH5_ISA32 && length == 3)
       memaddr--, length = 4;

      /* Only disassemble on four-byte boundaries.  Addresses that are not
        a multiple of four can happen after a data region.  */
      if (cr_type == CRT_SH5_ISA32 && length == 4)
       return print_insn_sh64x_media (memaddr, info);

      /* We get CRT_DATA *only* for data regions in a mixed-contents
        section.  For sections with data only, we get indication of one
        of the ISA:s.  You may think that we shouldn't disassemble
        section with only data if we can figure that out.  However, the
        disassembly function is by default not called for data-only
        sections, so if the user explicitly specified disassembly of a
        data section, that's what we should do.  */
      if (cr_type == CRT_DATA || length != 4)
       {
         int status;
         unsigned char data[4];
         struct sh64_disassemble_info *sh64_infop = info->private_data;

         if (length == 4
             && sh64_infop->crange.cr_type != CRT_NONE
             && memaddr >= sh64_infop->crange.cr_addr
             && memaddr < (sh64_infop->crange.cr_addr
                         + sh64_infop->crange.cr_size))
           length
             = (sh64_infop->crange.cr_addr
               + sh64_infop->crange.cr_size - memaddr);

         status
           = (*info->read_memory_func) (memaddr, data,
                                    length >= 4 ? 4 : length, info);

         if (status == 0 && length >= 4)
           {
             (*info->fprintf_func) (info->stream, ".long 0x%08lx",
                                 endian == BFD_ENDIAN_BIG
                                 ? (long) (bfd_getb32 (data))
                                 : (long) (bfd_getl32 (data)));
             return 4;
           }
         else
           {
             int i;

             for (i = 0; i < length; i++)
              {
                status = info->read_memory_func (memaddr + i, data, 1, info);
                if (status != 0)
                  break;
                (*info->fprintf_func) (info->stream, "%s0x%02x",
                                    i == 0 ? ".byte " : ", ",
                                    data[0]);
              }

             return i ? i : -1;
           }
       }
    }

  /* SH1 .. SH4 instruction, let caller handle it.  */
  return -2;
}

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Definition at line 525 of file sh64-dis.c.

{
  if (info->private_data == NULL && ! init_sh64_disasm_info (info))
    return -1;

  /* Make reasonable output.  */
  info->bytes_per_line = 4;
  info->bytes_per_chunk = 4;

  return print_insn_shmedia (memaddr, info);
}

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Definition at line 451 of file sparc-dis.c.

{
  FILE *stream = info->stream;
  bfd_byte buffer[4];
  unsigned long insn;
  sparc_opcode_hash *op;
  /* Nonzero of opcode table has been initialized.  */
  static int opcodes_initialized = 0;
  /* bfd mach number of last call.  */
  static unsigned long current_mach = 0;
  bfd_vma (*getword) (const void *);

  if (!opcodes_initialized
      || info->mach != current_mach)
    {
      int i;

      current_arch_mask = compute_arch_mask (info->mach);

      if (!opcodes_initialized)
       sorted_opcodes =
         xmalloc (sparc_num_opcodes * sizeof (sparc_opcode *));
      /* Reset the sorted table so we can resort it.  */
      for (i = 0; i < sparc_num_opcodes; ++i)
       sorted_opcodes[i] = &sparc_opcodes[i];
      qsort ((char *) sorted_opcodes, sparc_num_opcodes,
            sizeof (sorted_opcodes[0]), compare_opcodes);

      build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
      current_mach = info->mach;
      opcodes_initialized = 1;
    }

  {
    int status =
      (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);

    if (status != 0)
      {
       (*info->memory_error_func) (status, memaddr, info);
       return -1;
      }
  }

  /* On SPARClite variants such as DANlite (sparc86x), instructions
     are always big-endian even when the machine is in little-endian mode.  */
  if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
    getword = bfd_getb32;
  else
    getword = bfd_getl32;

  insn = getword (buffer);

  info->insn_info_valid = 1;                     /* We do return this info.  */
  info->insn_type = dis_nonbranch;        /* Assume non branch insn.  */
  info->branch_delay_insns = 0;                  /* Assume no delay.  */
  info->target = 0;                       /* Assume no target known.  */

  for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
    {
      const sparc_opcode *opcode = op->opcode;

      /* If the insn isn't supported by the current architecture, skip it.  */
      if (! (opcode->architecture & current_arch_mask))
       continue;

      if ((opcode->match & insn) == opcode->match
         && (opcode->lose & insn) == 0)
       {
         /* Nonzero means that we have found an instruction which has
            the effect of adding or or'ing the imm13 field to rs1.  */
         int imm_added_to_rs1 = 0;
         int imm_ored_to_rs1 = 0;

         /* Nonzero means that we have found a plus sign in the args
            field of the opcode table.  */
         int found_plus = 0;

         /* Nonzero means we have an annulled branch.  */
         int is_annulled = 0;

         /* Do we have an `add' or `or' instruction combining an
             immediate with rs1?  */
         if (opcode->match == 0x80102000) /* or */
           imm_ored_to_rs1 = 1;
         if (opcode->match == 0x80002000) /* add */
           imm_added_to_rs1 = 1;

         if (X_RS1 (insn) != X_RD (insn)
             && strchr (opcode->args, 'r') != 0)
             /* Can't do simple format if source and dest are different.  */
             continue;
         if (X_RS2 (insn) != X_RD (insn)
             && strchr (opcode->args, 'O') != 0)
             /* Can't do simple format if source and dest are different.  */
             continue;

         (*info->fprintf_func) (stream, opcode->name);

         {
           const char *s;

           if (opcode->args[0] != ',')
             (*info->fprintf_func) (stream, " ");

           for (s = opcode->args; *s != '\0'; ++s)
             {
              while (*s == ',')
                {
                  (*info->fprintf_func) (stream, ",");
                  ++s;
                  switch (*s)
                    {
                    case 'a':
                     (*info->fprintf_func) (stream, "a");
                     is_annulled = 1;
                     ++s;
                     continue;
                    case 'N':
                     (*info->fprintf_func) (stream, "pn");
                     ++s;
                     continue;

                    case 'T':
                     (*info->fprintf_func) (stream, "pt");
                     ++s;
                     continue;

                    default:
                     break;
                    }
                }

              (*info->fprintf_func) (stream, " ");

              switch (*s)
                {
                case '+':
                  found_plus = 1;
                  /* Fall through.  */

                default:
                  (*info->fprintf_func) (stream, "%c", *s);
                  break;

                case '#':
                  (*info->fprintf_func) (stream, "0");
                  break;

#define       reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
                case '1':
                case 'r':
                  reg (X_RS1 (insn));
                  break;

                case '2':
                case 'O':
                  reg (X_RS2 (insn));
                  break;

                case 'd':
                  reg (X_RD (insn));
                  break;
#undef reg

#define       freg(n)              (*info->fprintf_func) (stream, "%%%s", freg_names[n])
#define       fregx(n)      (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
                case 'e':
                  freg (X_RS1 (insn));
                  break;
                case 'v':   /* Double/even.  */
                case 'V':   /* Quad/multiple of 4.  */
                  fregx (X_RS1 (insn));
                  break;

                case 'f':
                  freg (X_RS2 (insn));
                  break;
                case 'B':   /* Double/even.  */
                case 'R':   /* Quad/multiple of 4.  */
                  fregx (X_RS2 (insn));
                  break;

                case 'g':
                  freg (X_RD (insn));
                  break;
                case 'H':   /* Double/even.  */
                case 'J':   /* Quad/multiple of 4.  */
                  fregx (X_RD (insn));
                  break;
#undef freg
#undef fregx

#define       creg(n)       (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
                case 'b':
                  creg (X_RS1 (insn));
                  break;

                case 'c':
                  creg (X_RS2 (insn));
                  break;

                case 'D':
                  creg (X_RD (insn));
                  break;
#undef creg

                case 'h':
                  (*info->fprintf_func) (stream, "%%hi(%#x)",
                                      ((unsigned) 0xFFFFFFFF
                                       & ((int) X_IMM22 (insn) << 10)));
                  break;

                case 'i':   /* 13 bit immediate.  */
                case 'I':   /* 11 bit immediate.  */
                case 'j':   /* 10 bit immediate.  */
                  {
                    int imm;

                    if (*s == 'i')
                      imm = X_SIMM (insn, 13);
                    else if (*s == 'I')
                     imm = X_SIMM (insn, 11);
                    else
                     imm = X_SIMM (insn, 10);

                    /* Check to see whether we have a 1+i, and take
                      note of that fact.

                      Note: because of the way we sort the table,
                      we will be matching 1+i rather than i+1,
                      so it is OK to assume that i is after +,
                      not before it.  */
                    if (found_plus)
                     imm_added_to_rs1 = 1;

                    if (imm <= 9)
                     (*info->fprintf_func) (stream, "%d", imm);
                    else
                     (*info->fprintf_func) (stream, "%#x", imm);
                  }
                  break;

                case 'X':   /* 5 bit unsigned immediate.  */
                case 'Y':   /* 6 bit unsigned immediate.  */
                  {
                    int imm = X_IMM (insn, *s == 'X' ? 5 : 6);

                    if (imm <= 9)
                     (info->fprintf_func) (stream, "%d", imm);
                    else
                     (info->fprintf_func) (stream, "%#x", (unsigned) imm);
                  }
                  break;

                case '3':
                  (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
                  break;

                case 'K':
                  {
                    int mask = X_MEMBAR (insn);
                    int bit = 0x40, printed_one = 0;
                    const char *name;

                    if (mask == 0)
                     (info->fprintf_func) (stream, "0");
                    else
                     while (bit)
                       {
                         if (mask & bit)
                           {
                            if (printed_one)
                              (info->fprintf_func) (stream, "|");
                            name = sparc_decode_membar (bit);
                            (info->fprintf_func) (stream, "%s", name);
                            printed_one = 1;
                           }
                         bit >>= 1;
                       }
                    break;
                  }

                case 'k':
                  info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
                  (*info->print_address_func) (info->target, info);
                  break;

                case 'G':
                  info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
                  (*info->print_address_func) (info->target, info);
                  break;

                case '6':
                case '7':
                case '8':
                case '9':
                  (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
                  break;

                case 'z':
                  (*info->fprintf_func) (stream, "%%icc");
                  break;

                case 'Z':
                  (*info->fprintf_func) (stream, "%%xcc");
                  break;

                case 'E':
                  (*info->fprintf_func) (stream, "%%ccr");
                  break;

                case 's':
                  (*info->fprintf_func) (stream, "%%fprs");
                  break;

                case 'o':
                  (*info->fprintf_func) (stream, "%%asi");
                  break;

                case 'W':
                  (*info->fprintf_func) (stream, "%%tick");
                  break;

                case 'P':
                  (*info->fprintf_func) (stream, "%%pc");
                  break;

                case '?':
                  if (X_RS1 (insn) == 31)
                    (*info->fprintf_func) (stream, "%%ver");
                  else if ((unsigned) X_RS1 (insn) < 17)
                    (*info->fprintf_func) (stream, "%%%s",
                                        v9_priv_reg_names[X_RS1 (insn)]);
                  else
                    (*info->fprintf_func) (stream, "%%reserved");
                  break;

                case '!':
                  if ((unsigned) X_RD (insn) < 17)
                    (*info->fprintf_func) (stream, "%%%s",
                                        v9_priv_reg_names[X_RD (insn)]);
                  else
                    (*info->fprintf_func) (stream, "%%reserved");
                  break;

                case '$':
                  if ((unsigned) X_RS1 (insn) < 32)
                    (*info->fprintf_func) (stream, "%%%s",
                                        v9_hpriv_reg_names[X_RS1 (insn)]);
                  else
                    (*info->fprintf_func) (stream, "%%reserved");
                  break;

                case '%':
                  if ((unsigned) X_RD (insn) < 32)
                    (*info->fprintf_func) (stream, "%%%s",
                                        v9_hpriv_reg_names[X_RD (insn)]);
                  else
                    (*info->fprintf_func) (stream, "%%reserved");
                  break;

                case '/':
                  if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
                    (*info->fprintf_func) (stream, "%%reserved");
                  else
                    (*info->fprintf_func) (stream, "%%%s",
                                        v9a_asr_reg_names[X_RS1 (insn)-16]);
                  break;

                case '_':
                  if (X_RD (insn) < 16 || X_RD (insn) > 25)
                    (*info->fprintf_func) (stream, "%%reserved");
                  else
                    (*info->fprintf_func) (stream, "%%%s",
                                        v9a_asr_reg_names[X_RD (insn)-16]);
                  break;

                case '*':
                  {
                    const char *name = sparc_decode_prefetch (X_RD (insn));

                    if (name)
                     (*info->fprintf_func) (stream, "%s", name);
                    else
                     (*info->fprintf_func) (stream, "%ld", X_RD (insn));
                    break;
                  }

                case 'M':
                  (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
                  break;

                case 'm':
                  (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
                  break;

                case 'L':
                  info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
                  (*info->print_address_func) (info->target, info);
                  break;

                case 'n':
                  (*info->fprintf_func)
                    (stream, "%#x", SEX (X_DISP22 (insn), 22));
                  break;

                case 'l':
                  info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
                  (*info->print_address_func) (info->target, info);
                  break;

                case 'A':
                  {
                    const char *name = sparc_decode_asi (X_ASI (insn));

                    if (name)
                     (*info->fprintf_func) (stream, "%s", name);
                    else
                     (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
                    break;
                  }

                case 'C':
                  (*info->fprintf_func) (stream, "%%csr");
                  break;

                case 'F':
                  (*info->fprintf_func) (stream, "%%fsr");
                  break;

                case 'p':
                  (*info->fprintf_func) (stream, "%%psr");
                  break;

                case 'q':
                  (*info->fprintf_func) (stream, "%%fq");
                  break;

                case 'Q':
                  (*info->fprintf_func) (stream, "%%cq");
                  break;

                case 't':
                  (*info->fprintf_func) (stream, "%%tbr");
                  break;

                case 'w':
                  (*info->fprintf_func) (stream, "%%wim");
                  break;

                case 'x':
                  (*info->fprintf_func) (stream, "%ld",
                                      ((X_LDST_I (insn) << 8)
                                       + X_ASI (insn)));
                  break;

                case 'y':
                  (*info->fprintf_func) (stream, "%%y");
                  break;

                case 'u':
                case 'U':
                  {
                    int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
                    const char *name = sparc_decode_sparclet_cpreg (val);

                    if (name)
                     (*info->fprintf_func) (stream, "%s", name);
                    else
                     (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
                    break;
                  }
                }
             }
         }

         /* If we are adding or or'ing something to rs1, then
            check to see whether the previous instruction was
            a sethi to the same register as in the sethi.
            If so, attempt to print the result of the add or
            or (in this context add and or do the same thing)
            and its symbolic value.  */
         if (imm_ored_to_rs1 || imm_added_to_rs1)
           {
             unsigned long prev_insn;
             int errcode;

             if (memaddr >= 4)
              errcode =
                (*info->read_memory_func)
                (memaddr - 4, buffer, sizeof (buffer), info);
             else
              errcode = 1;

             prev_insn = getword (buffer);

             if (errcode == 0)
              {
                /* If it is a delayed branch, we need to look at the
                   instruction before the delayed branch.  This handles
                   sequences such as:

                   sethi %o1, %hi(_foo), %o1
                   call _printf
                   or %o1, %lo(_foo), %o1  */

                if (is_delayed_branch (prev_insn))
                  {
                    if (memaddr >= 8)
                     errcode = (*info->read_memory_func)
                       (memaddr - 8, buffer, sizeof (buffer), info);
                    else
                     errcode = 1;

                    prev_insn = getword (buffer);
                  }
              }

             /* If there was a problem reading memory, then assume
               the previous instruction was not sethi.  */
             if (errcode == 0)
              {
                /* Is it sethi to the same register?  */
                if ((prev_insn & 0xc1c00000) == 0x01000000
                    && X_RD (prev_insn) == X_RS1 (insn))
                  {
                    (*info->fprintf_func) (stream, "\t! ");
                    info->target =
                     ((unsigned) 0xFFFFFFFF
                      & ((int) X_IMM22 (prev_insn) << 10));
                    if (imm_added_to_rs1)
                     info->target += X_SIMM (insn, 13);
                    else
                     info->target |= X_SIMM (insn, 13);
                    (*info->print_address_func) (info->target, info);
                    info->insn_type = dis_dref;
                    info->data_size = 4;  /* FIXME!!! */
                  }
              }
           }

         if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
           {
              /* FIXME -- check is_annulled flag.  */
             if (opcode->flags & F_UNBR)
              info->insn_type = dis_branch;
             if (opcode->flags & F_CONDBR)
              info->insn_type = dis_condbranch;
             if (opcode->flags & F_JSR)
              info->insn_type = dis_jsr;
             if (opcode->flags & F_DELAYED)
              info->branch_delay_insns = 1;
           }

         return sizeof (buffer);
       }
    }

  info->insn_type = dis_noninsn;   /* Mark as non-valid instruction.  */
  (*info->fprintf_func) (stream, _("unknown"));
  return sizeof (buffer);
}

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Definition at line 92 of file spu-dis.c.

{
  bfd_byte buffer[4];
  int value;
  int hex_value;
  int status;
  unsigned int insn;
  const struct spu_opcode *index;
  enum spu_insns tag;

  status = (*info->read_memory_func) (memaddr, buffer, 4, info);
  if (status != 0)
    {
      (*info->memory_error_func) (status, memaddr, info);
      return -1;
    }

  insn = bfd_getb32 (buffer);

  index = get_index_for_opcode (insn);

  if (index == 0)
    {
      (*info->fprintf_func) (info->stream, ".long 0x%x", insn);
    }
  else
    {
      int i;
      int paren = 0;
      tag = (enum spu_insns)(index - spu_opcodes);
      (*info->fprintf_func) (info->stream, "%s", index->mnemonic);
      if (tag == M_BI || tag == M_BISL || tag == M_IRET || tag == M_BISLED
         || tag == M_BIHNZ || tag == M_BIHZ || tag == M_BINZ || tag == M_BIZ
          || tag == M_SYNC || tag == M_HBR)
       {
         int fb = (insn >> (32-18)) & 0x7f;
         if (fb & 0x40)
           (*info->fprintf_func) (info->stream, tag == M_SYNC ? "c" : "p");
         if (fb & 0x20)
           (*info->fprintf_func) (info->stream, "d");
         if (fb & 0x10)
           (*info->fprintf_func) (info->stream, "e");
       }
      if (index->arg[0] != 0)
       (*info->fprintf_func) (info->stream, "\t");
      hex_value = 0;
      for (i = 1;  i <= index->arg[0]; i++)
       {
         int arg = index->arg[i];
         if (arg != A_P && !paren && i > 1)
           (*info->fprintf_func) (info->stream, ",");

         switch (arg)
           {
           case A_T:
             (*info->fprintf_func) (info->stream, "$%d",
                                 DECODE_INSN_RT (insn));
             break;
           case A_A:
             (*info->fprintf_func) (info->stream, "$%d",
                                 DECODE_INSN_RA (insn));
             break;
           case A_B:
             (*info->fprintf_func) (info->stream, "$%d",
                                 DECODE_INSN_RB (insn));
             break;
           case A_C:
             (*info->fprintf_func) (info->stream, "$%d",
                                 DECODE_INSN_RC (insn));
             break;
           case A_S:
             (*info->fprintf_func) (info->stream, "$sp%d",
                                 DECODE_INSN_RA (insn));
             break;
           case A_H:
             (*info->fprintf_func) (info->stream, "$ch%d",
                                 DECODE_INSN_RA (insn));
             break;
           case A_P:
             paren++;
             (*info->fprintf_func) (info->stream, "(");
             break;
           case A_U7A:
             (*info->fprintf_func) (info->stream, "%d",
                                 173 - DECODE_INSN_U8 (insn));
             break;
           case A_U7B:
             (*info->fprintf_func) (info->stream, "%d",
                                 155 - DECODE_INSN_U8 (insn));