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cell-binutils  2.17cvs20070401
d30v-opc.c
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00001 /* d30v-opc.c -- D30V opcode list
00002    Copyright 1997, 1998, 1999, 2000, 2005 Free Software Foundation, Inc.
00003    Written by Martin Hunt, Cygnus Support
00004 
00005    This file is part of GDB, GAS, and the GNU binutils.
00006 
00007    GDB, GAS, and the GNU binutils are free software; you can redistribute
00008    them and/or modify them under the terms of the GNU General Public
00009    License as published by the Free Software Foundation; either version
00010    2, or (at your option) any later version.
00011 
00012    GDB, GAS, and the GNU binutils are distributed in the hope that they
00013    will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015    the GNU General Public License for more details.
00016 
00017    You should have received a copy of the GNU General Public License
00018    along with this file; see the file COPYING.  If not, write to the Free
00019    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
00020    MA 02110-1301, USA.  */
00021 
00022 #include <stdio.h>
00023 #include "sysdep.h"
00024 #include "opcode/d30v.h"
00025 
00026 /* This table is sorted.
00027    If you add anything, it MUST be in alphabetical order.
00028    The first field is the name the assembler uses when looking
00029    up orcodes.  The second field is the name the disassembler will use.
00030    This allows the assembler to assemble references to r63 (for example)
00031    or "sp".  The disassembler will always use the preferred form (sp).  */
00032 const struct pd_reg pre_defined_registers[] =
00033 {
00034   { "a0", NULL, OPERAND_ACC + 0 },
00035   { "a1", NULL, OPERAND_ACC + 1 },
00036   { "bpc", NULL, OPERAND_CONTROL + 3 },
00037   { "bpsw", NULL, OPERAND_CONTROL + 1 },
00038   { "c", "c", OPERAND_FLAG + 7 },
00039   { "cr0", "psw", OPERAND_CONTROL },
00040   { "cr1", "bpsw", OPERAND_CONTROL + 1 },
00041   { "cr10", "mod_s", OPERAND_CONTROL + 10 },
00042   { "cr11", "mod_e", OPERAND_CONTROL + 11 },
00043   { "cr12", NULL, OPERAND_CONTROL + 12 },
00044   { "cr13", NULL, OPERAND_CONTROL + 13 },
00045   { "cr14", "iba", OPERAND_CONTROL + 14 },
00046   { "cr15", "eit_vb", OPERAND_CONTROL + 15 },
00047   { "cr16", "int_s", OPERAND_CONTROL + 16 },
00048   { "cr17", "int_m", OPERAND_CONTROL + 17 },
00049   { "cr18", NULL, OPERAND_CONTROL + 18 },
00050   { "cr19", NULL, OPERAND_CONTROL + 19 },
00051   { "cr2", "pc", OPERAND_CONTROL + 2 },
00052   { "cr20", NULL, OPERAND_CONTROL + 20 },
00053   { "cr21", NULL, OPERAND_CONTROL + 21 },
00054   { "cr22", NULL, OPERAND_CONTROL + 22 },
00055   { "cr23", NULL, OPERAND_CONTROL + 23 },
00056   { "cr24", NULL, OPERAND_CONTROL + 24 },
00057   { "cr25", NULL, OPERAND_CONTROL + 25 },
00058   { "cr26", NULL, OPERAND_CONTROL + 26 },
00059   { "cr27", NULL, OPERAND_CONTROL + 27 },
00060   { "cr28", NULL, OPERAND_CONTROL + 28 },
00061   { "cr29", NULL, OPERAND_CONTROL + 29 },
00062   { "cr3", "bpc", OPERAND_CONTROL + 3 },
00063   { "cr30", NULL, OPERAND_CONTROL + 30 },
00064   { "cr31", NULL, OPERAND_CONTROL + 31 },
00065   { "cr32", NULL, OPERAND_CONTROL + 32 },
00066   { "cr33", NULL, OPERAND_CONTROL + 33 },
00067   { "cr34", NULL, OPERAND_CONTROL + 34 },
00068   { "cr35", NULL, OPERAND_CONTROL + 35 },
00069   { "cr36", NULL, OPERAND_CONTROL + 36 },
00070   { "cr37", NULL, OPERAND_CONTROL + 37 },
00071   { "cr38", NULL, OPERAND_CONTROL + 38 },
00072   { "cr39", NULL, OPERAND_CONTROL + 39 },
00073   { "cr4", "dpsw", OPERAND_CONTROL + 4 },
00074   { "cr40", NULL, OPERAND_CONTROL + 40 },
00075   { "cr41", NULL, OPERAND_CONTROL + 41 },
00076   { "cr42", NULL, OPERAND_CONTROL + 42 },
00077   { "cr43", NULL, OPERAND_CONTROL + 43 },
00078   { "cr44", NULL, OPERAND_CONTROL + 44 },
00079   { "cr45", NULL, OPERAND_CONTROL + 45 },
00080   { "cr46", NULL, OPERAND_CONTROL + 46 },
00081   { "cr47", NULL, OPERAND_CONTROL + 47 },
00082   { "cr48", NULL, OPERAND_CONTROL + 48 },
00083   { "cr49", NULL, OPERAND_CONTROL + 49 },
00084   { "cr5","dpc", OPERAND_CONTROL + 5 },
00085   { "cr50", NULL, OPERAND_CONTROL + 50 },
00086   { "cr51", NULL, OPERAND_CONTROL + 51 },
00087   { "cr52", NULL, OPERAND_CONTROL + 52 },
00088   { "cr53", NULL, OPERAND_CONTROL + 53 },
00089   { "cr54", NULL, OPERAND_CONTROL + 54 },
00090   { "cr55", NULL, OPERAND_CONTROL + 55 },
00091   { "cr56", NULL, OPERAND_CONTROL + 56 },
00092   { "cr57", NULL, OPERAND_CONTROL + 57 },
00093   { "cr58", NULL, OPERAND_CONTROL + 58 },
00094   { "cr59", NULL, OPERAND_CONTROL + 59 },
00095   { "cr6", NULL, OPERAND_CONTROL + 6 },
00096   { "cr60", NULL, OPERAND_CONTROL + 60 },
00097   { "cr61", NULL, OPERAND_CONTROL + 61 },
00098   { "cr62", NULL, OPERAND_CONTROL + 62 },
00099   { "cr63", NULL, OPERAND_CONTROL + 63 },
00100   { "cr7", "rpt_c", OPERAND_CONTROL + 7 },
00101   { "cr8", "rpt_s", OPERAND_CONTROL + 8 },
00102   { "cr9", "rpt_e", OPERAND_CONTROL + 9 },
00103   { "dpc", NULL, OPERAND_CONTROL + 5 },
00104   { "dpsw", NULL, OPERAND_CONTROL + 4 },
00105   { "eit_vb", NULL, OPERAND_CONTROL + 15 },
00106   { "f0", NULL, OPERAND_FLAG + 0 },
00107   { "f1", NULL, OPERAND_FLAG + 1 },
00108   { "f2", NULL, OPERAND_FLAG + 2 },
00109   { "f3", NULL, OPERAND_FLAG + 3 },
00110   { "f4", "s", OPERAND_FLAG + 4 },
00111   { "f5", "v", OPERAND_FLAG + 5 },
00112   { "f6", "va", OPERAND_FLAG + 6 },
00113   { "f7", "c", OPERAND_FLAG + 7 },
00114   { "iba", NULL, OPERAND_CONTROL + 14 },
00115   { "int_m", NULL, OPERAND_CONTROL + 17 },
00116   { "int_s", NULL, OPERAND_CONTROL + 16 },
00117   { "link", "r62", 62 },
00118   { "mod_e", NULL, OPERAND_CONTROL + 11 },
00119   { "mod_s", NULL, OPERAND_CONTROL + 10 },
00120   { "pc", NULL, OPERAND_CONTROL + 2 },
00121   { "psw", NULL, OPERAND_CONTROL },
00122   { "pswh", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 2 },
00123   { "pswl", NULL, OPERAND_CONTROL + MAX_CONTROL_REG + 1 },
00124   { "r0", NULL, 0 },
00125   { "r1", NULL, 1 },
00126   { "r10", NULL, 10 },
00127   { "r11", NULL, 11 },
00128   { "r12", NULL, 12 },
00129   { "r13", NULL, 13 },
00130   { "r14", NULL, 14 },
00131   { "r15", NULL, 15 },
00132   { "r16", NULL, 16 },
00133   { "r17", NULL, 17 },
00134   { "r18", NULL, 18 },
00135   { "r19", NULL, 19 },
00136   { "r2", NULL, 2 },
00137   { "r20", NULL, 20 },
00138   { "r21", NULL, 21 },
00139   { "r22", NULL, 22 },
00140   { "r23", NULL, 23 },
00141   { "r24", NULL, 24 },
00142   { "r25", NULL, 25 },
00143   { "r26", NULL, 26 },
00144   { "r27", NULL, 27 },
00145   { "r28", NULL, 28 },
00146   { "r29", NULL, 29 },
00147   { "r3", NULL, 3 },
00148   { "r30", NULL, 30 },
00149   { "r31", NULL, 31 },
00150   { "r32", NULL, 32 },
00151   { "r33", NULL, 33 },
00152   { "r34", NULL, 34 },
00153   { "r35", NULL, 35 },
00154   { "r36", NULL, 36 },
00155   { "r37", NULL, 37 },
00156   { "r38", NULL, 38 },
00157   { "r39", NULL, 39 },
00158   { "r4", NULL, 4 },
00159   { "r40", NULL, 40 },
00160   { "r41", NULL, 41 },
00161   { "r42", NULL, 42 },
00162   { "r43", NULL, 43 },
00163   { "r44", NULL, 44 },
00164   { "r45", NULL, 45 },
00165   { "r46", NULL, 46 },
00166   { "r47", NULL, 47 },
00167   { "r48", NULL, 48 },
00168   { "r49", NULL, 49 },
00169   { "r5", NULL, 5 },
00170   { "r50", NULL, 50 },
00171   { "r51", NULL, 51 },
00172   { "r52", NULL, 52 },
00173   { "r53", NULL, 53 },
00174   { "r54", NULL, 54 },
00175   { "r55", NULL, 55 },
00176   { "r56", NULL, 56 },
00177   { "r57", NULL, 57 },
00178   { "r58", NULL, 58 },
00179   { "r59", NULL, 59 },
00180   { "r6", NULL, 6 },
00181   { "r60", NULL, 60 },
00182   { "r61", NULL, 61 },
00183   { "r62", "link", 62 },
00184   { "r63", "sp", 63 },
00185   { "r7", NULL, 7 },
00186   { "r8", NULL, 8 },
00187   { "r9", NULL, 9 },
00188   { "rpt_c", NULL, OPERAND_CONTROL + 7 },
00189   { "rpt_e", NULL, OPERAND_CONTROL + 9 },
00190   { "rpt_s", NULL, OPERAND_CONTROL + 8 },
00191   { "s", NULL, OPERAND_FLAG + 4 },
00192   { "sp", NULL, 63 },
00193   { "v", NULL, OPERAND_FLAG + 5 },
00194   { "va", NULL, OPERAND_FLAG + 6 },
00195 };
00196 
00197 int 
00198 reg_name_cnt (void)
00199 {
00200   return sizeof (pre_defined_registers) / sizeof (struct pd_reg);
00201 }
00202 
00203 /* OPCODE TABLE.
00204    The format of this table is defined in opcode/d30v.h.  */
00205 
00206 const struct d30v_opcode d30v_opcode_table[] =
00207 {
00208   { "abs", IALU1, 0x8, { SHORT_U }, EITHER, 0, 0, 0 },
00209   { "add", IALU1, 0x0, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
00210   { "add2h", IALU1, 0x1, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
00211   { "addc", IALU1, 0x4, { SHORT_A, LONG }, EITHER, FLAG_C, FLAG_CVVA, 0 },
00212   { "addhlll", IALU1, 0x10, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00213   { "addhllh", IALU1, 0x11, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00214   { "addhlhl", IALU1, 0x12, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00215   { "addhlhh", IALU1, 0x13, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00216   { "addhhll", IALU1, 0x14, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00217   { "addhhlh", IALU1, 0x15, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00218   { "addhhhl", IALU1, 0x16, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00219   { "addhhhh", IALU1, 0x17, { SHORT_A, LONG }, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00220   { "adds", IALU1, 0x6, { SHORT_A, LONG }, EITHER, 0, FLAG_CVVA, 0 },
00221   { "adds2h", IALU1, 0x7, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00222   { "and", LOGIC, 0x18, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00223   { "andfg", LOGIC, 0x8, { SHORT_F }, EITHER, 0, 0, 0 },
00224   { "avg", IALU1, 0xa, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
00225   { "avg2h", IALU1, 0xb, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
00226   { "bclr", LOGIC, 0x3, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
00227   { "bnot", LOGIC, 0x1, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
00228   { "bra", BRA, 0, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JMP, 0, RELOC_PCREL },
00229   { "bratnz", BRA, 0x4, { SHORT_B3br, LONG_2br }, MU, FLAG_JMP, 0, RELOC_PCREL },
00230   { "bratzr", BRA, 0x4, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP, 0, RELOC_PCREL },
00231   { "bset", LOGIC, 0x2, { SHORT_A }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
00232   { "bsr", BRA, 0x2, { SHORT_B1, SHORT_B2r, LONG_Ur }, MU, FLAG_JSR, 0, RELOC_PCREL },
00233   { "bsrtnz", BRA, 0x6, { SHORT_B3br, LONG_2br }, MU, FLAG_JSR, 0, RELOC_PCREL },
00234   { "bsrtzr", BRA, 0x6, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR, 0, RELOC_PCREL },
00235   { "btst", LOGIC, 0, { SHORT_AF }, EITHER_BUT_PREFER_MU, 0, 0, 0 },
00236   { "cmp", LOGIC, 0xC, { SHORT_CMP, LONG_CMP }, EITHER, 0, 0, 0 },
00237   { "cmpu", LOGIC, 0xD, { SHORT_CMPU, LONG_CMP }, EITHER, 0, 0, 0 },
00238   { "dbra", BRA, 0x10, { SHORT_B3r, LONG_2r }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
00239   { "dbrai", BRA, 0x14, { SHORT_D2r, LONG_Dr }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
00240   { "dbsr", BRA, 0x12, { SHORT_B3r, LONG_2r }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
00241   { "dbsri", BRA, 0x16, { SHORT_D2r, LONG_Dr }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_PCREL },
00242   { "dbt", BRA, 0xb, { SHORT_NONE }, MU, FLAG_JSR, FLAG_LKR, 0 },
00243   { "djmp", BRA, 0x11, { SHORT_B3, LONG_2 }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
00244   { "djmpi", BRA, 0x15, { SHORT_D2, LONG_D }, MU, FLAG_JMP | FLAG_DELAY, FLAG_RP, RELOC_ABS },
00245   { "djsr", BRA, 0x13, { SHORT_B3, LONG_2 }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
00246   { "djsri", BRA, 0x17, { SHORT_D2, LONG_D }, MU, FLAG_JSR | FLAG_DELAY, FLAG_RP, RELOC_ABS },
00247   { "jmp", BRA, 0x1, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JMP, 0, RELOC_ABS },
00248   { "jmptnz", BRA, 0x5, { SHORT_B3b, LONG_2b }, MU, FLAG_JMP, 0, RELOC_ABS },
00249   { "jmptzr", BRA, 0x5, { SHORT_B3, LONG_2 }, MU, FLAG_JMP, 0, RELOC_ABS },
00250   { "joinll", IALU1, 0xC, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00251   { "joinlh", IALU1, 0xD, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00252   { "joinhl", IALU1, 0xE, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00253   { "joinhh", IALU1, 0xF, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00254   { "jsr", BRA, 0x3, { SHORT_B1, SHORT_B2, LONG_U }, MU, FLAG_JSR, 0, RELOC_ABS },
00255   { "jsrtnz", BRA, 0x7, { SHORT_B3b, LONG_2b }, MU, FLAG_JSR, 0, RELOC_ABS },
00256   { "jsrtzr", BRA, 0x7, { SHORT_B3, LONG_2 }, MU, FLAG_JSR, 0, RELOC_ABS },
00257   { "ld2h", IMEM, 0x3, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
00258   { "ld2w", IMEM, 0x6, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
00259   { "ld4bh", IMEM, 0x5, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0, 0 },
00260   { "ld4bhu", IMEM, 0xd, { SHORT_M2, LONG_M2 }, MU, FLAG_MEM, 0, 0 },
00261   { "ldb", IMEM, 0, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
00262   { "ldbu", IMEM, 0x9, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
00263   { "ldh", IMEM, 0x2, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
00264   { "ldhh", IMEM, 0x1, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
00265   { "ldhu", IMEM, 0xa, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
00266   { "ldw", IMEM, 0x4, { SHORT_M, LONG_M }, MU, FLAG_MEM, 0, 0 },
00267   { "mac0", IALU2, 0x14, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
00268   { "mac1", IALU2, 0x14, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
00269   { "macs0", IALU2, 0x15, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
00270   { "macs1", IALU2, 0x15, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
00271   { "moddec", IMEM, 0x7, { SHORT_MODDEC }, MU, 0, 0, 0 },
00272   { "modinc", IMEM, 0x7, { SHORT_MODINC }, MU, 0, 0, 0 },
00273   { "msub0", IALU2, 0x16, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
00274   { "msub1", IALU2, 0x16, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
00275   { "msubs0", IALU2, 0x17, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
00276   { "msubs1", IALU2, 0x17, { SHORT_A1 }, IU, FLAG_MUL32, 0, 0 },
00277   { "mul", IALU2, 0x10, { SHORT_A }, IU, FLAG_MUL32, 0, 0 },
00278   { "mul2h", IALU2, 0, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
00279   { "mulhxll", IALU2, 0x4, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
00280   { "mulhxlh", IALU2, 0x5, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
00281   { "mulhxhl", IALU2, 0x6, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
00282   { "mulhxhh", IALU2, 0x7, { SHORT_A }, IU, FLAG_MUL16, 0, 0 },
00283   { "mulx", IALU2, 0x18, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
00284   { "mulx2h", IALU2, 0x1, { SHORT_A2 }, IU, FLAG_MUL16, 0, 0 },
00285   { "mulxs", IALU2, 0x19, { SHORT_AA }, IU, FLAG_MUL32, 0, 0 },
00286   { "mvfacc", IALU2, 0x1f, { SHORT_RA }, IU, 0, 0, 0 },
00287   { "mvfsys", BRA, 0x1e, { SHORT_C1 }, MU, FLAG_ALL, FLAG_ALL, 0 },
00288   { "mvtacc", IALU2, 0xf, { SHORT_AR }, IU, 0, 0, 0 },
00289   { "mvtsys", BRA, 0xe, { SHORT_C2 }, MU, FLAG_ALL, FLAG_ALL, 0 },
00290   { "nop", BRA, 0xF, { SHORT_NONE }, EITHER, 0, 0, 0 },
00291   { "not", LOGIC, 0x19, { SHORT_U }, EITHER, 0, 0, 0 },
00292   { "notfg", LOGIC, 0x9, { SHORT_UF }, EITHER, 0, 0, 0 },
00293   { "or", LOGIC, 0x1a, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00294   { "orfg", LOGIC, 0xa, { SHORT_F }, EITHER, 0, 0, 0 },
00295   { "reit", BRA, 0x8, { SHORT_NONE }, MU, FLAG_SM | FLAG_JMP, FLAG_SM | FLAG_LKR, 0 },
00296   { "repeat", BRA, 0x18, { SHORT_D1r, LONG_2r }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
00297   { "repeati", BRA, 0x1a, { SHORT_D2Br, LONG_Dbr }, MU, FLAG_RP, FLAG_RP, RELOC_PCREL },
00298   { "rot", LOGIC, 0x14, { SHORT_A }, EITHER, 0, 0, 0 },
00299   { "rot2h", LOGIC, 0x15, { SHORT_A }, EITHER, 0, 0, 0 },
00300   { "rtd", BRA, 0xa, { SHORT_NONE }, MU, FLAG_JMP, FLAG_LKR, 0 },
00301   { "sat", IALU2, 0x8, { SHORT_A5 }, IU, 0, 0, 0 },
00302   { "sat2h", IALU2, 0x9, { SHORT_A5 }, IU, 0, 0, 0 },
00303   { "sathl", IALU2, 0x1c, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
00304   { "sathh", IALU2, 0x1d, { SHORT_A5 }, IU, FLAG_ADDSUBppp, 0, 0 },
00305   { "satz", IALU2, 0xa, { SHORT_A5 }, IU, 0, 0, 0 },
00306   { "satz2h", IALU2, 0xb, { SHORT_A5 }, IU, 0, 0, 0 },
00307   { "sra", LOGIC, 0x10, { SHORT_A }, EITHER, 0, 0, 0 },
00308   { "sra2h", LOGIC, 0x11, { SHORT_A }, EITHER, 0, 0, 0 },
00309   { "srahh", LOGIC, 0x5, { SHORT_A }, EITHER, 0, 0, 0 },
00310   { "srahl", LOGIC, 0x4, { SHORT_A }, EITHER, 0, 0, 0 },
00311   { "src", LOGIC, 0x16, { SHORT_A }, EITHER, FLAG_ADDSUBppp, 0, 0 },
00312   { "srl", LOGIC, 0x12, { SHORT_A }, EITHER, 0, 0, 0 },
00313   { "srl2h", LOGIC, 0x13, { SHORT_A }, EITHER, 0, 0, 0 },
00314   { "srlhh", LOGIC, 0x7, { SHORT_A }, EITHER, 0, 0, 0 },
00315   { "srlhl", LOGIC, 0x6, { SHORT_A }, EITHER, 0, 0, 0 },
00316   { "st2h", IMEM, 0x13, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
00317   { "st2w", IMEM, 0x16, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
00318   { "st4hb", IMEM, 0x15, { SHORT_M2, LONG_M2 }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
00319   { "stb", IMEM, 0x10, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
00320   { "sth", IMEM, 0x12, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
00321   { "sthh", IMEM, 0x11, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
00322   { "stw", IMEM, 0x14, { SHORT_M, LONG_M }, MU, 0, FLAG_MEM | FLAG_NOT_WITH_ADDSUBppp, 0 },
00323   { "sub", IALU1, 0x2, { SHORT_A, LONG}, EITHER, 0, FLAG_CVVA, 0 },
00324   { "sub2h", IALU1, 0x3, { SHORT_A, LONG}, EITHER, 0, 0, 0 },
00325   { "subb", IALU1, 0x5, { SHORT_A, LONG}, EITHER, FLAG_C, FLAG_CVVA, 0 },
00326   { "subhlll", IALU1, 0x18, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00327   { "subhllh", IALU1, 0x19, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00328   { "subhlhl", IALU1, 0x1a, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00329   { "subhlhh", IALU1, 0x1b, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00330   { "subhhll", IALU1, 0x1c, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00331   { "subhhlh", IALU1, 0x1d, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00332   { "subhhhl", IALU1, 0x1e, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00333   { "subhhhh", IALU1, 0x1f, { SHORT_A, LONG}, EITHER, FLAG_ADDSUBppp, FLAG_CVVA, 0 },
00334   { "trap", BRA, 0x9, { SHORT_B1, SHORT_T}, MU, FLAG_JSR, FLAG_SM | FLAG_LKR, 0 },
00335   { "xor", LOGIC, 0x1b, { SHORT_A, LONG }, EITHER, 0, 0, 0 },
00336   { "xorfg", LOGIC, 0xb, { SHORT_F }, EITHER, 0, 0, 0 },
00337   { NULL, 0, 0, { 0 }, 0, 0, 0, 0 },
00338 };
00339 
00340 
00341 /* Now define the operand types.
00342    Format is length, bits, position, flags.  */
00343 
00344 const struct d30v_operand d30v_operand_table[] =
00345 {
00346 #define UNUSED       (0)
00347   { 0, 0, 0, 0 },
00348 #define Ra    (UNUSED + 1)
00349   { 6, 6, 0, OPERAND_REG | OPERAND_DEST },
00350 #define Ra2   (Ra + 1)
00351   { 6, 6, 0, OPERAND_REG | OPERAND_DEST | OPERAND_2REG },
00352 #define Ra3   (Ra2 + 1)
00353   { 6, 6, 0, OPERAND_REG },
00354 #define Rb    (Ra3 + 1)
00355   { 6, 6, 6, OPERAND_REG },
00356 #define Rb2   (Rb + 1)
00357   { 6, 6, 6, OPERAND_REG | OPERAND_DEST },
00358 #define Rc    (Rb2 + 1)
00359   { 6, 6, 12, OPERAND_REG },
00360 #define Aa    (Rc + 1)
00361   { 6, 1, 0, OPERAND_ACC | OPERAND_REG | OPERAND_DEST },
00362 #define Ab    (Aa + 1)
00363   { 6, 1, 6, OPERAND_ACC | OPERAND_REG },
00364 #define IMM5  (Ab + 1)
00365   { 6, 5, 12, OPERAND_NUM },
00366 #define IMM5U (IMM5 + 1)
00367   { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used.  */
00368 #define IMM5S3        (IMM5U + 1)
00369   { 6, 5, 12, OPERAND_NUM | OPERAND_SIGNED }, /* Not used.  */
00370 #define IMM6  (IMM5S3 + 1)
00371   { 6, 6, 12, OPERAND_NUM | OPERAND_SIGNED },
00372 #define IMM6U (IMM6 + 1)
00373   { 6, 6, 0, OPERAND_NUM },
00374 #define IMM6U2        (IMM6U + 1)
00375   { 6, 6, 12, OPERAND_NUM },
00376 #define REL6S3        (IMM6U2 + 1)
00377   { 6, 6, 0, OPERAND_NUM | OPERAND_SHIFT | OPERAND_PCREL },
00378 #define REL12S3       (REL6S3 + 1)
00379   { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
00380 #define IMM12S3       (REL12S3 + 1)
00381   { 12, 12, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
00382 #define REL18S3       (IMM12S3 + 1)
00383   { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT | OPERAND_PCREL },
00384 #define IMM18S3       (REL18S3 + 1)
00385   { 18, 18, 12, OPERAND_NUM | OPERAND_SIGNED | OPERAND_SHIFT },
00386 #define REL32 (IMM18S3 + 1)
00387   { 32, 32, 0, OPERAND_NUM | OPERAND_PCREL },
00388 #define IMM32 (REL32 + 1)
00389   { 32, 32, 0, OPERAND_NUM },
00390 #define Fa    (IMM32 + 1)
00391   { 6, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST },
00392 #define Fb    (Fa + 1)
00393   { 6, 3, 6, OPERAND_REG | OPERAND_FLAG },
00394 #define Fc    (Fb + 1)
00395   { 6, 3, 12, OPERAND_REG | OPERAND_FLAG },
00396 #define ATSIGN       (Fc + 1)
00397   { 0, 0, 0, OPERAND_ATSIGN},
00398 #define ATPAR (ATSIGN + 1)  /* "@(" */
00399   { 0, 0, 0, OPERAND_ATPAR},
00400 #define PLUS  (ATPAR + 1)   /* Postincrement.  */
00401   { 0, 0, 0, OPERAND_PLUS},
00402 #define MINUS (PLUS + 1)    /* Postdecrement.  */
00403   { 0, 0, 0, OPERAND_MINUS},
00404 #define ATMINUS      (MINUS + 1)   /* Predecrement.  */
00405   { 0, 0, 0, OPERAND_ATMINUS},
00406 #define Ca    (ATMINUS + 1) /* Control register.  */
00407   { 6, 6, 0, OPERAND_REG | OPERAND_CONTROL | OPERAND_DEST},
00408 #define Cb    (Ca + 1)      /* Control register.  */
00409   { 6, 6, 6, OPERAND_REG | OPERAND_CONTROL},
00410 #define CC    (Cb + 1)      /* Condition code (CMPcc and CMPUcc).  */
00411   { 3, 3, -3, OPERAND_NAME},
00412 #define Fa2   (CC + 1)      /* Flag register (CMPcc and CMPUcc).  */
00413   { 3, 3, 0, OPERAND_REG | OPERAND_FLAG | OPERAND_DEST},
00414 #define Fake  (Fa2 + 1)     /* Place holder for "id" field in mvfsys and mvtsys.  */
00415   { 6, 2, 12, OPERAND_SPECIAL},
00416 };
00417 
00418 /* Now we need to define the instruction formats.  */
00419 
00420 const struct d30v_format d30v_format_table[] =
00421 {
00422   { 0, 0, { 0 } },
00423   { SHORT_M, 0, { Ra, ATPAR, Rb, Rc } },  /* Ra,@(Rb,Rc) */
00424   { SHORT_M, 1, { Ra, ATPAR, Rb, PLUS, Rc } },   /* Ra,@(Rb+,Rc) */
00425   { SHORT_M, 2, { Ra, ATPAR, Rb, IMM6 } },       /* Ra,@(Rb,imm6) */
00426   { SHORT_M, 3, { Ra, ATPAR, Rb, MINUS, Rc } },  /* Ra,@(Rb-,Rc) */
00427   { SHORT_M2, 0, { Ra2, ATPAR, Rb, Rc } },       /* Ra,@(Rb,Rc) */
00428   { SHORT_M2, 1, { Ra2, ATPAR, Rb, PLUS, Rc } },/* Ra,@(Rb+,Rc) */
00429   { SHORT_M2, 2, { Ra2, ATPAR, Rb, IMM6 } },     /* Ra,@(Rb,imm6) */
00430   { SHORT_M2, 3, { Ra2, ATPAR, Rb, MINUS, Rc } },/* Ra,@(Rb-,Rc) */
00431   { SHORT_A, 0, { Ra, Rb, Rc } },         /* Ra,Rb,Rc */
00432   { SHORT_A, 2, { Ra, Rb, IMM6 } },              /* Ra,Rb,imm6 */
00433   { SHORT_B1, 0, { Rc } },                /* Rc */
00434   { SHORT_B2, 2, { IMM18S3 } },                  /* imm18 */
00435   { SHORT_B2r, 2, { REL18S3 } },          /* rel18 */
00436   { SHORT_B3, 0, { Ra3, Rc } },                  /* Ra,Rc */
00437   { SHORT_B3, 2, { Ra3, IMM12S3 } },             /* Ra,imm12 */
00438   { SHORT_B3r, 0, { Ra3, Rc } },          /* Ra,Rc */
00439   { SHORT_B3r, 2, { Ra3, REL12S3 } },            /* Ra,rel12 */
00440   { SHORT_B3b, 1, { Ra3, Rc } },          /* Ra,Rc */
00441   { SHORT_B3b, 3, { Ra3, IMM12S3 } },            /* Ra,imm12 */
00442   { SHORT_B3br, 1, { Ra3, Rc } },         /* Ra,Rc */
00443   { SHORT_B3br, 3, { Ra3, REL12S3 } },           /* Ra,rel12 */
00444   { SHORT_D1r, 0, { Ra, Rc } },                  /* Ra,Rc */
00445   { SHORT_D1r, 2, { Ra, REL12S3 } },             /* Ra,rel12s3 */
00446   { SHORT_D2, 0, { REL6S3, Rc } },        /* rel6s3,Rc */
00447   { SHORT_D2, 2, { REL6S3, IMM12S3 } },          /* rel6s3,imm12s3 */
00448   { SHORT_D2r, 0, { REL6S3, Rc } },              /* rel6s3,Rc */
00449   { SHORT_D2r, 2, { REL6S3, REL12S3 } },  /* rel6s3,rel12s3 */
00450   { SHORT_D2Br, 0, { IMM6U, Rc } },              /* imm6u,Rc */
00451   { SHORT_D2Br, 2, { IMM6U, REL12S3 } },  /* imm6u,rel12s3 */
00452   { SHORT_U, 0, { Ra, Rb } },                    /* Ra,Rb */
00453   { SHORT_F, 0, { Fa, Fb, Fc } },         /* Fa,Fb,Fc  (orfg, xorfg) */
00454   { SHORT_F, 2, { Fa, Fb, IMM6 } },              /* Fa,Fb,imm6 */
00455   { SHORT_AF, 0, { Fa, Rb, Rc } },        /* Fa,Rb,Rc */
00456   { SHORT_AF, 2, { Fa, Rb, IMM6 } },             /* Fa,Rb,imm6 */
00457   { SHORT_T, 2, { IMM5 } },               /* imm5s3   (trap) */
00458   { SHORT_A5, 0, { Ra, Rb, Rc } },        /* Ra,Rb,Rc */
00459   { SHORT_A5, 2, { Ra, Rb, IMM5 } },             /* Ra,Rb,imm5    (sat*) */
00460   { SHORT_CMP, 0, { CC, Fa2, Rb, Rc} },          /* CC  Fa2,Rb,Rc */
00461   { SHORT_CMP, 2, { CC, Fa2, Rb, IMM6} }, /* CC  Fa2,Rb,imm6 */
00462   { SHORT_CMPU, 0, { CC, Fa2, Rb, Rc} },  /* CC  Fa2,Rb,Rc */
00463   { SHORT_CMPU, 2, { CC, Fa2, Rb, IMM6U2} },     /* CC  Fa2,Rb,imm6 */
00464   { SHORT_A1, 1, { Ra, Rb, Rc } },        /* Ra,Rb,Rc for MAC where a=1 */
00465   { SHORT_A1, 3, { Ra, Rb, IMM6 } },             /* Ra,Rb,imm6 for MAC where a=1 */
00466   { SHORT_AA, 0, { Aa, Rb, Rc } },        /* Aa,Rb,Rc */
00467   { SHORT_AA, 2, { Aa, Rb, IMM6 } },             /* Aa,Rb,imm6 */
00468   { SHORT_RA, 0, { Ra, Ab, Rc } },        /* Ra,Ab,Rc */
00469   { SHORT_RA, 2, { Ra, Ab, IMM6U2 } },           /* Ra,Ab,imm6u */
00470   { SHORT_MODINC, 1, { Rb2, IMM5 } },            /* Rb2,imm5 (modinc) */
00471   { SHORT_MODDEC, 3, { Rb2, IMM5 } },            /* Rb2,imm5 (moddec) */
00472   { SHORT_C1, 0, { Ra, Cb, Fake } },             /* Ra,Cb (mvfsys) */
00473   { SHORT_C2, 0, { Ca, Rb, Fake } },             /* Ca,Rb (mvtsys) */
00474   { SHORT_UF, 0, { Fa, Fb } },                   /* Fa,Fb  (notfg) */
00475   { SHORT_A2, 0, { Ra2, Rb, Rc } },              /* Ra2,Rb,Rc */
00476   { SHORT_A2, 2, { Ra2, Rb, IMM6 } },            /* Ra2,Rb,imm6 */
00477   { SHORT_NONE, 0, { 0 } },               /* no operands (nop, reit) */
00478   { SHORT_AR, 0, { Aa, Rb, Rc } },        /* Aa,Rb,Rc */
00479   { LONG, 2, { Ra, Rb, IMM32 } },         /* Ra,Rb,imm32 */
00480   { LONG_U, 2, { IMM32 } },               /* imm32 */
00481   { LONG_Ur, 2, { REL32 } },                     /* rel32 */
00482   { LONG_CMP, 2, { CC, Fa2, Rb, IMM32} }, /* CC  Fa2,Rb,imm32 */
00483   { LONG_M, 2, { Ra, ATPAR, Rb, IMM32 } },       /* Ra,@(Rb,imm32) */
00484   { LONG_M2, 2, { Ra2, ATPAR, Rb, IMM32 } },     /* Ra,@(Rb,imm32) */
00485   { LONG_2, 2, { Ra3, IMM32 } },          /* Ra,imm32 */
00486   { LONG_2r, 2, { Ra3, REL32 } },         /* Ra,rel32 */
00487   { LONG_2b, 3, { Ra3, IMM32 } },         /* Ra,imm32 */
00488   { LONG_2br, 3, { Ra3, REL32 } },        /* Ra,rel32 */
00489   { LONG_D, 2, { REL6S3, IMM32 } },              /* rel6s3,imm32 */
00490   { LONG_Dr, 2, { REL6S3, REL32 } },             /* rel6s3,rel32 */
00491   { LONG_Dbr, 2, { IMM6U, REL32 } },             /* imm6,rel32 */
00492   { 0, 0, { 0 } },
00493 };
00494 
00495 const char *d30v_ecc_names[] =
00496 {
00497   "al",
00498   "tx",
00499   "fx",
00500   "xt",
00501   "xf",
00502   "tt",
00503   "tf",
00504   "res"
00505 };
00506 
00507 const char *d30v_cc_names[] =
00508 {
00509   "eq",
00510   "ne",
00511   "gt",
00512   "ge",
00513   "lt",
00514   "le",
00515   "ps",
00516   "ng",
00517   NULL
00518 };