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cell-binutils  2.17cvs20070401
d10v-opc.c
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00001 /* d10v-opc.c -- D10V opcode list
00002    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
00003    Written by Martin Hunt, Cygnus Support
00004 
00005 This file is part of GDB, GAS, and the GNU binutils.
00006 
00007 GDB, GAS, and the GNU binutils are free software; you can redistribute
00008 them and/or modify them under the terms of the GNU General Public
00009 License as published by the Free Software Foundation; either version
00010 2, or (at your option) any later version.
00011 
00012 GDB, GAS, and the GNU binutils are distributed in the hope that they
00013 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00014 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00015 the GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this file; see the file COPYING.  If not, write to the Free
00019 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00020 
00021 #include <stdio.h>
00022 #include "sysdep.h"
00023 #include "opcode/d10v.h"
00024 
00025 
00026 /*   The table is sorted. Suitable for searching by a binary search. */
00027 const struct pd_reg d10v_predefined_registers[] =
00028 {
00029   { "a0", NULL, OPERAND_ACC0+0 },
00030   { "a1", NULL, OPERAND_ACC1+1 },
00031   { "bpc", NULL, OPERAND_CONTROL+3 },
00032   { "bpsw", NULL, OPERAND_CONTROL+1 },
00033   { "c", NULL, OPERAND_CFLAG+3 },
00034   { "cr0", "psw", OPERAND_CONTROL },
00035   { "cr1", "bpsw", OPERAND_CONTROL+1 },
00036   { "cr10", "mod_s", OPERAND_CONTROL+10 },
00037   { "cr11", "mod_e", OPERAND_CONTROL+11 },
00038   { "cr12", NULL, OPERAND_CONTROL+12 },
00039   { "cr13", NULL, OPERAND_CONTROL+13 },
00040   { "cr14", "iba", OPERAND_CONTROL+14 },
00041   { "cr15", NULL, OPERAND_CONTROL+15 },
00042   { "cr2", "pc", OPERAND_CONTROL+2 },
00043   { "cr3", "bpc", OPERAND_CONTROL+3 },
00044   { "cr4", "dpsw", OPERAND_CONTROL+4 },
00045   { "cr5", "dpc", OPERAND_CONTROL+5 },
00046   { "cr6", NULL, OPERAND_CONTROL+6 },
00047   { "cr7", "rpt_c", OPERAND_CONTROL+7 },
00048   { "cr8", "rpt_s", OPERAND_CONTROL+8 },
00049   { "cr9", "rpt_e", OPERAND_CONTROL+9 },
00050   { "dpc", NULL, OPERAND_CONTROL+5 },
00051   { "dpsw", NULL, OPERAND_CONTROL+4 },
00052   { "f0", NULL, OPERAND_FFLAG+0 },
00053   { "f1", NULL, OPERAND_FFLAG+1 },
00054   { "iba", NULL, OPERAND_CONTROL+14 },
00055   { "link", "r13", OPERAND_GPR+13 },
00056   { "mod_e", NULL, OPERAND_CONTROL+11 },
00057   { "mod_s", NULL, OPERAND_CONTROL+10 },
00058   { "pc", NULL, OPERAND_CONTROL+2 },
00059   { "psw", NULL, OPERAND_CONTROL+0 },
00060   { "r0", NULL, OPERAND_GPR+0 },
00061   { "r0-r1", NULL, OPERAND_GPR+0},
00062   { "r1", NULL, OPERAND_GPR+1 },
00063   { "r1", NULL, OPERAND_GPR+1 },
00064   { "r10", NULL, OPERAND_GPR+10 },
00065   { "r10-r11", NULL, OPERAND_GPR+10 },
00066   { "r11", NULL, OPERAND_GPR+11 },
00067   { "r12", NULL, OPERAND_GPR+12 },
00068   { "r12-r13", NULL, OPERAND_GPR+12 },
00069   { "r13", NULL, OPERAND_GPR+13 },
00070   { "r14", NULL, OPERAND_GPR+14 },
00071   { "r14-r15", NULL, OPERAND_GPR+14 },
00072   { "r15", "sp", OPERAND_SP|(OPERAND_GPR+15) },
00073   { "r2", NULL, OPERAND_GPR+2 },
00074   { "r2-r3", NULL, OPERAND_GPR+2 },
00075   { "r3", NULL, OPERAND_GPR+3 },
00076   { "r4", NULL, OPERAND_GPR+4 },
00077   { "r4-r5", NULL, OPERAND_GPR+4 },
00078   { "r5", NULL, OPERAND_GPR+5 },
00079   { "r6", NULL, OPERAND_GPR+6 },
00080   { "r6-r7", NULL, OPERAND_GPR+6 },
00081   { "r7", NULL, OPERAND_GPR+7 },
00082   { "r8", NULL, OPERAND_GPR+8 },
00083   { "r8-r9", NULL, OPERAND_GPR+8 },
00084   { "r9", NULL, OPERAND_GPR+9 },
00085   { "rpt_c", NULL, OPERAND_CONTROL+7 },
00086   { "rpt_e", NULL, OPERAND_CONTROL+9 },
00087   { "rpt_s", NULL, OPERAND_CONTROL+8 },
00088   { "sp", NULL, OPERAND_SP|(OPERAND_GPR+15) },
00089 };
00090 
00091 int 
00092 d10v_reg_name_cnt()
00093 {
00094   return (sizeof(d10v_predefined_registers) / sizeof(struct pd_reg));
00095 }
00096 
00097 const struct d10v_operand d10v_operands[] =
00098 {
00099 #define UNUSED       (0)
00100   { 0, 0, 0 },
00101 #define RSRC  (UNUSED + 1)
00102   { 4, 1, OPERAND_GPR|OPERAND_REG },
00103 #define RSRC_SP (RSRC + 1)
00104   { 4, 1, OPERAND_SP|OPERAND_GPR|OPERAND_REG },
00105 #define RSRC_NOSP (RSRC_SP + 1)
00106   { 4, 1, OPERAND_NOSP|OPERAND_GPR|OPERAND_REG },
00107 #define RDST  (RSRC_NOSP + 1)
00108   { 4, 5, OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
00109 #define ASRC  (RDST + 1)
00110   { 1, 4, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
00111 #define ASRC0ONLY (ASRC + 1)
00112   { 1, 4, OPERAND_ACC0|OPERAND_REG },
00113 #define ADST  (ASRC0ONLY + 1)
00114   { 1, 8, OPERAND_DEST|OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
00115 #define RSRCE (ADST + 1)
00116   { 4, 1, OPERAND_EVEN|OPERAND_GPR|OPERAND_REG },
00117 #define RDSTE (RSRCE + 1)
00118   { 4, 5, OPERAND_EVEN|OPERAND_DEST|OPERAND_GPR|OPERAND_REG },
00119 #define NUM16 (RDSTE + 1)
00120   { 16, 0, OPERAND_NUM|OPERAND_SIGNED },
00121 #define NUM3  (NUM16 + 1)                 /* rac, rachi */
00122   { 3, 1, OPERAND_NUM|OPERAND_SIGNED|RESTRICTED_NUM3 },
00123 #define NUM4  (NUM3 + 1)
00124   { 4, 1, OPERAND_NUM|OPERAND_SIGNED },
00125 #define UNUM4 (NUM4 + 1)
00126   { 4, 1, OPERAND_NUM },
00127 #define UNUM4S       (UNUM4 + 1)                 /* addi, slli, srai, srli, subi */
00128   { 4, 1, OPERAND_NUM|OPERAND_SHIFT },
00129 #define UNUM8 (UNUM4S + 1)                /* repi */
00130   { 8, 16, OPERAND_NUM },
00131 #define UNUM16       (UNUM8 + 1)                 /* cmpui */
00132   { 16, 0, OPERAND_NUM },
00133 #define ANUM16       (UNUM16 + 1)
00134   { 16, 0, OPERAND_ADDR|OPERAND_SIGNED },
00135 #define ANUM8 (ANUM16 + 1)
00136   { 8, 0, OPERAND_ADDR|OPERAND_SIGNED },
00137 #define ASRC2 (ANUM8 + 1)
00138   { 1, 8, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
00139 #define RSRC2 (ASRC2 + 1)
00140   { 4, 5, OPERAND_GPR|OPERAND_REG },
00141 #define RSRC2E       (RSRC2 + 1)
00142   { 4, 5, OPERAND_GPR|OPERAND_REG|OPERAND_EVEN },
00143 #define ASRC0 (RSRC2E + 1)
00144   { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG },
00145 #define ADST0 (ASRC0 + 1)
00146   { 1, 0, OPERAND_ACC0|OPERAND_ACC1|OPERAND_REG|OPERAND_DEST },
00147 #define FFSRC (ADST0 + 1)
00148   { 2, 1, OPERAND_REG | OPERAND_FFLAG },
00149 #define CFSRC (FFSRC + 1)
00150   { 2, 1, OPERAND_REG | OPERAND_CFLAG },
00151 #define FDST  (CFSRC + 1)
00152   { 1, 5, OPERAND_REG | OPERAND_FFLAG | OPERAND_DEST},
00153 #define ATSIGN       (FDST + 1)
00154   { 0, 0, OPERAND_ATSIGN},
00155 #define ATPAR (ATSIGN + 1)  /* "@(" */
00156   { 0, 0, OPERAND_ATPAR},
00157 #define PLUS  (ATPAR + 1)   /* postincrement */
00158   { 0, 0, OPERAND_PLUS},
00159 #define MINUS (PLUS + 1)    /* postdecrement */
00160   { 0, 0, OPERAND_MINUS},
00161 #define ATMINUS      (MINUS + 1)   /* predecrement */
00162   { 0, 0, OPERAND_ATMINUS},
00163 #define CSRC  (ATMINUS + 1) /* control register */
00164   { 4, 1, OPERAND_REG|OPERAND_CONTROL},
00165 #define CDST  (CSRC + 1)    /* control register */
00166   { 4, 5, OPERAND_REG|OPERAND_CONTROL|OPERAND_DEST},
00167 };
00168 
00169 const struct d10v_opcode d10v_opcodes[] = {
00170   { "abs", SHORT_2, 1, EITHER, PAR|WF0, 0x4607, 0x7e1f, { RDST } },
00171   { "abs", SHORT_2, 1, IU, PAR|WF0, 0x5607, 0x7eff, { ADST } },
00172   { "add", SHORT_2, 1, EITHER, PAR|WCAR, 0x0200, 0x7e01, { RDST, RSRC } },
00173   { "add", SHORT_2, 1, IU, PAR, 0x1201, 0x7ee3, { ADST, RSRCE } },
00174   { "add", SHORT_2, 1, IU, PAR, 0x1203, 0x7eef, { ADST, ASRC } },
00175   { "add2w", SHORT_2, 2, IU, PAR|WCAR, 0x1200, 0x7e23, { RDSTE, RSRCE } },
00176   { "add3", LONG_L, 1, MU, SEQ|WCAR, 0x1000000, 0x3f000000, { RDST, RSRC, NUM16 } },
00177   { "addac3", LONG_R, 1, IU, SEQ, 0x17000200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
00178   { "addac3", LONG_R, 1, IU, SEQ, 0x17000202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
00179   { "addac3s", LONG_R, 1, IU, SEQ, 0x17001200, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
00180   { "addac3s", LONG_R, 1, IU, SEQ, 0x17001202, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
00181   { "addi", SHORT_2, 1, EITHER, PAR|WCAR,  0x201, 0x7e01, { RDST, UNUM4S } },
00182   { "and", SHORT_2, 1, EITHER, PAR, 0xc00, 0x7e01, { RDST, RSRC } },
00183   { "and3", LONG_L, 1, MU, SEQ, 0x6000000, 0x3f000000, { RDST, RSRC, NUM16 } },
00184   { "bclri", SHORT_2, 1, IU, PAR, 0xc01, 0x7e01, { RDST, UNUM4 } },
00185   { "bl", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
00186   { "bl.s", SHORT_B, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4900, 0x7f00, { ANUM8 } },
00187   { "bl.l", LONG_B, 3, MU, BRANCH_LINK|SEQ, 0x24800000, 0x3fff0000, { ANUM16 } },
00188   { "bnoti", SHORT_2, 1, IU, PAR, 0xa01, 0x7e01, { RDST, UNUM4 } },
00189   { "bra", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
00190   { "bra.s", SHORT_B, 3, MU, ALONE|BRANCH|PAR, 0x4800, 0x7f00, { ANUM8 } },
00191   { "bra.l", LONG_B, 3, MU, BRANCH|SEQ, 0x24000000, 0x3fff0000, { ANUM16 } },
00192   { "brf0f", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
00193   { "brf0f.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4a00, 0x7f00, { ANUM8 } },
00194   { "brf0f.l", LONG_B, 3, MU, SEQ, 0x25000000, 0x3fff0000, { ANUM16 } },
00195   { "brf0t", OPCODE_FAKE, 0, 0, 0, 0, 0, { 0, 8, 16, 0 } },
00196   { "brf0t.s", SHORT_B, 3, MU, BRANCH|PAR|RF0, 0x4b00, 0x7f00, { ANUM8 } },
00197   { "brf0t.l", LONG_B, 3, MU, SEQ, 0x25800000, 0x3fff0000, { ANUM16 } },
00198   { "bseti", SHORT_2, 1, IU, PAR, 0x801, 0x7e01, { RDST, UNUM4 } },
00199   { "btsti", SHORT_2, 1, IU, PAR|WF0, 0xe01, 0x7e01, { RSRC2, UNUM4 } },
00200   { "clrac", SHORT_2, 1, IU, PAR, 0x5601, 0x7eff, { ADST } },
00201   { "cmp", SHORT_2, 1, EITHER, PAR|WF0, 0x600, 0x7e01, { RSRC2, RSRC } },
00202   { "cmp", SHORT_2, 1, IU, PAR|WF0, 0x1603, 0x7eef, { ASRC2, ASRC } },
00203   { "cmpeq", SHORT_2, 1, EITHER, PAR|WF0, 0x400, 0x7e01, { RSRC2, RSRC } },
00204   { "cmpeq", SHORT_2, 1, IU, PAR|WF0, 0x1403, 0x7eef, { ASRC2, ASRC } },
00205   { "cmpeqi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
00206   { "cmpeqi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x401, 0x7e01, { RSRC2, NUM4 } },
00207   { "cmpeqi.l", LONG_L, 1, MU, SEQ, 0x2000000, 0x3f0f0000, { RSRC2, NUM16 } },
00208   { "cmpi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
00209   { "cmpi.s", SHORT_2, 1, EITHER, PAR|WF0, 0x601, 0x7e01, { RSRC2, NUM4 } },
00210   { "cmpi.l", LONG_L, 1, MU, SEQ, 0x3000000, 0x3f0f0000, { RSRC2, NUM16 } },
00211   { "cmpu", SHORT_2, 1, EITHER, PAR|WF0, 0x4600, 0x7e01, { RSRC2, RSRC } },
00212   { "cmpui", LONG_L, 1, MU, SEQ, 0x23000000, 0x3f0f0000, { RSRC2, UNUM16 } },
00213   { "cpfg", SHORT_2, 1, MU, PAR, 0x4e0f, 0x7fdf, { FDST, CFSRC } },
00214   { "cpfg", SHORT_2, 1, MU, PAR, 0x4e09, 0x7fd9, { FDST, FFSRC } },
00215   { "dbt", SHORT_2, 5, MU, ALONE|PAR, 0x5f20, 0x7fff, { 0 } },
00216   { "divs", LONG_L, 1, BOTH, SEQ, 0x14002800, 0x3f10fe21, { RDSTE, RSRC } },
00217   { "exef0f", SHORT_2, 1, EITHER, PARONLY, 0x4e04, 0x7fff, { 0 } },
00218   { "exef0t", SHORT_2, 1, EITHER, PARONLY, 0x4e24, 0x7fff, { 0 } },
00219   { "exef1f", SHORT_2, 1, EITHER, PARONLY, 0x4e40, 0x7fff, { 0 } },
00220   { "exef1t", SHORT_2, 1, EITHER, PARONLY, 0x4e42, 0x7fff, { 0 } },
00221   { "exefaf", SHORT_2, 1, EITHER, PARONLY, 0x4e00, 0x7fff, { 0 } },
00222   { "exefat", SHORT_2, 1, EITHER, PARONLY, 0x4e02, 0x7fff, { 0 } },
00223   { "exetaf", SHORT_2, 1, EITHER, PARONLY, 0x4e20, 0x7fff, { 0 } },
00224   { "exetat", SHORT_2, 1, EITHER, PARONLY, 0x4e22, 0x7fff, { 0 } },
00225   { "exp", LONG_R, 1, IU, SEQ, 0x15002a00, 0x3ffffe03, { RDST, RSRCE } },
00226   { "exp", LONG_R, 1, IU, SEQ, 0x15002a02, 0x3ffffe0f, { RDST, ASRC } },
00227   { "jl", SHORT_2, 3, MU, ALONE|BRANCH_LINK|PAR, 0x4d00, 0x7fe1, { RSRC } },
00228   { "jmp", SHORT_2, 3, MU, ALONE|BRANCH|PAR, 0x4c00, 0x7fe1, { RSRC } },
00229   { "ld", LONG_L, 1, MU, SEQ, 0x30000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
00230   { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } },
00231   { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } },
00232   { "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } },
00233   { "ld", LONG_L, 1, MU, SEQ, 0x32010000, 0x3f0f0000, { RDST, ATSIGN, NUM16 } },
00234   { "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } },
00235   { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } },
00236   { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } },
00237   { "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } },
00238   { "ld2w", LONG_L, 1, MU, SEQ, 0x33010000, 0x3f1f0000, { RDSTE, ATSIGN, NUM16 } },
00239   { "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
00240   { "ldb", SHORT_2, 1, MU, PAR|RMEM, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } },
00241   { "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
00242   { "ldi.s", SHORT_2, 1, EITHER, PAR|RMEM, 0x4001, 0x7e01 , { RDST, NUM4 } },
00243   { "ldi.l", LONG_L, 1, MU, SEQ, 0x20000000, 0x3f0f0000, { RDST, NUM16 } },
00244   { "ldub", LONG_L, 1, MU, SEQ, 0x39000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
00245   { "ldub", SHORT_2, 1, MU, PAR|RMEM, 0x7200, 0x7e01, { RDST, ATSIGN, RSRC } },
00246   { "mac", SHORT_2, 1, IU, PAR, 0x2a00, 0x7e00, { ADST0, RSRC2, RSRC } },
00247   { "macsu", SHORT_2, 1, IU, PAR, 0x1a00, 0x7e00, { ADST0, RSRC2, RSRC } },
00248   { "macu", SHORT_2, 1, IU, PAR, 0x3a00, 0x7e00, { ADST0, RSRC2, RSRC } },
00249   { "max", SHORT_2, 1, IU, PAR|WF0, 0x2600, 0x7e01, { RDST, RSRC } },
00250   { "max", SHORT_2, 1, IU, PAR|WF0, 0x3600, 0x7ee3, { ADST, RSRCE } },
00251   { "max", SHORT_2, 1, IU, PAR|WF0, 0x3602, 0x7eef, { ADST, ASRC } },
00252   { "min", SHORT_2, 1, IU, PAR|WF0, 0x2601, 0x7e01 , { RDST, RSRC } },
00253   { "min", SHORT_2, 1, IU, PAR|WF0, 0x3601, 0x7ee3 , { ADST, RSRCE } },
00254   { "min", SHORT_2, 1, IU, PAR|WF0, 0x3603, 0x7eef, { ADST, ASRC } },
00255   { "msb", SHORT_2, 1, IU, PAR, 0x2800, 0x7e00, { ADST0, RSRC2, RSRC } },
00256   { "msbsu", SHORT_2, 1, IU, PAR, 0x1800, 0x7e00, { ADST0, RSRC2, RSRC } },
00257   { "msbu", SHORT_2, 1, IU, PAR, 0x3800, 0x7e00, { ADST0, RSRC2, RSRC } },
00258   { "mul", SHORT_2, 1, IU, PAR, 0x2e00, 0x7e01 , { RDST, RSRC } },
00259   { "mulx", SHORT_2, 1, IU, PAR, 0x2c00, 0x7e00, { ADST0, RSRC2, RSRC } },
00260   { "mulxsu", SHORT_2, 1, IU, PAR, 0x1c00, 0x7e00, { ADST0, RSRC2, RSRC } },
00261   { "mulxu", SHORT_2, 1, IU, PAR, 0x3c00, 0x7e00, { ADST0, RSRC2, RSRC } },
00262   { "mv", SHORT_2, 1, EITHER, PAR, 0x4000, 0x7e01, { RDST, RSRC } },
00263   { "mv2w", SHORT_2, 1, IU, PAR, 0x5000, 0x7e23, { RDSTE, RSRCE } },
00264   { "mv2wfac", SHORT_2, 1, IU, PAR, 0x3e00, 0x7e2f, { RDSTE, ASRC } },
00265   { "mv2wtac", SHORT_2, 1, IU, PAR, 0x3e01, 0x7ee3, { RSRCE, ADST } },
00266   { "mvac", SHORT_2, 1, IU, PAR, 0x3e03, 0x7eef, { ADST, ASRC } },
00267   { "mvb", SHORT_2, 1, IU, PAR, 0x5400, 0x7e01, { RDST, RSRC } },
00268   { "mvf0f", SHORT_2, 1, EITHER, PAR|RF0, 0x4400, 0x7e01, { RDST, RSRC } },
00269   { "mvf0t", SHORT_2, 1, EITHER, PAR|RF0, 0x4401, 0x7e01, { RDST, RSRC } },
00270   { "mvfacg", SHORT_2, 1, IU, PAR, 0x1e04, 0x7e0f, { RDST, ASRC } },
00271   { "mvfachi", SHORT_2, 1, IU, PAR, 0x1e00, 0x7e0f, { RDST, ASRC } },
00272   { "mvfaclo", SHORT_2, 1, IU, PAR, 0x1e02, 0x7e0f, { RDST, ASRC } },
00273   { "mvfc", SHORT_2, 1, MU, PAR, 0x5200, 0x7e01, { RDST, CSRC } },
00274   { "mvtacg", SHORT_2, 1, IU, PAR, 0x1e41, 0x7ee1, { RSRC, ADST } },
00275   { "mvtachi", SHORT_2, 1, IU, PAR, 0x1e01, 0x7ee1, { RSRC, ADST } },
00276   { "mvtaclo", SHORT_2, 1, IU, PAR, 0x1e21, 0x7ee1, { RSRC, ADST } },
00277   { "mvtc", SHORT_2, 1, MU, PAR, 0x5600, 0x7e01, { RSRC, CDST } },
00278   { "mvub", SHORT_2, 1, IU, PAR, 0x5401, 0x7e01, { RDST, RSRC } },
00279   { "neg", SHORT_2, 1, EITHER, PAR, 0x4605, 0x7e1f, { RDST } },
00280   { "neg", SHORT_2, 1, IU, PAR, 0x5605, 0x7eff, { ADST } },
00281   { "nop", SHORT_2, 1, EITHER, PAR, 0x5e00, 0x7fff, { 0 } },
00282   { "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } },
00283   { "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } },
00284   { "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } },
00285   /* Special case. sac&sachi must occur before rac&rachi because they have
00286      intersecting masks! The masks for rac&rachi will match sac&sachi but
00287      not the other way around.
00288    */
00289   { "sac", SHORT_2, 1, IU, PAR|RF0|WF0, 0x5209, 0x7e2f, { RDSTE, ASRC } },
00290   { "sachi", SHORT_2, 1, IU, PAR|RF0|WF0, 0x4209, 0x7e0f, { RDST, ASRC } },
00291   { "rac", SHORT_2, 1, IU, PAR|WF0, 0x5201, 0x7e21, { RDSTE, ASRC0ONLY, NUM3 } },
00292   { "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } },
00293   { "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } },
00294   { "repi", LONG_L, 2, MU, SEQ, 0x2f000000, 0x3f000000, { UNUM8, ANUM16 } },
00295   { "rtd", SHORT_2, 3, MU, ALONE|PAR, 0x5f60, 0x7fff, { 0 } },
00296   { "rte", SHORT_2, 3, MU, ALONE|PAR, 0x5f40, 0x7fff, { 0 } },
00297   { "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } },
00298   { "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } },
00299   { "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } },
00300   { "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } },
00301   { "sleep", SHORT_2, 1, MU, ALONE|PAR, 0x5fc0, 0x7fff, { 0 } },
00302   { "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } },
00303   { "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } },
00304   { "slli", SHORT_2, 1, IU, PAR, 0x2201, 0x7e01, { RDST, UNUM4 } },
00305   { "slli", SHORT_2, 1, IU, PAR, 0x3201, 0x7ee1, { ADST, UNUM4S } },
00306   { "slx", SHORT_2, 1, IU, PAR|RF0, 0x460b, 0x7e1f, { RDST } },
00307   { "sra", SHORT_2, 1, IU, PAR, 0x2400, 0x7e01, { RDST, RSRC } },
00308   { "sra", SHORT_2, 1, IU, PAR, 0x3400, 0x7ee1, { ADST, RSRC } },
00309   { "srai", SHORT_2, 1, IU, PAR, 0x2401, 0x7e01, { RDST, UNUM4 } },
00310   { "srai", SHORT_2, 1, IU, PAR, 0x3401, 0x7ee1, { ADST, UNUM4S } },
00311   { "srl", SHORT_2, 1, IU, PAR, 0x2000, 0x7e01, { RDST, RSRC } },
00312   { "srl", SHORT_2, 1, IU, PAR, 0x3000, 0x7ee1, { ADST, RSRC } },
00313   { "srli", SHORT_2, 1, IU, PAR, 0x2001, 0x7e01, { RDST, UNUM4 } },
00314   { "srli", SHORT_2, 1, IU, PAR, 0x3001, 0x7ee1, { ADST, UNUM4S } },
00315   { "srx", SHORT_2, 1, IU, PAR|RF0, 0x4609, 0x7e1f, { RDST } },
00316   { "st", LONG_L, 1, MU, SEQ, 0x34000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
00317   { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
00318   { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC_SP } },
00319   { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
00320   { "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC_NOSP, MINUS } },
00321   { "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } },
00322   { "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
00323   { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
00324   { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC_SP } },
00325   { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
00326   { "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC_NOSP, MINUS } },
00327   { "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } },
00328   { "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
00329   { "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
00330   { "stop", SHORT_2, 1, MU, ALONE|PAR, 0x5fe0, 0x7fff, { 0 } },
00331   { "sub", SHORT_2, 1, EITHER, PAR|WCAR, 0x0, 0x7e01, { RDST, RSRC } },
00332   { "sub", SHORT_2, 1, IU, PAR, 0x1001, 0x7ee3, { ADST, RSRC } },
00333   { "sub", SHORT_2, 1, IU, PAR, 0x1003, 0x7eef, { ADST, ASRC } },
00334   { "sub2w", SHORT_2, 1, IU, PAR|WCAR, 0x1000, 0x7e23, { RDSTE, RSRCE } },
00335   { "subac3", LONG_R, 1, IU, SEQ, 0x17000000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
00336   { "subac3", LONG_R, 1, IU, SEQ, 0x17000002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
00337   { "subac3s", LONG_R, 1, IU, SEQ, 0x17001000, 0x3ffffe22, { RDSTE, RSRCE, ASRC0 } },
00338   { "subac3s", LONG_R, 1, IU, SEQ, 0x17001002, 0x3ffffe2e, { RDSTE, ASRC, ASRC0 } },
00339   { "subi", SHORT_2, 1, EITHER, PAR, 0x1, 0x7e01, { RDST, UNUM4S } },
00340   { "trap", SHORT_2, 5, MU, ALONE|BRANCH_LINK|PAR, 0x5f00, 0x7fe1, { UNUM4 } },
00341   { "tst0i", LONG_L, 1, MU, SEQ, 0x7000000, 0x3f0f0000, { RSRC2, NUM16 } },
00342   { "tst1i", LONG_L, 1, MU, SEQ, 0xf000000, 0x3f0f0000, { RSRC2, NUM16 } },
00343   { "wait", SHORT_2, 1, MU, ALONE|PAR, 0x5f80, 0x7fff, { 0 } },
00344   { "xor", SHORT_2, 1, EITHER, PAR, 0xa00, 0x7e01, { RDST, RSRC } },
00345   { "xor3", LONG_L, 1, MU, SEQ, 0x5000000, 0x3f000000, { RDST, RSRC, NUM16 } },
00346   { 0, 0, 0, 0, 0, 0, 0, { 0 } },
00347 };
00348 
00349