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cell-binutils  2.17cvs20070401
crx-opc.c
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00001 /* crx-opc.c -- Table of opcodes for the CRX processor.
00002    Copyright 2004 Free Software Foundation, Inc.
00003    Contributed by Tomer Levi NSC, Israel.
00004    Originally written for GAS 2.12 by Tomer Levi.
00005 
00006    This file is part of GAS, GDB and the GNU binutils.
00007 
00008    GAS, GDB, and GNU binutils is free software; you can redistribute it
00009    and/or modify it under the terms of the GNU General Public License as
00010    published by the Free Software Foundation; either version 2, or (at your
00011    option) any later version.
00012 
00013    GAS, GDB, and GNU binutils are distributed in the hope that they will be
00014    useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
00015    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00016    GNU General Public License for more details.
00017 
00018    You should have received a copy of the GNU General Public License
00019    along with this program; if not, write to the Free Software
00020    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00021 
00022 #include <stdio.h>
00023 #include "libiberty.h"
00024 #include "symcat.h"
00025 #include "opcode/crx.h"
00026 
00027 const inst crx_instruction[] =
00028 {
00029 /* Create an arithmetic instruction - INST[bw].  */
00030 #define  ARITH_BYTE_INST(NAME, OPC) \
00031   /* opc8 cst4 r */                                                   \
00032   {NAME, 1, OPC,  24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}},     \
00033   /* opc8 i16 r */                                                    \
00034   {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}},  \
00035   /* opc8 r r */                                                      \
00036   {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
00037 
00038   ARITH_BYTE_INST ("addub", 0x0),
00039   ARITH_BYTE_INST ("addb",  0x1),
00040   ARITH_BYTE_INST ("addcb", 0x2),
00041   ARITH_BYTE_INST ("andb",  0x3),
00042   ARITH_BYTE_INST ("cmpb",  0x4),
00043   ARITH_BYTE_INST ("movb",  0x5),
00044   ARITH_BYTE_INST ("orb",   0x6),
00045   ARITH_BYTE_INST ("subb",  0x7),
00046   ARITH_BYTE_INST ("subcb", 0x8),
00047   ARITH_BYTE_INST ("xorb",  0x9),
00048   ARITH_BYTE_INST ("mulb",  0xA),
00049 
00050   ARITH_BYTE_INST ("adduw", 0x10),
00051   ARITH_BYTE_INST ("addw",  0x11),
00052   ARITH_BYTE_INST ("addcw", 0x12),
00053   ARITH_BYTE_INST ("andw",  0x13),
00054   ARITH_BYTE_INST ("cmpw",  0x14),
00055   ARITH_BYTE_INST ("movw",  0x15),
00056   ARITH_BYTE_INST ("orw",   0x16),
00057   ARITH_BYTE_INST ("subw",  0x17),
00058   ARITH_BYTE_INST ("subcw", 0x18),
00059   ARITH_BYTE_INST ("xorw",  0x19),
00060   ARITH_BYTE_INST ("mulw",  0x1A),
00061 
00062 /* Create an arithmetic instruction - INST[d].  */
00063 #define  ARITH_INST(NAME, OPC) \
00064   /* opc8 cst4 r */                                                \
00065   {NAME, 1, OPC,  24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}},       \
00066   /* opc8 i16 r */                                                 \
00067   {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0},  {regr,16}}},  \
00068   /* opc8 i32 r */                                                 \
00069   {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0},  {regr,16}}},          \
00070   /* opc8 r r */                                                   \
00071   {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}}
00072 
00073   ARITH_INST ("addud", 0x20),
00074   ARITH_INST ("addd",  0x21),
00075   ARITH_INST ("addcd", 0x22),
00076   ARITH_INST ("andd",  0x23),
00077   ARITH_INST ("cmpd",  0x24),
00078   ARITH_INST ("movd",  0x25),
00079   ARITH_INST ("ord",   0x26),
00080   ARITH_INST ("subd",  0x27),
00081   ARITH_INST ("subcd", 0x28),
00082   ARITH_INST ("xord",  0x29),
00083   ARITH_INST ("muld",  0x2A),
00084 
00085 /* Create a shift instruction.  */
00086 #define  SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2) \
00087   /* OPRD=ui3 -->> opc9 ui3 r */                       \
00088   /* OPRD=ui4 -->> opc8 ui4 r */                       \
00089   /* OPRD=ui5 -->> opc7 ui5 r */                       \
00090   {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
00091   /* opc8 r r */                                       \
00092   {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}}
00093 
00094   SHIFT_INST ("sllb", ui3, 0x1F8, 23, 0x4D),
00095   SHIFT_INST ("srlb", ui3, 0x1F9, 23, 0x4E),
00096   SHIFT_INST ("srab", ui3, 0x1FA, 23, 0x4F),
00097 
00098   SHIFT_INST ("sllw", ui4, 0xB6,  24, 0x5D),
00099   SHIFT_INST ("srlw", ui4, 0xB7,  24, 0x5E),
00100   SHIFT_INST ("sraw", ui4, 0xB8,  24, 0x5F),
00101 
00102   SHIFT_INST ("slld", ui5, 0x78,  25, 0x6D),
00103   SHIFT_INST ("srld", ui5, 0x79,  25, 0x6E),
00104   SHIFT_INST ("srad", ui5, 0x7A,  25, 0x6F),
00105 
00106 /* Create a conditional branch instruction.  */
00107 #define  BRANCH_INST(NAME, OPC) \
00108   /* opc4 c4 dispe9 */                                                \
00109   {NAME,  1, OPC, 24, BRANCH_INS | RELAXABLE, {{dispe9,16}}},         \
00110   /* opc4 c4 disps17 */                                               \
00111   {NAME,  2, (OPC<<8)+0x7E, 16,    BRANCH_INS | RELAXABLE, {{disps17,0}}}, \
00112   /* opc4 c4 disps32 */                                               \
00113   {NAME,  3, (OPC<<8)+0x7F, 16,    BRANCH_INS | RELAXABLE, {{disps32,0}}}
00114 
00115   BRANCH_INST ("beq", 0x70),
00116   BRANCH_INST ("bne", 0x71),
00117   BRANCH_INST ("bcs", 0x72),
00118   BRANCH_INST ("bcc", 0x73),
00119   BRANCH_INST ("bhi", 0x74),
00120   BRANCH_INST ("bls", 0x75),
00121   BRANCH_INST ("bgt", 0x76),
00122   BRANCH_INST ("ble", 0x77),
00123   BRANCH_INST ("bfs", 0x78),
00124   BRANCH_INST ("bfc", 0x79),
00125   BRANCH_INST ("blo", 0x7A),
00126   BRANCH_INST ("bhs", 0x7B),
00127   BRANCH_INST ("blt", 0x7C),
00128   BRANCH_INST ("bge", 0x7D),
00129   BRANCH_INST ("br",  0x7E),
00130 
00131 /* Create a 'Branch if Equal to 0' instruction.  */
00132 #define  BRANCH_NEQ_INST(NAME, OPC) \
00133   /* opc8 dispu5 r */                                          \
00134   {NAME,  1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {dispu5,20}}}
00135 
00136   BRANCH_NEQ_INST ("beq0b",  0xB0),
00137   BRANCH_NEQ_INST ("bne0b",  0xB1),
00138   BRANCH_NEQ_INST ("beq0w",  0xB2),
00139   BRANCH_NEQ_INST ("bne0w",  0xB3),
00140   BRANCH_NEQ_INST ("beq0d",  0xB4),
00141   BRANCH_NEQ_INST ("bne0d",  0xB5),
00142 
00143 /* Create instruction with no operands.  */
00144 #define  NO_OP_INST(NAME, OPC) \
00145   /* opc16 */                   \
00146   {NAME,  1, OPC, 16, 0, {{0, 0}}}
00147 
00148   NO_OP_INST ("nop", 0x3002),
00149   NO_OP_INST ("retx",       0x3003),
00150   NO_OP_INST ("di",  0x3004),
00151   NO_OP_INST ("ei",  0x3005),
00152   NO_OP_INST ("wait",       0x3006),
00153   NO_OP_INST ("eiwait",     0x3007),
00154 
00155 /* Create a 'Compare & Branch' instruction.  */
00156 #define  CMPBR_INST(NAME, OPC1, OPC2, C4) \
00157   /* opc12 r r c4 disps9 */                                   \
00158   {NAME, 2, ((0x300+OPC1)<<12)+C4,  8, CMPBR_INS | FMT_3| RELAXABLE,  \
00159       {{regr,16}, {regr,12}, {disps9,0}}},                           \
00160   /* opc12 r r c4 disps25 */                                         \
00161   {NAME, 3, ((0x310+OPC1)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
00162       {{regr,16}, {regr,12}, {disps25,0}}},                          \
00163   /* opc12 i4cst4 r c4 disps9 */                              \
00164   {NAME, 2, ((0x300+OPC2)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
00165       {{cst4,16}, {regr,12}, {disps9,0}}},                           \
00166   /* opc12 i4cst4 r c4 disps25 */                             \
00167   {NAME, 3, ((0x310+OPC2)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
00168       {{cst4,16}, {regr,12}, {disps25,0}}}
00169 
00170   CMPBR_INST ("cmpbeqb", 0x8, 0xC, 0x0),
00171   CMPBR_INST ("cmpbneb", 0x8, 0xC, 0x1),
00172   CMPBR_INST ("cmpbhib", 0x8, 0xC, 0x4),
00173   CMPBR_INST ("cmpblsb", 0x8, 0xC, 0x5),
00174   CMPBR_INST ("cmpbgtb", 0x8, 0xC, 0x6),
00175   CMPBR_INST ("cmpbleb", 0x8, 0xC, 0x7),
00176   CMPBR_INST ("cmpblob", 0x8, 0xC, 0xA),
00177   CMPBR_INST ("cmpbhsb", 0x8, 0xC, 0xB),
00178   CMPBR_INST ("cmpbltb", 0x8, 0xC, 0xC),
00179   CMPBR_INST ("cmpbgeb", 0x8, 0xC, 0xD),
00180 
00181   CMPBR_INST ("cmpbeqw", 0x9, 0xD, 0x0),
00182   CMPBR_INST ("cmpbnew", 0x9, 0xD, 0x1),
00183   CMPBR_INST ("cmpbhiw", 0x9, 0xD, 0x4),
00184   CMPBR_INST ("cmpblsw", 0x9, 0xD, 0x5),
00185   CMPBR_INST ("cmpbgtw", 0x9, 0xD, 0x6),
00186   CMPBR_INST ("cmpblew", 0x9, 0xD, 0x7),
00187   CMPBR_INST ("cmpblow", 0x9, 0xD, 0xA),
00188   CMPBR_INST ("cmpbhsw", 0x9, 0xD, 0xB),
00189   CMPBR_INST ("cmpbltw", 0x9, 0xD, 0xC),
00190   CMPBR_INST ("cmpbgew", 0x9, 0xD, 0xD),
00191 
00192   CMPBR_INST ("cmpbeqd", 0xA, 0xE, 0x0),
00193   CMPBR_INST ("cmpbned", 0xA, 0xE, 0x1),
00194   CMPBR_INST ("cmpbhid", 0xA, 0xE, 0x4),
00195   CMPBR_INST ("cmpblsd", 0xA, 0xE, 0x5),
00196   CMPBR_INST ("cmpbgtd", 0xA, 0xE, 0x6),
00197   CMPBR_INST ("cmpbled", 0xA, 0xE, 0x7),
00198   CMPBR_INST ("cmpblod", 0xA, 0xE, 0xA),
00199   CMPBR_INST ("cmpbhsd", 0xA, 0xE, 0xB),
00200   CMPBR_INST ("cmpbltd", 0xA, 0xE, 0xC),
00201   CMPBR_INST ("cmpbged", 0xA, 0xE, 0xD),
00202 
00203 /* Create an instruction using a single register operand.  */
00204 #define  REG1_INST(NAME, OPC) \
00205   /* opc8 c4 r */                         \
00206   {NAME,  1, OPC, 20, NO_TYPE_INS, {{regr,16}}}
00207 
00208 /* Same as REG1_INST, with additional FLAGS.  */
00209 #define  REG1_FLAG_INST(NAME, OPC, FLAGS) \
00210   /* opc8 c4 r */                                \
00211   {NAME,  1, OPC, 20, NO_TYPE_INS | FLAGS, {{regr,16}}}
00212 
00213   /* JCond instructions     */
00214   REG1_INST ("jeq",  0xBA0),
00215   REG1_INST ("jne",  0xBA1),
00216   REG1_INST ("jcs",  0xBA2),
00217   REG1_INST ("jcc",  0xBA3),
00218   REG1_INST ("jhi",  0xBA4),
00219   REG1_INST ("jls",  0xBA5),
00220   REG1_INST ("jgt",  0xBA6),
00221   REG1_INST ("jle",  0xBA7),
00222   REG1_INST ("jfs",  0xBA8),
00223   REG1_INST ("jfc",  0xBA9),
00224   REG1_INST ("jlo",  0xBAA),
00225   REG1_INST ("jhs",  0xBAB),
00226   REG1_INST ("jlt",  0xBAC),
00227   REG1_INST ("jge",  0xBAD),
00228   REG1_INST ("jump", 0xBAE),
00229 
00230   /* SCond instructions */
00231   REG1_INST ("seq",  0xBB0),
00232   REG1_INST ("sne",  0xBB1),
00233   REG1_INST ("scs",  0xBB2),
00234   REG1_INST ("scc",  0xBB3),
00235   REG1_INST ("shi",  0xBB4),
00236   REG1_INST ("sls",  0xBB5),
00237   REG1_INST ("sgt",  0xBB6),
00238   REG1_INST ("sle",  0xBB7),
00239   REG1_INST ("sfs",  0xBB8),
00240   REG1_INST ("sfc",  0xBB9),
00241   REG1_INST ("slo",  0xBBA),
00242   REG1_INST ("shs",  0xBBB),
00243   REG1_INST ("slt",  0xBBC),
00244   REG1_INST ("sge",  0xBBD),
00245 
00246 /* Create an instruction using two register operands.  */
00247 #define  REG2_INST(NAME, OPC) \
00248   /* opc24 r r  OR  opc20 c4 r r */                     \
00249   {NAME,  2, 0x300800+OPC,  8, NO_TYPE_INS, {{regr,4}, {regr,0}}}
00250 
00251   /* MULTIPLY INSTRUCTIONS */
00252   REG2_INST ("macsb",  0x40),
00253   REG2_INST ("macub",  0x41),
00254   REG2_INST ("macqb",  0x42),
00255 
00256   REG2_INST ("macsw",  0x50),
00257   REG2_INST ("macuw",  0x51),
00258   REG2_INST ("macqw",  0x52),
00259 
00260   REG2_INST ("macsd",  0x60),
00261   REG2_INST ("macud",  0x61),
00262   REG2_INST ("macqd",  0x62),
00263 
00264   REG2_INST ("mullsd", 0x65),
00265   REG2_INST ("mullud", 0x66),
00266 
00267   REG2_INST ("mulsbw", 0x3B),
00268   REG2_INST ("mulubw", 0x3C),
00269   REG2_INST ("mulswd", 0x3D),
00270   REG2_INST ("muluwd", 0x3E),
00271 
00272   /*  SIGNEXTEND STUFF    */
00273   REG2_INST ("sextbw", 0x30),
00274   REG2_INST ("sextbd", 0x31),
00275   REG2_INST ("sextwd", 0x32),
00276   REG2_INST ("zextbw", 0x34),
00277   REG2_INST ("zextbd", 0x35),
00278   REG2_INST ("zextwd", 0x36),
00279 
00280   REG2_INST ("bswap",  0x3F),
00281 
00282   REG2_INST ("maxsb",  0x80),
00283   REG2_INST ("minsb",  0x81),
00284   REG2_INST ("maxub",  0x82),
00285   REG2_INST ("minub",  0x83),
00286   REG2_INST ("absb",   0x84),
00287   REG2_INST ("negb",   0x85),
00288   REG2_INST ("cntl0b", 0x86),
00289   REG2_INST ("cntl1b", 0x87),
00290   REG2_INST ("popcntb",0x88),
00291   REG2_INST ("rotlb",  0x89),
00292   REG2_INST ("rotrb",  0x8A),
00293   REG2_INST ("mulqb",  0x8B),
00294   REG2_INST ("addqb",  0x8C),
00295   REG2_INST ("subqb",  0x8D),
00296   REG2_INST ("cntlsb", 0x8E),
00297 
00298   REG2_INST ("maxsw",  0x90),
00299   REG2_INST ("minsw",  0x91),
00300   REG2_INST ("maxuw",  0x92),
00301   REG2_INST ("minuw",  0x93),
00302   REG2_INST ("absw",   0x94),
00303   REG2_INST ("negw",   0x95),
00304   REG2_INST ("cntl0w", 0x96),
00305   REG2_INST ("cntl1w", 0x97),
00306   REG2_INST ("popcntw",0x98),
00307   REG2_INST ("rotlw",  0x99),
00308   REG2_INST ("rotrw",  0x9A),
00309   REG2_INST ("mulqw",  0x9B),
00310   REG2_INST ("addqw",  0x9C),
00311   REG2_INST ("subqw",  0x9D),
00312   REG2_INST ("cntlsw", 0x9E),
00313 
00314   REG2_INST ("maxsd",  0xA0),
00315   REG2_INST ("minsd",  0xA1),
00316   REG2_INST ("maxud",  0xA2),
00317   REG2_INST ("minud",  0xA3),
00318   REG2_INST ("absd",   0xA4),
00319   REG2_INST ("negd",   0xA5),
00320   REG2_INST ("cntl0d", 0xA6),
00321   REG2_INST ("cntl1d", 0xA7),
00322   REG2_INST ("popcntd",0xA8),
00323   REG2_INST ("rotld",  0xA9),
00324   REG2_INST ("rotrd",  0xAA),
00325   REG2_INST ("mulqd",  0xAB),
00326   REG2_INST ("addqd",  0xAC),
00327   REG2_INST ("subqd",  0xAD),
00328   REG2_INST ("cntlsd", 0xAE),
00329 
00330 /* Conditional move instructions */
00331   REG2_INST ("cmoveqd", 0x70),
00332   REG2_INST ("cmovned", 0x71),
00333   REG2_INST ("cmovcsd", 0x72),
00334   REG2_INST ("cmovccd", 0x73),
00335   REG2_INST ("cmovhid", 0x74),
00336   REG2_INST ("cmovlsd", 0x75),
00337   REG2_INST ("cmovgtd", 0x76),
00338   REG2_INST ("cmovled", 0x77),
00339   REG2_INST ("cmovfsd", 0x78),
00340   REG2_INST ("cmovfcd", 0x79),
00341   REG2_INST ("cmovlod", 0x7A),
00342   REG2_INST ("cmovhsd", 0x7B),
00343   REG2_INST ("cmovltd", 0x7C),
00344   REG2_INST ("cmovged", 0x7D),
00345 
00346 /* Load instructions (from memory to register).  */
00347 #define  LD_REG_INST(NAME, OPC1, OPC2, DISP) \
00348   /* opc12 r abs16 */                                                     \
00349   {NAME,  2, 0x320+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
00350       {{abs16,0}, {regr,16}}},                                            \
00351   /* opc12 r abs32 */                                                     \
00352   {NAME,  3, 0x330+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
00353       {{abs32,0}, {regr,16}}},                                            \
00354   /* opc4 r rbase dispu[bwd]4 */                                   \
00355   {NAME,  1, 0x8+OPC2,  28, LD_STOR_INS | DISP | REVERSE_MATCH,                  \
00356       {{rbase_dispu4,16}, {regr,24}}},                                    \
00357   /* opc4 r rbase disps16 */                                              \
00358   {NAME,  2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH,  \
00359       {{rbase_disps16,16}, {regr,24}}},                                   \
00360   /* opc4 r rbase disps32 */                                              \
00361   {NAME,  3, ((0x8+OPC2)<<8)+0xF,  20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \
00362       {{rbase_disps32,16}, {regr,24}}},                                   \
00363   /* opc12 r rbase ridx scl2 disps6 */                                    \
00364   {NAME,  2, 0x32C+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
00365       {{rindex_disps6,0}, {regr,16}}},                                    \
00366   /* opc12 r rbase ridx scl2 disps22 */                                   \
00367   {NAME,  3, 0x33C+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
00368       {{rindex_disps22,0}, {regr,16}}},                                   \
00369   /* opc12 r rbase disps12 */                                             \
00370   {NAME,  2, 0x328+OPC1,  20, LD_STOR_INS_INC | REVERSE_MATCH,            \
00371       {{rbase_disps12,12}, {regr,16}}}
00372 
00373   LD_REG_INST ("loadb", 0x0, 0x0, DISPUB4),
00374   LD_REG_INST ("loadw", 0x1, 0x1, DISPUW4),
00375   LD_REG_INST ("loadd", 0x2, 0x2, DISPUD4),
00376 
00377 /* Store instructions (from Register to Memory).  */
00378 #define  ST_REG_INST(NAME, OPC1, OPC2, DISP) \
00379   /* opc12 r abs16 */                                                       \
00380   {NAME,  2, 0x320+OPC1,  20, LD_STOR_INS, {{regr,16}, {abs16,0}}},         \
00381   /* opc12 r abs32 */                                                       \
00382   {NAME,  3, 0x330+OPC1,  20, LD_STOR_INS, {{regr,16}, {abs32,0}}},         \
00383   /* opc4 r rbase dispu[bwd]4 */                                     \
00384   {NAME,  1, 0x8+OPC2,  28, LD_STOR_INS | DISP,                             \
00385       {{regr,24}, {rbase_dispu4,16}}},                                      \
00386   /* opc4 r rbase disps16 */                                                \
00387   {NAME,  2, ((0x8+OPC2)<<8)+0xE,  20, LD_STOR_INS | FMT_1,                 \
00388       {{regr,24}, {rbase_disps16,16}}},                                     \
00389   /* opc4 r rbase disps32 */                                                \
00390   {NAME,  3, ((0x8+OPC2)<<8)+0xF,  20, LD_STOR_INS | FMT_1,                 \
00391       {{regr,24}, {rbase_disps32,16}}},                                     \
00392   /* opc12 r rbase ridx scl2 disps6 */                                      \
00393   {NAME,  2, 0x32C+OPC1,  20, LD_STOR_INS,                                  \
00394       {{regr,16}, {rindex_disps6,0}}},                                      \
00395   /* opc12 r rbase ridx scl2 disps22 */                                     \
00396   {NAME,  3, 0x33C+OPC1,  20, LD_STOR_INS, {{regr,16}, {rindex_disps22,0}}},  \
00397   /* opc12 r rbase disps12 */                                               \
00398   {NAME,  2, 0x328+OPC1,  20, LD_STOR_INS_INC, {{regr,16}, {rbase_disps12,12}}}
00399 
00400 /* Store instructions (Immediate to Memory).  */
00401 #define  ST_I_INST(NAME, OPC) \
00402   /* opc12 ui4 rbase disps12 */                                             \
00403   {NAME,  2, 0x368+OPC,     20, LD_STOR_INS_INC, {{ui4,16}, {rbase_disps12,12}}}, \
00404   /* opc12 ui4 abs16 */                                                     \
00405   {NAME,  2, 0x360+OPC,     20, STOR_IMM_INS, {{ui4,16}, {abs16,0}}},       \
00406   /* opc12 ui4 abs32 */                                                     \
00407   {NAME,  3, 0x370+OPC,     20, STOR_IMM_INS, {{ui4,16}, {abs32,0}}},       \
00408   /* opc12 ui4 rbase disps12 */                                             \
00409   {NAME,  2, 0x364+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rbase_disps12,12}}},    \
00410   /* opc12 ui4 rbase disps28 */                                             \
00411   {NAME,  3, 0x374+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rbase_disps28,12}}},    \
00412   /* opc12 ui4 rbase ridx scl2 disps6 */                             \
00413   {NAME,  2, 0x36C+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rindex_disps6,0}}},     \
00414   /* opc12 ui4 rbase ridx scl2 disps22 */                            \
00415   {NAME,  3, 0x37C+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rindex_disps22,0}}}
00416 
00417   ST_REG_INST ("storb", 0x20, 0x4, DISPUB4),
00418   ST_I_INST ("storb",  0x0),
00419 
00420   ST_REG_INST ("storw", 0x21, 0x5, DISPUW4),
00421   ST_I_INST ("storw",  0x1),
00422 
00423   ST_REG_INST ("stord", 0x22, 0x6, DISPUD4),
00424   ST_I_INST ("stord",  0x2),
00425 
00426 /* Create a bit instruction.  */
00427 #define  CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2) \
00428   /* OP=ui3 -->> opc13 ui3 */                                               \
00429   /* OP=ui4 -->> opc12 ui4 */                                               \
00430   /* OP=ui5 -->> opc11 ui5 */                                               \
00431                                                                      \
00432   /* opcNN iN abs16 */                                                      \
00433   {NAME,  2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}},         \
00434   /* opcNN iN abs32 */                                                      \
00435   {NAME,  3, OPC1+1*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs32,0}}},         \
00436   /* opcNN iN rbase */                                                      \
00437   {NAME,  1, OPC2,  SHIFT+4,  CSTBIT_INS, {{OP,20}, {rbase,16}}},           \
00438   /* opcNN iN rbase disps12 */                                              \
00439   {NAME,  2, OPC1+2*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps12,12}}},  \
00440   /* opcNN iN rbase disps28 */                                              \
00441   {NAME,  3, OPC1+3*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps28,12}}},  \
00442   /* opcNN iN rbase ridx scl2 disps6 */                                     \
00443   {NAME,  2, OPC1+4*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps6,0}}},   \
00444   /* opcNN iN rbase ridx scl2 disps22 */                             \
00445   {NAME,  3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps22,0}}}
00446 
00447   CSTBIT_INST ("cbitb", ui3, 0x700, 0x20, 19, 0x1FC),
00448   CSTBIT_INST ("cbitw", ui4, 0x382, 0x10, 20, 0xBD),
00449   CSTBIT_INST ("cbitd", ui5, 0x1C3, 0x8,  21, 0x7B),
00450   {"cbitd",   2, 0x300838,  8, CSTBIT_INS, {{regr,4}, {regr,0}}},
00451   {"cbitd",   2, 0x18047B,  9, CSTBIT_INS, {{ui5,4}, {regr,0}}},
00452 
00453   CSTBIT_INST ("sbitb", ui3, 0x701, 0x20, 19, 0x1FD),
00454   CSTBIT_INST ("sbitw", ui4, 0x383, 0x10, 20, 0xBE),
00455   CSTBIT_INST ("sbitd", ui5, 0x1C4, 0x8,  21, 0x7C),
00456   {"sbitd",   2, 0x300839,  8, CSTBIT_INS, {{regr,4}, {regr,0}}},
00457   {"sbitd",   2, 0x18047C,  9, CSTBIT_INS, {{ui5,4}, {regr,0}}},
00458 
00459   CSTBIT_INST ("tbitb", ui3, 0x702, 0x20, 19, 0x1FE),
00460   CSTBIT_INST ("tbitw", ui4, 0x384, 0x10, 20, 0xBF),
00461   CSTBIT_INST ("tbitd", ui5, 0x1C5, 0x8,  21, 0x7D),
00462   {"tbitd",   2, 0x30083A,  8, CSTBIT_INS, {{regr,4}, {regr,0}}},
00463   {"tbitd",   2, 0x18047D,  9, CSTBIT_INS, {{ui5,4}, {regr,0}}},
00464 
00465 /* Instructions including a register list (opcode is represented as a mask).  */
00466 #define  REGLIST_INST(NAME, OPC, FLAG) \
00467   /* opc12 r mask16 */                                                    \
00468   {NAME,  2, OPC, 20, NO_TYPE_INS | REG_LIST | FLAG, {{regr,16}, {ui16,0}}}
00469 
00470   REG1_INST ("getrfid",     0xFF9),
00471   REG1_INST ("setrfid",     0xFFA),
00472 
00473   REGLIST_INST ("push",      0x346,        NO_RPTR),
00474   REG1_FLAG_INST ("push", 0xFFB, NO_SP),
00475   REGLIST_INST ("pushx", 0x347,     NO_RPTR),
00476 
00477   REGLIST_INST ("pop",       0x324,        NO_RPTR),
00478   REG1_FLAG_INST ("pop", 0xFFC,     NO_SP),
00479   REGLIST_INST ("popx",      0x327,        NO_RPTR),
00480 
00481   REGLIST_INST ("popret", 0x326, NO_RPTR),
00482   REG1_FLAG_INST ("popret",0xFFD,NO_SP),
00483 
00484   REGLIST_INST ("loadm",  0x324, NO_RPTR),
00485   REGLIST_INST ("loadma", 0x325, USER_REG),
00486 
00487   REGLIST_INST ("storm",  0x344, NO_RPTR),
00488   REGLIST_INST ("storma", 0x345, USER_REG),
00489 
00490 /* Create a branch instruction.  */
00491 #define  BR_INST(NAME, OPC1, OPC2, INS_TYPE) \
00492   /* opc12 r disps17 */                                                 \
00493   {NAME,  2, OPC1,  20, INS_TYPE | RELAXABLE, {{regr,16}, {disps17,0}}},  \
00494   /* opc12 r disps32 */                                                 \
00495   {NAME,  3, OPC2,  20, INS_TYPE | RELAXABLE, {{regr,16}, {disps32,0}}}
00496 
00497   BR_INST ("bal",   0x307, 0x317, NO_TYPE_INS),
00498 
00499   /* Decrement and Branch instructions.  */
00500   BR_INST ("dbnzb", 0x304, 0x314, DCR_BRANCH_INS),
00501   BR_INST ("dbnzw", 0x305, 0x315, DCR_BRANCH_INS),
00502   BR_INST ("dbnzd", 0x306, 0x316, DCR_BRANCH_INS),
00503 
00504   /* Jump and link instructions.  */
00505   REG1_INST ("jal",    0xFF8),
00506   REG2_INST ("jal",    0x37),
00507   REG2_INST ("jalid",  0x33),
00508 
00509 /* Create a CO-processor instruction.  */
00510   /* esc12 c4 ui16 */
00511   {"cpi",  2, 0x301,  20, COP_REG_INS, {{ui4,16}, {ui16,0}}},
00512   /* esc12 c4 ui16 ui16 */
00513   {"cpi",  3, 0x311,  20, COP_REG_INS, {{ui4,16}, {ui16,0}, {ui16,16}}},
00514 
00515 #define  COP_INST(NAME, OPC, TYPE, REG1, REG2) \
00516   /* opc12 c4 opc8 REG1 REG2 */                                             \
00517   {NAME,  2, 0x301030+OPC,  8, TYPE | FMT_2, {{ui4,16}, {REG1,4}, {REG2,0}}}
00518 /* A reverse form of the above macro.  */
00519 #define  REV_COP_INST(NAME, OPC, TYPE, REG1, REG2) \
00520   /* opc12 c4 opc8 REG2 REG1 */                                             \
00521   {NAME,  2, 0x301030+OPC,  8, TYPE | FMT_2, {{ui4,16}, {REG1,0}, {REG2,4}}}
00522 
00523   COP_INST    ("mtcr",   0, COP_REG_INS,  regr,    copregr),
00524   COP_INST    ("mfcr",   1, COP_REG_INS,  copregr,  regr),
00525   COP_INST    ("mtcsr",  2, COPS_REG_INS, regr,    copsregr),
00526   COP_INST    ("mfcsr",  3, COPS_REG_INS, copsregr, regr),
00527   COP_INST    ("ldcr",   4, COP_REG_INS,  regr,    copregr),
00528   REV_COP_INST       ("stcr",   5, COP_REG_INS,  copregr,  regr),
00529   COP_INST    ("ldcsr",  6, COPS_REG_INS, regr,     copsregr),
00530   REV_COP_INST       ("stcsr",  7, COPS_REG_INS, copsregr, regr),
00531 
00532 /* Create a memory-related CO-processor instruction.  */
00533 #define  COPMEM_INST(NAME, OPC, TYPE) \
00534   /* opc12 c4 opc12 r mask16 */                           \
00535   {NAME,  3, 0x3110300+OPC,  4, TYPE | REG_LIST | FMT_5,  \
00536       {{ui4,16}, {regr,0}, {ui16,16}}}
00537 
00538   COPMEM_INST("loadmcr",  0,  COP_REG_INS),
00539   COPMEM_INST("stormcr",  1,  COP_REG_INS),
00540   COPMEM_INST("loadmcsr", 2,  COPS_REG_INS),
00541   COPMEM_INST("stormcsr", 3,  COPS_REG_INS),
00542 
00543   /* CO-processor extensions.  */
00544   /* opc12 c4 opc4 ui4 disps9 */
00545   {"bcop",    2, 0x30107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, 
00546       {{ui4,8}, {ui4,16}, {disps9,0}}},
00547   /* opc12 c4 opc4 ui4 disps25 */
00548   {"bcop",    3, 0x31107, 12, COP_BRANCH_INS | FMT_4 | RELAXABLE, 
00549       {{ui4,8}, {ui4,16}, {disps25,0}}},
00550   /* opc12 c4 opc4 cpdo r r */
00551   {"cpdop",   2, 0x3010B, 12, COP_REG_INS | FMT_4, 
00552       {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}}},
00553   /* opc12 c4 opc4 cpdo r r cpdo16 */
00554   {"cpdop",   3, 0x3110B, 12, COP_REG_INS | FMT_4, 
00555       {{ui4,16}, {ui4,8}, {regr,4}, {regr,0}, {ui16,16}}},
00556   /* esc16 r procreg */
00557   {"mtpr",    2, 0x3009,  16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}},
00558   /* esc16 procreg r */
00559   {"mfpr",    2, 0x300A,  16, NO_TYPE_INS, {{regr8,8}, {regr8,0}}},
00560 
00561   /* Miscellaneous.  */
00562   /* opc12 ui4 */
00563   {"excp",    1, 0xFFF,     20, NO_TYPE_INS, {{ui4,16}}},
00564   /* opc28 ui4 */
00565   {"cinv",    2, 0x3010000, 4,     NO_TYPE_INS, {{ui4,0}}},
00566 
00567   /* opc9 ui5 ui5 ui5 r r */
00568   {"ram", 2, 0x7C,  23, NO_TYPE_INS, 
00569       {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}},
00570   {"rim", 2, 0x7D,  23, NO_TYPE_INS, 
00571       {{ui5,18}, {ui5,13}, {ui5,8}, {regr,4}, {regr,0}}},
00572 
00573   /* opc9 ui3 r */
00574   {"rotb",    1, 0x1FB,     23, NO_TYPE_INS, {{ui3,20}, {regr,16}}},
00575   /* opc8 ui4 r */
00576   {"rotw",    1, 0xB9,      24, NO_TYPE_INS, {{ui4,20}, {regr,16}}},
00577   /* opc23 ui5 r */
00578   {"rotd",    2, 0x180478,  9, NO_TYPE_INS, {{ui5,4}, {regr,0}}},
00579 
00580   {NULL,      0, 0, 0,      0, {{0, 0}}}
00581 };
00582 
00583 const int crx_num_opcodes = ARRAY_SIZE (crx_instruction);
00584 
00585 /* Macro to build a reg_entry, which have an opcode image :
00586    For example :
00587       REG(u4, 0x84, CRX_U_REGTYPE)
00588    is interpreted as :
00589       {"u4",  u4, 0x84, CRX_U_REGTYPE}  */
00590 #define REG(NAME, N, TYPE)    {STRINGX(NAME), {NAME}, N, TYPE}
00591 
00592 const reg_entry crx_regtab[] =
00593 {
00594 /* Build a general purpose register r<N>.  */
00595 #define REG_R(N)    REG(CONCAT2(r,N), N, CRX_R_REGTYPE)
00596 
00597   REG_R(0),  REG_R(1),      REG_R(2),  REG_R(3),
00598   REG_R(4),  REG_R(5),      REG_R(6),  REG_R(7),
00599   REG_R(8),  REG_R(9),      REG_R(10), REG_R(11),
00600   REG_R(12), REG_R(13), REG_R(14), REG_R(15),
00601   REG(ra, 0xe, CRX_R_REGTYPE),
00602   REG(sp, 0xf, CRX_R_REGTYPE),
00603 
00604 /* Build a user register u<N>.  */
00605 #define REG_U(N)    REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE)
00606 
00607   REG_U(0),  REG_U(1),  REG_U(2),  REG_U(3),
00608   REG_U(4),  REG_U(5),  REG_U(6),  REG_U(7),
00609   REG_U(8),  REG_U(9),  REG_U(10), REG_U(11),
00610   REG_U(12), REG_U(13), REG_U(14), REG_U(15),
00611   REG(ura, 0x8e, CRX_U_REGTYPE),
00612   REG(usp, 0x8f, CRX_U_REGTYPE),
00613 
00614 /* Build a configuration register.  */
00615 #define REG_CFG(NAME, N)    REG(NAME, N, CRX_CFG_REGTYPE)
00616 
00617   REG_CFG(hi,     0x10),
00618   REG_CFG(lo,     0x11),
00619   REG_CFG(uhi,           0x90),
00620   REG_CFG(ulo,           0x91),
00621   REG_CFG(psr,           0x12),
00622   REG_CFG(intbase,  0x13),
00623   REG_CFG(isp,           0x14),
00624   REG_CFG(cfg,           0x15),
00625   REG_CFG(cpcfg,    0x16),
00626   REG_CFG(cen,           0x17)
00627 };
00628 
00629 const int crx_num_regs = ARRAY_SIZE (crx_regtab);
00630 
00631 const reg_entry crx_copregtab[] =
00632 {
00633 /* Build a Coprocessor register c<N>.  */
00634 #define REG_C(N)    REG(CONCAT2(c,N), N, CRX_C_REGTYPE)
00635 
00636   REG_C(0),  REG_C(1),      REG_C(2),  REG_C(3),
00637   REG_C(4),  REG_C(5),      REG_C(6),  REG_C(7),
00638   REG_C(8),  REG_C(9),      REG_C(10), REG_C(11),
00639   REG_C(12), REG_C(13), REG_C(14), REG_C(15),
00640 
00641 /* Build a Coprocessor Special register cs<N>.  */
00642 #define REG_CS(N)    REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE)
00643 
00644   REG_CS(0),  REG_CS(1),  REG_CS(2),  REG_CS(3),
00645   REG_CS(4),  REG_CS(5),  REG_CS(6),  REG_CS(7),
00646   REG_CS(8),  REG_CS(9),  REG_CS(10), REG_CS(11),
00647   REG_CS(12), REG_CS(13), REG_CS(14), REG_CS(15)
00648 };
00649 
00650 const int crx_num_copregs = ARRAY_SIZE (crx_copregtab);
00651 
00652 /* CRX operands table.  */
00653 const operand_entry crx_optab[] =
00654 {
00655   /* Index 0 is dummy, so we can count the instruction's operands.  */
00656   {0,  nullargs,   0},                                  /* dummy */
00657   {4,  arg_ic,           OP_CST4},                      /* cst4 */
00658   {16, arg_ic,           OP_SIGNED},                           /* i16 */
00659   {32, arg_ic,           OP_SIGNED},                           /* i32 */
00660   {3,  arg_ic,           OP_UNSIGNED},                  /* ui3 */
00661   {4,  arg_ic,           OP_UNSIGNED},                   /* ui4 */
00662   {5,  arg_ic,           OP_UNSIGNED},                   /* ui5 */
00663   {16, arg_ic,           OP_UNSIGNED},                   /* ui16 */
00664   {8,  arg_c,     OP_EVEN|OP_SHIFT|OP_SIGNED},   /* disps9 */
00665   {16, arg_c,     OP_EVEN|OP_SHIFT|OP_SIGNED},   /* disps17 */
00666   {24, arg_c,     OP_EVEN|OP_SHIFT|OP_SIGNED},   /* disps25 */
00667   {32, arg_c,     OP_EVEN|OP_SHIFT|OP_SIGNED},   /* disps32 */
00668   {4,  arg_c,     OP_EVEN|OP_SHIFT_DEC|OP_UNSIGNED},  /* dispu5 */
00669   {8,  arg_c,     OP_EVEN|OP_SHIFT|OP_SIGNED|OP_ESC}, /* dispe9 */
00670   {16, arg_c,     OP_UNSIGNED|OP_UPPER_64KB},           /* abs16 */
00671   {32, arg_c,     OP_UNSIGNED},                  /* abs32 */
00672   {4,  arg_rbase,  0},                                  /* rbase */
00673   {4,  arg_cr,           OP_DISPU4},                           /* rbase_dispu4 */
00674   {12, arg_cr,           OP_SIGNED},                           /* rbase_disps12 */
00675   {16, arg_cr,           OP_SIGNED},                           /* rbase_disps16 */
00676   {28, arg_cr,           OP_SIGNED},                           /* rbase_disps28 */
00677   {32, arg_cr,           OP_SIGNED},                           /* rbase_disps32 */
00678   {6,  arg_idxr,   OP_SIGNED},                          /* rindex_disps6 */
00679   {22,  arg_idxr,   OP_SIGNED},                         /* rindex_disps22 */
00680   {4,  arg_r,     0},                                   /* regr */
00681   {8,  arg_r,     0},                                   /* regr8 */
00682   {4,  arg_copr,   0},                                  /* copregr */
00683   {4,  arg_copsr,  0}                                   /* copsregr */
00684 };
00685 
00686 /* CRX traps/interrupts.  */
00687 const trap_entry crx_traps[] =
00688 {
00689   {"nmi", 1}, {"svc", 5}, {"dvz", 6}, {"flg", 7},
00690   {"bpt", 8}, {"und", 10}, {"prv", 11}, {"iberr", 12}
00691 };
00692 
00693 const int crx_num_traps = ARRAY_SIZE (crx_traps);
00694 
00695 /* cst4 operand mapping:
00696 The value in entry <N> is mapped to the value <N>
00697       Value            Binary mapping
00698     cst4_map[N]        -->>        N
00699 
00700 Example (for N=5):
00701 
00702     cst4_map[5]=-4  -->>    5             */
00703 const long cst4_map[] =
00704 {
00705   0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48
00706 };
00707 
00708 const int cst4_maps = ARRAY_SIZE (cst4_map);
00709 
00710 /* CRX instructions that don't have arguments.  */
00711 const char* no_op_insn[] = 
00712 {
00713   "di", "ei", "eiwait", "nop", "retx", "wait", NULL
00714 };