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cell-binutils  2.17cvs20070401
Defines | Variables
crx-opc.c File Reference
#include <stdio.h>
#include "libiberty.h"
#include "symcat.h"
#include "opcode/crx.h"

Go to the source code of this file.

Defines

#define ARITH_BYTE_INST(NAME, OPC)
#define ARITH_INST(NAME, OPC)
#define SHIFT_INST(NAME, OPRD, OPC1, SHIFT1, OPC2)
#define BRANCH_INST(NAME, OPC)
#define BRANCH_NEQ_INST(NAME, OPC)
#define NO_OP_INST(NAME, OPC)
#define CMPBR_INST(NAME, OPC1, OPC2, C4)
#define REG1_INST(NAME, OPC)
#define REG1_FLAG_INST(NAME, OPC, FLAGS)
#define REG2_INST(NAME, OPC)
#define LD_REG_INST(NAME, OPC1, OPC2, DISP)
#define ST_REG_INST(NAME, OPC1, OPC2, DISP)
#define ST_I_INST(NAME, OPC)
#define CSTBIT_INST(NAME, OP, OPC1, DIFF, SHIFT, OPC2)
#define REGLIST_INST(NAME, OPC, FLAG)
#define BR_INST(NAME, OPC1, OPC2, INS_TYPE)
#define COP_INST(NAME, OPC, TYPE, REG1, REG2)
#define REV_COP_INST(NAME, OPC, TYPE, REG1, REG2)
#define COPMEM_INST(NAME, OPC, TYPE)
#define REG(NAME, N, TYPE)   {STRINGX(NAME), {NAME}, N, TYPE}
#define REG_R(N)   REG(CONCAT2(r,N), N, CRX_R_REGTYPE)
#define REG_U(N)   REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE)
#define REG_CFG(NAME, N)   REG(NAME, N, CRX_CFG_REGTYPE)
#define REG_C(N)   REG(CONCAT2(c,N), N, CRX_C_REGTYPE)
#define REG_CS(N)   REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE)

Variables

const inst crx_instruction []
const int crx_num_opcodes = ARRAY_SIZE (crx_instruction)
const reg_entry crx_regtab []
const int crx_num_regs = ARRAY_SIZE (crx_regtab)
const reg_entry crx_copregtab []
const int crx_num_copregs = ARRAY_SIZE (crx_copregtab)
const operand_entry crx_optab []
const trap_entry crx_traps []
const int crx_num_traps = ARRAY_SIZE (crx_traps)
const long cst4_map []
const int cst4_maps = ARRAY_SIZE (cst4_map)
const char * no_op_insn []

Define Documentation

#define ARITH_BYTE_INST (   NAME,
  OPC 
)
Value:
/* opc8 cst4 r */                                                     \
  {NAME, 1, OPC,  24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}},     \
  /* opc8 i16 r */                                                    \
  {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}},  \
  /* opc8 r r */                                                      \
  {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
#define ARITH_INST (   NAME,
  OPC 
)
Value:
/* opc8 cst4 r */                                                  \
  {NAME, 1, OPC,  24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}},       \
  /* opc8 i16 r */                                                 \
  {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0},  {regr,16}}},  \
  /* opc8 i32 r */                                                 \
  {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0},  {regr,16}}},          \
  /* opc8 r r */                                                   \
  {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}}
#define BR_INST (   NAME,
  OPC1,
  OPC2,
  INS_TYPE 
)
Value:
/* opc12 r disps17 */                                                   \
  {NAME,  2, OPC1,  20, INS_TYPE | RELAXABLE, {{regr,16}, {disps17,0}}},  \
  /* opc12 r disps32 */                                                 \
  {NAME,  3, OPC2,  20, INS_TYPE | RELAXABLE, {{regr,16}, {disps32,0}}}
#define BRANCH_INST (   NAME,
  OPC 
)
Value:
/* opc4 c4 dispe9 */                                           \
  {NAME,  1, OPC, 24, BRANCH_INS | RELAXABLE, {{dispe9,16}}},         \
  /* opc4 c4 disps17 */                                               \
  {NAME,  2, (OPC<<8)+0x7E, 16,    BRANCH_INS | RELAXABLE, {{disps17,0}}}, \
  /* opc4 c4 disps32 */                                               \
  {NAME,  3, (OPC<<8)+0x7F, 16,    BRANCH_INS | RELAXABLE, {{disps32,0}}}
#define BRANCH_NEQ_INST (   NAME,
  OPC 
)
Value:
/* opc8 dispu5 r */                                     \
  {NAME,  1, OPC, 24, BRANCH_NEQ_INS, {{regr,16}, {dispu5,20}}}
#define CMPBR_INST (   NAME,
  OPC1,
  OPC2,
  C4 
)
Value:
/* opc12 r r c4 disps9 */                                     \
  {NAME, 2, ((0x300+OPC1)<<12)+C4,  8, CMPBR_INS | FMT_3| RELAXABLE,  \
      {{regr,16}, {regr,12}, {disps9,0}}},                           \
  /* opc12 r r c4 disps25 */                                         \
  {NAME, 3, ((0x310+OPC1)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
      {{regr,16}, {regr,12}, {disps25,0}}},                          \
  /* opc12 i4cst4 r c4 disps9 */                              \
  {NAME, 2, ((0x300+OPC2)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
      {{cst4,16}, {regr,12}, {disps9,0}}},                           \
  /* opc12 i4cst4 r c4 disps25 */                             \
  {NAME, 3, ((0x310+OPC2)<<12)+C4,  8, CMPBR_INS | FMT_3 | RELAXABLE, \
      {{cst4,16}, {regr,12}, {disps25,0}}}
#define COP_INST (   NAME,
  OPC,
  TYPE,
  REG1,
  REG2 
)
Value:
/* opc12 c4 opc8 REG1 REG2 */                                               \
  {NAME,  2, 0x301030+OPC,  8, TYPE | FMT_2, {{ui4,16}, {REG1,4}, {REG2,0}}}
#define COPMEM_INST (   NAME,
  OPC,
  TYPE 
)
Value:
/* opc12 c4 opc12 r mask16 */                             \
  {NAME,  3, 0x3110300+OPC,  4, TYPE | REG_LIST | FMT_5,  \
      {{ui4,16}, {regr,0}, {ui16,16}}}
#define CSTBIT_INST (   NAME,
  OP,
  OPC1,
  DIFF,
  SHIFT,
  OPC2 
)
Value:
/* OP=ui3 -->> opc13 ui3 */                                          \
  /* OP=ui4 -->> opc12 ui4 */                                               \
  /* OP=ui5 -->> opc11 ui5 */                                               \
                                                                     \
  /* opcNN iN abs16 */                                                      \
  {NAME,  2, OPC1+0*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs16,0}}},         \
  /* opcNN iN abs32 */                                                      \
  {NAME,  3, OPC1+1*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {abs32,0}}},         \
  /* opcNN iN rbase */                                                      \
  {NAME,  1, OPC2,  SHIFT+4,  CSTBIT_INS, {{OP,20}, {rbase,16}}},           \
  /* opcNN iN rbase disps12 */                                              \
  {NAME,  2, OPC1+2*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps12,12}}},  \
  /* opcNN iN rbase disps28 */                                              \
  {NAME,  3, OPC1+3*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rbase_disps28,12}}},  \
  /* opcNN iN rbase ridx scl2 disps6 */                                     \
  {NAME,  2, OPC1+4*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps6,0}}},   \
  /* opcNN iN rbase ridx scl2 disps22 */                             \
  {NAME,  3, OPC1+5*DIFF, SHIFT, CSTBIT_INS, {{OP,16}, {rindex_disps22,0}}}
#define LD_REG_INST (   NAME,
  OPC1,
  OPC2,
  DISP 
)
Value:
/* opc12 r abs16 */                                                \
  {NAME,  2, 0x320+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
      {{abs16,0}, {regr,16}}},                                            \
  /* opc12 r abs32 */                                                     \
  {NAME,  3, 0x330+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
      {{abs32,0}, {regr,16}}},                                            \
  /* opc4 r rbase dispu[bwd]4 */                                   \
  {NAME,  1, 0x8+OPC2,  28, LD_STOR_INS | DISP | REVERSE_MATCH,                  \
      {{rbase_dispu4,16}, {regr,24}}},                                    \
  /* opc4 r rbase disps16 */                                              \
  {NAME,  2, ((0x8+OPC2)<<8)+0xE, 20, LD_STOR_INS | FMT_1 | REVERSE_MATCH,  \
      {{rbase_disps16,16}, {regr,24}}},                                   \
  /* opc4 r rbase disps32 */                                              \
  {NAME,  3, ((0x8+OPC2)<<8)+0xF,  20, LD_STOR_INS | FMT_1 | REVERSE_MATCH, \
      {{rbase_disps32,16}, {regr,24}}},                                   \
  /* opc12 r rbase ridx scl2 disps6 */                                    \
  {NAME,  2, 0x32C+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
      {{rindex_disps6,0}, {regr,16}}},                                    \
  /* opc12 r rbase ridx scl2 disps22 */                                   \
  {NAME,  3, 0x33C+OPC1,  20, LD_STOR_INS | REVERSE_MATCH,                \
      {{rindex_disps22,0}, {regr,16}}},                                   \
  /* opc12 r rbase disps12 */                                             \
  {NAME,  2, 0x328+OPC1,  20, LD_STOR_INS_INC | REVERSE_MATCH,            \
      {{rbase_disps12,12}, {regr,16}}}
#define NO_OP_INST (   NAME,
  OPC 
)
Value:
/* opc16 */                     \
  {NAME,  1, OPC, 16, 0, {{0, 0}}}
#define REG (   NAME,
  N,
  TYPE 
)    {STRINGX(NAME), {NAME}, N, TYPE}

Definition at line 590 of file crx-opc.c.

#define REG1_FLAG_INST (   NAME,
  OPC,
  FLAGS 
)
Value:
/* opc8 c4 r */                                  \
  {NAME,  1, OPC, 20, NO_TYPE_INS | FLAGS, {{regr,16}}}
#define REG1_INST (   NAME,
  OPC 
)
Value:
/* opc8 c4 r */                           \
  {NAME,  1, OPC, 20, NO_TYPE_INS, {{regr,16}}}
#define REG2_INST (   NAME,
  OPC 
)
Value:
/* opc24 r r  OR  opc20 c4 r r */                \
  {NAME,  2, 0x300800+OPC,  8, NO_TYPE_INS, {{regr,4}, {regr,0}}}
#define REG_C (   N)    REG(CONCAT2(c,N), N, CRX_C_REGTYPE)
#define REG_CFG (   NAME,
  N 
)    REG(NAME, N, CRX_CFG_REGTYPE)
#define REG_CS (   N)    REG(CONCAT2(cs,N), N, CRX_CS_REGTYPE)
#define REG_R (   N)    REG(CONCAT2(r,N), N, CRX_R_REGTYPE)
#define REG_U (   N)    REG(CONCAT2(u,N), 0x80 + N, CRX_U_REGTYPE)
#define REGLIST_INST (   NAME,
  OPC,
  FLAG 
)
Value:
/* opc12 r mask16 */                                               \
  {NAME,  2, OPC, 20, NO_TYPE_INS | REG_LIST | FLAG, {{regr,16}, {ui16,0}}}
#define REV_COP_INST (   NAME,
  OPC,
  TYPE,
  REG1,
  REG2 
)
Value:
/* opc12 c4 opc8 REG2 REG1 */                                               \
  {NAME,  2, 0x301030+OPC,  8, TYPE | FMT_2, {{ui4,16}, {REG1,0}, {REG2,4}}}
#define SHIFT_INST (   NAME,
  OPRD,
  OPC1,
  SHIFT1,
  OPC2 
)
Value:
/* OPRD=ui3 -->> opc9 ui3 r */                         \
  /* OPRD=ui4 -->> opc8 ui4 r */                       \
  /* OPRD=ui5 -->> opc7 ui5 r */                       \
  {NAME, 1, OPC1, SHIFT1, SHIFT_INS, {{OPRD,20}, {regr,16}}}, \
  /* opc8 r r */                                       \
  {NAME, 1, OPC2, 24, SHIFT_INS, {{regr,20}, {regr,16}}}
#define ST_I_INST (   NAME,
  OPC 
)
Value:
/* opc12 ui4 rbase disps12 */                                               \
  {NAME,  2, 0x368+OPC,     20, LD_STOR_INS_INC, {{ui4,16}, {rbase_disps12,12}}}, \
  /* opc12 ui4 abs16 */                                                     \
  {NAME,  2, 0x360+OPC,     20, STOR_IMM_INS, {{ui4,16}, {abs16,0}}},       \
  /* opc12 ui4 abs32 */                                                     \
  {NAME,  3, 0x370+OPC,     20, STOR_IMM_INS, {{ui4,16}, {abs32,0}}},       \
  /* opc12 ui4 rbase disps12 */                                             \
  {NAME,  2, 0x364+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rbase_disps12,12}}},    \
  /* opc12 ui4 rbase disps28 */                                             \
  {NAME,  3, 0x374+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rbase_disps28,12}}},    \
  /* opc12 ui4 rbase ridx scl2 disps6 */                             \
  {NAME,  2, 0x36C+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rindex_disps6,0}}},     \
  /* opc12 ui4 rbase ridx scl2 disps22 */                            \
  {NAME,  3, 0x37C+OPC,     20, STOR_IMM_INS, {{ui4,16}, {rindex_disps22,0}}}
#define ST_REG_INST (   NAME,
  OPC1,
  OPC2,
  DISP 
)
Value:
/* opc12 r abs16 */                                                  \
  {NAME,  2, 0x320+OPC1,  20, LD_STOR_INS, {{regr,16}, {abs16,0}}},         \
  /* opc12 r abs32 */                                                       \
  {NAME,  3, 0x330+OPC1,  20, LD_STOR_INS, {{regr,16}, {abs32,0}}},         \
  /* opc4 r rbase dispu[bwd]4 */                                     \
  {NAME,  1, 0x8+OPC2,  28, LD_STOR_INS | DISP,                             \
      {{regr,24}, {rbase_dispu4,16}}},                                      \
  /* opc4 r rbase disps16 */                                                \
  {NAME,  2, ((0x8+OPC2)<<8)+0xE,  20, LD_STOR_INS | FMT_1,                 \
      {{regr,24}, {rbase_disps16,16}}},                                     \
  /* opc4 r rbase disps32 */                                                \
  {NAME,  3, ((0x8+OPC2)<<8)+0xF,  20, LD_STOR_INS | FMT_1,                 \
      {{regr,24}, {rbase_disps32,16}}},                                     \
  /* opc12 r rbase ridx scl2 disps6 */                                      \
  {NAME,  2, 0x32C+OPC1,  20, LD_STOR_INS,                                  \
      {{regr,16}, {rindex_disps6,0}}},                                      \
  /* opc12 r rbase ridx scl2 disps22 */                                     \
  {NAME,  3, 0x33C+OPC1,  20, LD_STOR_INS, {{regr,16}, {rindex_disps22,0}}},  \
  /* opc12 r rbase disps12 */                                               \
  {NAME,  2, 0x328+OPC1,  20, LD_STOR_INS_INC, {{regr,16}, {rbase_disps12,12}}}

Variable Documentation

Initial value:
{

#define REG_C(N)    

  REG_C(0),  REG_C(1),      REG_C(2),  REG_C(3),
  REG_C(4),  REG_C(5),      REG_C(6),  REG_C(7),
  REG_C(8),  REG_C(9),      REG_C(10), REG_C(11),
  REG_C(12), REG_C(13), REG_C(14), REG_C(15),


#define REG_CS(N)    

  REG_CS(0),  REG_CS(1),  REG_CS(2),  REG_CS(3),
  REG_CS(4),  REG_CS(5),  REG_CS(6),  REG_CS(7),
  REG_CS(8),  REG_CS(9),  REG_CS(10), REG_CS(11),
  REG_CS(12), REG_CS(13), REG_CS(14), REG_CS(15)
}

Definition at line 631 of file crx-opc.c.

Definition at line 27 of file crx-opc.c.

Definition at line 650 of file crx-opc.c.

Definition at line 583 of file crx-opc.c.

Definition at line 629 of file crx-opc.c.

Definition at line 693 of file crx-opc.c.

Definition at line 653 of file crx-opc.c.

Definition at line 592 of file crx-opc.c.

Initial value:
{
  {"nmi", 1}, {"svc", 5}, {"dvz", 6}, {"flg", 7},
  {"bpt", 8}, {"und", 10}, {"prv", 11}, {"iberr", 12}
}

Definition at line 687 of file crx-opc.c.

Initial value:
{
  0, 1, 2, 3, 4, -4, -1, 7, 8, 16, 32, 20, 12, 48
}

Definition at line 703 of file crx-opc.c.

Definition at line 708 of file crx-opc.c.

const char* no_op_insn[]
Initial value:
 
{
  "di", "ei", "eiwait", "nop", "retx", "wait", NULL
}

Definition at line 711 of file crx-opc.c.