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cell-binutils  2.17cvs20070401
cris-opc.c
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00001 /* cris-opc.c -- Table of opcodes for the CRIS processor.
00002    Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
00003    Contributed by Axis Communications AB, Lund, Sweden.
00004    Originally written for GAS 1.38.1 by Mikael Asker.
00005    Reorganized by Hans-Peter Nilsson.
00006 
00007 This file is part of GAS, GDB and the GNU binutils.
00008 
00009 GAS, GDB, and GNU binutils is free software; you can redistribute it
00010 and/or modify it under the terms of the GNU General Public License as
00011 published by the Free Software Foundation; either version 2, or (at your
00012 option) any later version.
00013 
00014 GAS, GDB, and GNU binutils are distributed in the hope that they will be
00015 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
00016 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00017 GNU General Public License for more details.
00018 
00019 You should have received a copy of the GNU General Public License
00020 along with this program; if not, write to the Free Software
00021 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00022 
00023 #include "opcode/cris.h"
00024 
00025 #ifndef NULL
00026 #define NULL (0)
00027 #endif
00028 
00029 /* This table isn't used for CRISv32 and the size of immediate operands.  */
00030 const struct cris_spec_reg
00031 cris_spec_regs[] =
00032 {
00033   {"bz",  0,  1, cris_ver_v32p,       NULL},
00034   {"p0",  0,  1, 0,            NULL},
00035   {"vr",  1,  1, 0,            NULL},
00036   {"p1",  1,  1, 0,            NULL},
00037   {"pid", 2,  1, cris_ver_v32p,    NULL},
00038   {"p2",  2,  1, cris_ver_v32p,       NULL},
00039   {"p2",  2,  1, cris_ver_warning, NULL},
00040   {"srs", 3,  1, cris_ver_v32p,    NULL},
00041   {"p3",  3,  1, cris_ver_v32p,       NULL},
00042   {"p3",  3,  1, cris_ver_warning, NULL},
00043   {"wz",  4,  2, cris_ver_v32p,       NULL},
00044   {"p4",  4,  2, 0,            NULL},
00045   {"ccr", 5,  2, cris_ver_v0_10,   NULL},
00046   {"exs", 5,  4, cris_ver_v32p,       NULL},
00047   {"p5",  5,  2, cris_ver_v0_10,   NULL},
00048   {"p5",  5,  4, cris_ver_v32p,       NULL},
00049   {"dcr0",6,  2, cris_ver_v0_3,       NULL},
00050   {"eda", 6,  4, cris_ver_v32p,       NULL},
00051   {"p6",  6,  2, cris_ver_v0_3,       NULL},
00052   {"p6",  6,  4, cris_ver_v32p,       NULL},
00053   {"dcr1/mof", 7, 4, cris_ver_v10p,
00054    "Register `dcr1/mof' with ambiguous size specified.  Guessing 4 bytes"},
00055   {"dcr1/mof", 7, 2, cris_ver_v0_3,
00056    "Register `dcr1/mof' with ambiguous size specified.  Guessing 2 bytes"},
00057   {"mof", 7,  4, cris_ver_v10p,       NULL},
00058   {"dcr1",7,  2, cris_ver_v0_3,       NULL},
00059   {"p7",  7,  4, cris_ver_v10p,       NULL},
00060   {"p7",  7,  2, cris_ver_v0_3,       NULL},
00061   {"dz",  8,  4, cris_ver_v32p,       NULL},
00062   {"p8",  8,  4, 0,            NULL},
00063   {"ibr", 9,  4, cris_ver_v0_10,   NULL},
00064   {"ebp", 9,  4, cris_ver_v32p,       NULL},
00065   {"p9",  9,  4, 0,            NULL},
00066   {"irp", 10, 4, cris_ver_v0_10,   NULL},
00067   {"erp", 10, 4, cris_ver_v32p,       NULL},
00068   {"p10", 10, 4, 0,            NULL},
00069   {"srp", 11, 4, 0,            NULL},
00070   {"p11", 11, 4, 0,            NULL},
00071   /* For disassembly use only.  Accept at assembly with a warning.  */
00072   {"bar/dtp0", 12, 4, cris_ver_warning,
00073    "Ambiguous register `bar/dtp0' specified"},
00074   {"nrp", 12, 4, cris_ver_v32p,       NULL},
00075   {"bar", 12, 4, cris_ver_v8_10,   NULL},
00076   {"dtp0",12, 4, cris_ver_v0_3,       NULL},
00077   {"p12", 12, 4, 0,            NULL},
00078   /* For disassembly use only.  Accept at assembly with a warning.  */
00079   {"dccr/dtp1",13, 4, cris_ver_warning,
00080    "Ambiguous register `dccr/dtp1' specified"},
00081   {"ccs", 13, 4, cris_ver_v32p,       NULL},
00082   {"dccr",13, 4, cris_ver_v8_10,   NULL},
00083   {"dtp1",13, 4, cris_ver_v0_3,       NULL},
00084   {"p13", 13, 4, 0,            NULL},
00085   {"brp", 14, 4, cris_ver_v3_10,   NULL},
00086   {"usp", 14, 4, cris_ver_v32p,       NULL},
00087   {"p14", 14, 4, cris_ver_v3p,        NULL},
00088   {"usp", 15, 4, cris_ver_v10,        NULL},
00089   {"spc", 15, 4, cris_ver_v32p,       NULL},
00090   {"p15", 15, 4, cris_ver_v10p,       NULL},
00091   {NULL, 0, 0, cris_ver_version_all, NULL}
00092 };
00093 
00094 /* Add version specifiers to this table when necessary.
00095    The (now) regular coding of register names suggests a simpler
00096    implementation.  */
00097 const struct cris_support_reg cris_support_regs[] =
00098 {
00099   {"s0", 0},
00100   {"s1", 1},
00101   {"s2", 2},
00102   {"s3", 3},
00103   {"s4", 4},
00104   {"s5", 5},
00105   {"s6", 6},
00106   {"s7", 7},
00107   {"s8", 8},
00108   {"s9", 9},
00109   {"s10", 10},
00110   {"s11", 11},
00111   {"s12", 12},
00112   {"s13", 13},
00113   {"s14", 14},
00114   {"s15", 15},
00115   {NULL, 0}
00116 };
00117 
00118 /* All CRIS opcodes are 16 bits.
00119 
00120    - The match component is a mask saying which bits must match a
00121      particular opcode in order for an instruction to be an instance
00122      of that opcode.
00123 
00124    - The args component is a string containing characters symbolically
00125      matching the operands of an instruction.  Used for both assembly
00126      and disassembly.
00127 
00128      Operand-matching characters:
00129      [ ] , space
00130         Verbatim.
00131      A The string "ACR" (case-insensitive).
00132      B Not really an operand.  It causes a "BDAP -size,SP" prefix to be
00133        output for the PUSH alias-instructions and recognizes a push-
00134        prefix at disassembly.  This letter isn't recognized for v32.
00135        Must be followed by a R or P letter.
00136      ! Non-match pattern, will not match if there's a prefix insn.
00137      b Non-matching operand, used for branches with 16-bit
00138        displacement. Only recognized by the disassembler.
00139      c 5-bit unsigned immediate in bits <4:0>.
00140      C 4-bit unsigned immediate in bits <3:0>.
00141      d  At assembly, optionally (as in put other cases before this one)
00142        ".d" or ".D" at the start of the operands, followed by one space
00143        character.  At disassembly, nothing.
00144      D General register in bits <15:12> and <3:0>.
00145      f List of flags in bits <15:12> and <3:0>.
00146      i 6-bit signed immediate in bits <5:0>.
00147      I 6-bit unsigned immediate in bits <5:0>.
00148      M Size modifier (B, W or D) for CLEAR instructions.
00149      m Size modifier (B, W or D) in bits <5:4>
00150      N  A 32-bit dword, like in the difference between s and y.
00151         This has no effect on bits in the opcode.  Can also be expressed
00152        as "[pc+]" in input.
00153      n  As N, but PC-relative (to the start of the instruction).
00154      o [-128..127] word offset in bits <7:1> and <0>.  Used by 8-bit
00155        branch instructions.
00156      O [-128..127] offset in bits <7:0>.  Also matches a comma and a
00157        general register after the expression, in bits <15:12>.  Used
00158        only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
00159      P Special register in bits <15:12>.
00160      p Indicates that the insn is a prefix insn.  Must be first
00161        character.
00162      Q  As O, but don't relax; force an 8-bit offset.
00163      R General register in bits <15:12>.
00164      r General register in bits <3:0>.
00165      S Source operand in bit <10> and a prefix; a 3-operand prefix
00166        without side-effect.
00167      s Source operand in bits <10> and <3:0>, optionally with a
00168        side-effect prefix, except [pc] (the name, not R15 as in ACR)
00169        isn't allowed for v32 and higher.
00170      T  Support register in bits <15:12>.
00171      u  4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
00172      U  Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
00173        Not recognized at disassembly.
00174      x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
00175      y Like 's' but do not allow an integer at assembly.
00176      Y The difference s-y; only an integer is allowed.
00177      z Size modifier (B or W) in bit <4>.  */
00178 
00179 
00180 /* Please note the order of the opcodes in this table is significant.
00181    The assembler requires that all instances of the same mnemonic must
00182    be consecutive.  If they aren't, the assembler might not recognize
00183    them, or may indicate an internal error.
00184 
00185    The disassembler should not normally care about the order of the
00186    opcodes, but will prefer an earlier alternative if the "match-score"
00187    (see cris-dis.c) is computed as equal.
00188 
00189    It should not be significant for proper execution that this table is
00190    in alphabetical order, but please follow that convention for an easy
00191    overview.  */
00192 
00193 const struct cris_opcode
00194 cris_opcodes[] =
00195 {
00196   {"abs",     0x06B0, 0x0940,               "r,R",     0, SIZE_NONE,     0,
00197    cris_abs_op},
00198 
00199   {"add",     0x0600, 0x09c0,               "m r,R",   0, SIZE_NONE,     0,
00200    cris_reg_mode_add_sub_cmp_and_or_move_op},
00201 
00202   {"add",     0x0A00, 0x01c0,               "m s,R",   0, SIZE_FIELD,    0,
00203    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00204 
00205   {"add",     0x0A00, 0x01c0,               "m S,D",   0, SIZE_NONE,
00206    cris_ver_v0_10,
00207    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00208 
00209   {"add",     0x0a00, 0x05c0,               "m S,R,r", 0, SIZE_NONE,
00210    cris_ver_v0_10,
00211    cris_three_operand_add_sub_cmp_and_or_op},
00212 
00213   {"add",     0x0A00, 0x01c0,               "m s,R",   0, SIZE_FIELD,
00214    cris_ver_v32p,
00215    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00216 
00217   {"addc",    0x0570, 0x0A80,               "r,R",     0, SIZE_FIX_32,
00218    cris_ver_v32p,
00219    cris_not_implemented_op},
00220 
00221   {"addc",    0x09A0, 0x0250,               "s,R",     0, SIZE_FIX_32,
00222    cris_ver_v32p,
00223    cris_not_implemented_op},
00224 
00225   {"addi",    0x0540, 0x0A80,               "x,r,A",   0, SIZE_NONE,
00226    cris_ver_v32p,
00227    cris_addi_op},
00228 
00229   {"addi",    0x0500, 0x0Ac0,               "x,r",     0, SIZE_NONE,     0,
00230    cris_addi_op},
00231 
00232   /* This collates after "addo", but we want to disassemble as "addoq",
00233      not "addo".  */
00234   {"addoq",   0x0100, 0x0E00,               "Q,A",     0, SIZE_NONE,
00235    cris_ver_v32p,
00236    cris_not_implemented_op},
00237 
00238   {"addo",    0x0940, 0x0280,               "m s,R,A", 0, SIZE_FIELD_SIGNED,
00239    cris_ver_v32p,
00240    cris_not_implemented_op},
00241 
00242   /* This must be located after the insn above, lest we misinterpret
00243      "addo.b -1,r0,acr" as "addo .b-1,r0,acr".  FIXME: Sounds like a
00244      parser bug.  */
00245   {"addo",   0x0100, 0x0E00,                "O,A",     0, SIZE_NONE,
00246    cris_ver_v32p,
00247    cris_not_implemented_op},
00248 
00249   {"addq",    0x0200, 0x0Dc0,               "I,R",     0, SIZE_NONE,     0,
00250    cris_quick_mode_add_sub_op},
00251 
00252   {"adds",    0x0420, 0x0Bc0,               "z r,R",   0, SIZE_NONE,     0,
00253    cris_reg_mode_add_sub_cmp_and_or_move_op},
00254 
00255   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
00256   {"adds",    0x0820, 0x03c0,               "z s,R",   0, SIZE_FIELD,    0,
00257    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00258 
00259   {"adds",    0x0820, 0x03c0,               "z S,D",   0, SIZE_NONE,
00260    cris_ver_v0_10,
00261    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00262 
00263   {"adds",    0x0820, 0x07c0,               "z S,R,r", 0, SIZE_NONE,
00264    cris_ver_v0_10,
00265    cris_three_operand_add_sub_cmp_and_or_op},
00266 
00267   {"addu",    0x0400, 0x0be0,               "z r,R",   0, SIZE_NONE,     0,
00268    cris_reg_mode_add_sub_cmp_and_or_move_op},
00269 
00270   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
00271   {"addu",    0x0800, 0x03e0,               "z s,R",   0, SIZE_FIELD,    0,
00272    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00273 
00274   {"addu",    0x0800, 0x03e0,               "z S,D",   0, SIZE_NONE,
00275    cris_ver_v0_10,
00276    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00277 
00278   {"addu",    0x0800, 0x07e0,               "z S,R,r", 0, SIZE_NONE,
00279    cris_ver_v0_10,
00280    cris_three_operand_add_sub_cmp_and_or_op},
00281 
00282   {"and",     0x0700, 0x08C0,               "m r,R",   0, SIZE_NONE,     0,
00283    cris_reg_mode_add_sub_cmp_and_or_move_op},
00284 
00285   {"and",     0x0B00, 0x00C0,               "m s,R",   0, SIZE_FIELD,    0,
00286    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00287 
00288   {"and",     0x0B00, 0x00C0,               "m S,D",   0, SIZE_NONE,
00289    cris_ver_v0_10,
00290    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00291 
00292   {"and",     0x0B00, 0x04C0,               "m S,R,r", 0, SIZE_NONE,
00293    cris_ver_v0_10,
00294    cris_three_operand_add_sub_cmp_and_or_op},
00295 
00296   {"andq",    0x0300, 0x0CC0,               "i,R",     0, SIZE_NONE,     0,
00297    cris_quick_mode_and_cmp_move_or_op},
00298 
00299   {"asr",     0x0780, 0x0840,               "m r,R",   0, SIZE_NONE,     0,
00300    cris_asr_op},
00301 
00302   {"asrq",    0x03a0, 0x0c40,               "c,R",     0, SIZE_NONE,     0,
00303    cris_asrq_op},
00304 
00305   {"ax",      0x15B0, 0xEA4F,               "",       0, SIZE_NONE,     0,
00306    cris_ax_ei_setf_op},
00307 
00308   /* FIXME: Should use branch #defines.  */
00309   {"b",             0x0dff, 0x0200,                "b",      1, SIZE_NONE,     0,
00310    cris_sixteen_bit_offset_branch_op},
00311 
00312   {"ba",
00313    BA_QUICK_OPCODE,
00314    0x0F00+(0xF-CC_A)*0x1000,                "o",      1, SIZE_NONE,     0,
00315    cris_eight_bit_offset_branch_op},
00316 
00317   /* Needs to come after the usual "ba o", which might be relaxed to
00318      this one.  */
00319   {"ba",     BA_DWORD_OPCODE,
00320    0xffff & (~BA_DWORD_OPCODE),             "n",      0, SIZE_FIX_32,
00321    cris_ver_v32p,
00322    cris_none_reg_mode_jump_op},
00323 
00324   {"bas",     0x0EBF, 0x0140,               "n,P",     0, SIZE_FIX_32,
00325    cris_ver_v32p,
00326    cris_none_reg_mode_jump_op},
00327 
00328   {"basc",     0x0EFF, 0x0100,              "n,P",     0, SIZE_FIX_32,
00329    cris_ver_v32p,
00330    cris_none_reg_mode_jump_op},
00331 
00332   {"bcc",
00333    BRANCH_QUICK_OPCODE+CC_CC*0x1000,
00334    0x0f00+(0xF-CC_CC)*0x1000,               "o",      1, SIZE_NONE,     0,
00335    cris_eight_bit_offset_branch_op},
00336 
00337   {"bcs",
00338    BRANCH_QUICK_OPCODE+CC_CS*0x1000,
00339    0x0f00+(0xF-CC_CS)*0x1000,               "o",      1, SIZE_NONE,     0,
00340    cris_eight_bit_offset_branch_op},
00341 
00342   {"bdap",
00343    BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS,  "pm s,R",  0, SIZE_FIELD_SIGNED,
00344    cris_ver_v0_10,
00345    cris_bdap_prefix},
00346 
00347   {"bdap",
00348    BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS,  "pO",       0, SIZE_NONE,
00349    cris_ver_v0_10,
00350    cris_quick_mode_bdap_prefix},
00351 
00352   {"beq",
00353    BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
00354    0x0f00+(0xF-CC_EQ)*0x1000,               "o",      1, SIZE_NONE,     0,
00355    cris_eight_bit_offset_branch_op},
00356 
00357   /* This is deliberately put before "bext" to trump it, even though not
00358      in alphabetical order, since we don't do excluding version checks
00359      for v0..v10.  */
00360   {"bwf",
00361    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
00362    0x0f00+(0xF-CC_EXT)*0x1000,              "o",      1, SIZE_NONE,
00363    cris_ver_v10,
00364    cris_eight_bit_offset_branch_op},
00365 
00366   {"bext",
00367    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
00368    0x0f00+(0xF-CC_EXT)*0x1000,              "o",      1, SIZE_NONE,
00369    cris_ver_v0_3,
00370    cris_eight_bit_offset_branch_op},
00371 
00372   {"bge",
00373    BRANCH_QUICK_OPCODE+CC_GE*0x1000,
00374    0x0f00+(0xF-CC_GE)*0x1000,               "o",      1, SIZE_NONE,     0,
00375    cris_eight_bit_offset_branch_op},
00376 
00377   {"bgt",
00378    BRANCH_QUICK_OPCODE+CC_GT*0x1000,
00379    0x0f00+(0xF-CC_GT)*0x1000,               "o",      1, SIZE_NONE,     0,
00380    cris_eight_bit_offset_branch_op},
00381 
00382   {"bhi",
00383    BRANCH_QUICK_OPCODE+CC_HI*0x1000,
00384    0x0f00+(0xF-CC_HI)*0x1000,               "o",      1, SIZE_NONE,     0,
00385    cris_eight_bit_offset_branch_op},
00386 
00387   {"bhs",
00388    BRANCH_QUICK_OPCODE+CC_HS*0x1000,
00389    0x0f00+(0xF-CC_HS)*0x1000,               "o",      1, SIZE_NONE,     0,
00390    cris_eight_bit_offset_branch_op},
00391 
00392   {"biap", BIAP_OPCODE, BIAP_Z_BITS,        "pm r,R",  0, SIZE_NONE,
00393    cris_ver_v0_10,
00394    cris_biap_prefix},
00395 
00396   {"ble",
00397    BRANCH_QUICK_OPCODE+CC_LE*0x1000,
00398    0x0f00+(0xF-CC_LE)*0x1000,               "o",      1, SIZE_NONE,     0,
00399    cris_eight_bit_offset_branch_op},
00400 
00401   {"blo",
00402    BRANCH_QUICK_OPCODE+CC_LO*0x1000,
00403    0x0f00+(0xF-CC_LO)*0x1000,               "o",      1, SIZE_NONE,     0,
00404    cris_eight_bit_offset_branch_op},
00405 
00406   {"bls",
00407    BRANCH_QUICK_OPCODE+CC_LS*0x1000,
00408    0x0f00+(0xF-CC_LS)*0x1000,               "o",      1, SIZE_NONE,     0,
00409    cris_eight_bit_offset_branch_op},
00410 
00411   {"blt",
00412    BRANCH_QUICK_OPCODE+CC_LT*0x1000,
00413    0x0f00+(0xF-CC_LT)*0x1000,               "o",      1, SIZE_NONE,     0,
00414    cris_eight_bit_offset_branch_op},
00415 
00416   {"bmi",
00417    BRANCH_QUICK_OPCODE+CC_MI*0x1000,
00418    0x0f00+(0xF-CC_MI)*0x1000,               "o",      1, SIZE_NONE,     0,
00419    cris_eight_bit_offset_branch_op},
00420 
00421   {"bmod",    0x0ab0, 0x0140,               "s,R",     0, SIZE_FIX_32,
00422    cris_ver_sim_v0_10,
00423    cris_not_implemented_op},
00424 
00425   {"bmod",    0x0ab0, 0x0140,               "S,D",     0, SIZE_NONE,
00426    cris_ver_sim_v0_10,
00427    cris_not_implemented_op},
00428 
00429   {"bmod",    0x0ab0, 0x0540,               "S,R,r",   0, SIZE_NONE,
00430    cris_ver_sim_v0_10,
00431    cris_not_implemented_op},
00432 
00433   {"bne",
00434    BRANCH_QUICK_OPCODE+CC_NE*0x1000,
00435    0x0f00+(0xF-CC_NE)*0x1000,               "o",      1, SIZE_NONE,     0,
00436    cris_eight_bit_offset_branch_op},
00437 
00438   {"bound",   0x05c0, 0x0A00,               "m r,R",   0, SIZE_NONE,     0,
00439    cris_two_operand_bound_op},
00440   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
00441   {"bound",   0x09c0, 0x0200,               "m s,R",   0, SIZE_FIELD,
00442    cris_ver_v0_10,
00443    cris_two_operand_bound_op},
00444   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
00445   {"bound",   0x0dcf, 0x0200,               "m Y,R",   0, SIZE_FIELD,    0,
00446    cris_two_operand_bound_op},
00447   {"bound",   0x09c0, 0x0200,               "m S,D",   0, SIZE_NONE,
00448    cris_ver_v0_10,
00449    cris_two_operand_bound_op},
00450   {"bound",   0x09c0, 0x0600,               "m S,R,r", 0, SIZE_NONE,
00451    cris_ver_v0_10,
00452    cris_three_operand_bound_op},
00453 
00454   {"bpl",
00455    BRANCH_QUICK_OPCODE+CC_PL*0x1000,
00456    0x0f00+(0xF-CC_PL)*0x1000,               "o",      1, SIZE_NONE,     0,
00457    cris_eight_bit_offset_branch_op},
00458 
00459   {"break",   0xe930, 0x16c0,               "C",      0, SIZE_NONE,
00460    cris_ver_v3p,
00461    cris_break_op},
00462 
00463   {"bsb",
00464    BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
00465    0x0f00+(0xF-CC_EXT)*0x1000,              "o",      1, SIZE_NONE,
00466    cris_ver_v32p,
00467    cris_eight_bit_offset_branch_op},
00468 
00469   {"bsr",     0xBEBF, 0x4140,               "n",      0, SIZE_FIX_32,
00470    cris_ver_v32p,
00471    cris_none_reg_mode_jump_op},
00472 
00473   {"bsrc",     0xBEFF, 0x4100,              "n",      0, SIZE_FIX_32,
00474    cris_ver_v32p,
00475    cris_none_reg_mode_jump_op},
00476 
00477   {"bstore",  0x0af0, 0x0100,               "s,R",     0, SIZE_FIX_32,
00478    cris_ver_warning,
00479    cris_not_implemented_op},
00480 
00481   {"bstore",  0x0af0, 0x0100,               "S,D",     0, SIZE_NONE,
00482    cris_ver_warning,
00483    cris_not_implemented_op},
00484 
00485   {"bstore",  0x0af0, 0x0500,               "S,R,r",   0, SIZE_NONE,
00486    cris_ver_warning,
00487    cris_not_implemented_op},
00488 
00489   {"btst",    0x04F0, 0x0B00,               "r,R",     0, SIZE_NONE,     0,
00490    cris_btst_nop_op},
00491   {"btstq",   0x0380, 0x0C60,               "c,R",     0, SIZE_NONE,     0,
00492    cris_btst_nop_op},
00493 
00494   {"bvc",
00495    BRANCH_QUICK_OPCODE+CC_VC*0x1000,
00496    0x0f00+(0xF-CC_VC)*0x1000,               "o",      1, SIZE_NONE,     0,
00497    cris_eight_bit_offset_branch_op},
00498 
00499   {"bvs",
00500    BRANCH_QUICK_OPCODE+CC_VS*0x1000,
00501    0x0f00+(0xF-CC_VS)*0x1000,               "o",      1, SIZE_NONE,     0,
00502    cris_eight_bit_offset_branch_op},
00503 
00504   {"clear",   0x0670, 0x3980,               "M r",     0, SIZE_NONE,     0,
00505    cris_reg_mode_clear_op},
00506 
00507   {"clear",   0x0A70, 0x3180,               "M y",     0, SIZE_NONE,     0,
00508    cris_none_reg_mode_clear_test_op},
00509 
00510   {"clear",   0x0A70, 0x3180,               "M S",     0, SIZE_NONE,
00511    cris_ver_v0_10,
00512    cris_none_reg_mode_clear_test_op},
00513 
00514   {"clearf",  0x05F0, 0x0A00,               "f",      0, SIZE_NONE,     0,
00515    cris_clearf_di_op},
00516 
00517   {"cmp",     0x06C0, 0x0900,               "m r,R",   0, SIZE_NONE,     0,
00518    cris_reg_mode_add_sub_cmp_and_or_move_op},
00519 
00520   {"cmp",     0x0Ac0, 0x0100,               "m s,R",   0, SIZE_FIELD,    0,
00521    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00522 
00523   {"cmp",     0x0Ac0, 0x0100,               "m S,D",   0, SIZE_NONE,
00524    cris_ver_v0_10,
00525    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00526 
00527   {"cmpq",    0x02C0, 0x0D00,               "i,R",     0, SIZE_NONE,     0,
00528    cris_quick_mode_and_cmp_move_or_op},
00529 
00530   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
00531   {"cmps",    0x08e0, 0x0300,               "z s,R",   0, SIZE_FIELD,    0,
00532    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00533 
00534   {"cmps",    0x08e0, 0x0300,               "z S,D",   0, SIZE_NONE,
00535    cris_ver_v0_10,
00536    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00537 
00538   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
00539   {"cmpu",    0x08c0, 0x0320,               "z s,R" ,  0, SIZE_FIELD,    0,
00540    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00541 
00542   {"cmpu",    0x08c0, 0x0320,               "z S,D",   0, SIZE_NONE,
00543    cris_ver_v0_10,
00544    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00545 
00546   {"di",      0x25F0, 0xDA0F,               "",       0, SIZE_NONE,     0,
00547    cris_clearf_di_op},
00548 
00549   {"dip",     DIP_OPCODE, DIP_Z_BITS,       "ps",            0, SIZE_FIX_32,
00550    cris_ver_v0_10,
00551    cris_dip_prefix},
00552 
00553   {"div",     0x0980, 0x0640,               "m R,r",   0, SIZE_FIELD,    0,
00554    cris_not_implemented_op},
00555 
00556   {"dstep",   0x06f0, 0x0900,               "r,R",     0, SIZE_NONE,     0,
00557    cris_dstep_logshift_mstep_neg_not_op},
00558 
00559   {"ei",      0x25B0, 0xDA4F,               "",       0, SIZE_NONE,     0,
00560    cris_ax_ei_setf_op},
00561 
00562   {"fidxd",    0x0ab0, 0xf540,              "[r]",     0, SIZE_NONE,
00563    cris_ver_v32p,
00564    cris_not_implemented_op},
00565 
00566   {"fidxi",    0x0d30, 0xF2C0,              "[r]",     0, SIZE_NONE,
00567    cris_ver_v32p,
00568    cris_not_implemented_op},
00569 
00570   {"ftagd",    0x1AB0, 0xE540,              "[r]",     0, SIZE_NONE,
00571    cris_ver_v32p,
00572    cris_not_implemented_op},
00573 
00574   {"ftagi",    0x1D30, 0xE2C0,              "[r]",     0, SIZE_NONE,
00575    cris_ver_v32p,
00576    cris_not_implemented_op},
00577 
00578   {"halt",    0xF930, 0x06CF,               "",       0, SIZE_NONE,
00579    cris_ver_v32p,
00580    cris_not_implemented_op},
00581 
00582   {"jas",    0x09B0, 0x0640,                "r,P",     0, SIZE_NONE,
00583    cris_ver_v32p,
00584    cris_reg_mode_jump_op},
00585 
00586   {"jas",    0x0DBF, 0x0240,                "N,P",     0, SIZE_FIX_32,
00587    cris_ver_v32p,
00588    cris_reg_mode_jump_op},
00589 
00590   {"jasc",    0x0B30, 0x04C0,               "r,P",     0, SIZE_NONE,
00591    cris_ver_v32p,
00592    cris_reg_mode_jump_op},
00593 
00594   {"jasc",    0x0F3F, 0x00C0,               "N,P",     0, SIZE_FIX_32,
00595    cris_ver_v32p,
00596    cris_reg_mode_jump_op},
00597 
00598   {"jbrc",    0x69b0, 0x9640,               "r",      0, SIZE_NONE,
00599    cris_ver_v8_10,
00600    cris_reg_mode_jump_op},
00601 
00602   {"jbrc",    0x6930, 0x92c0,               "s",      0, SIZE_FIX_32,
00603    cris_ver_v8_10,
00604    cris_none_reg_mode_jump_op},
00605 
00606   {"jbrc",    0x6930, 0x92c0,               "S",      0, SIZE_NONE,
00607    cris_ver_v8_10,
00608    cris_none_reg_mode_jump_op},
00609 
00610   {"jir",     0xA9b0, 0x5640,               "r",      0, SIZE_NONE,
00611    cris_ver_v8_10,
00612    cris_reg_mode_jump_op},
00613 
00614   {"jir",     0xA930, 0x52c0,               "s",      0, SIZE_FIX_32,
00615    cris_ver_v8_10,
00616    cris_none_reg_mode_jump_op},
00617 
00618   {"jir",     0xA930, 0x52c0,               "S",      0, SIZE_NONE,
00619    cris_ver_v8_10,
00620    cris_none_reg_mode_jump_op},
00621 
00622   {"jirc",    0x29b0, 0xd640,               "r",      0, SIZE_NONE,
00623    cris_ver_v8_10,
00624    cris_reg_mode_jump_op},
00625 
00626   {"jirc",    0x2930, 0xd2c0,               "s",      0, SIZE_FIX_32,
00627    cris_ver_v8_10,
00628    cris_none_reg_mode_jump_op},
00629 
00630   {"jirc",    0x2930, 0xd2c0,               "S",      0, SIZE_NONE,
00631    cris_ver_v8_10,
00632    cris_none_reg_mode_jump_op},
00633 
00634   {"jsr",     0xB9b0, 0x4640,               "r",      0, SIZE_NONE,     0,
00635    cris_reg_mode_jump_op},
00636 
00637   {"jsr",     0xB930, 0x42c0,               "s",      0, SIZE_FIX_32,
00638    cris_ver_v0_10,
00639    cris_none_reg_mode_jump_op},
00640 
00641   {"jsr",     0xBDBF, 0x4240,               "N",      0, SIZE_FIX_32,
00642    cris_ver_v32p,
00643    cris_none_reg_mode_jump_op},
00644 
00645   {"jsr",     0xB930, 0x42c0,               "S",      0, SIZE_NONE,
00646    cris_ver_v0_10,
00647    cris_none_reg_mode_jump_op},
00648 
00649   {"jsrc",    0x39b0, 0xc640,               "r",      0, SIZE_NONE,
00650    cris_ver_v8_10,
00651    cris_reg_mode_jump_op},
00652 
00653   {"jsrc",    0x3930, 0xc2c0,               "s",      0, SIZE_FIX_32,
00654    cris_ver_v8_10,
00655    cris_none_reg_mode_jump_op},
00656 
00657   {"jsrc",    0x3930, 0xc2c0,               "S",      0, SIZE_NONE,
00658    cris_ver_v8_10,
00659    cris_none_reg_mode_jump_op},
00660 
00661   {"jsrc",    0xBB30, 0x44C0,               "r",       0, SIZE_NONE,
00662    cris_ver_v32p,
00663    cris_reg_mode_jump_op},
00664 
00665   {"jsrc",    0xBF3F, 0x40C0,               "N",      0, SIZE_FIX_32,
00666    cris_ver_v32p,
00667    cris_reg_mode_jump_op},
00668 
00669   {"jump",    0x09b0, 0xF640,               "r",      0, SIZE_NONE,     0,
00670    cris_reg_mode_jump_op},
00671 
00672   {"jump",
00673    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "s",        0, SIZE_FIX_32,
00674    cris_ver_v0_10,
00675    cris_none_reg_mode_jump_op},
00676 
00677   {"jump",
00678    JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS,  "S",        0, SIZE_NONE,
00679    cris_ver_v0_10,
00680    cris_none_reg_mode_jump_op},
00681 
00682   {"jump",    0x09F0, 0x060F,               "P",      0, SIZE_NONE,
00683    cris_ver_v32p,
00684    cris_none_reg_mode_jump_op},
00685 
00686   {"jump",
00687    JUMP_PC_INCR_OPCODE_V32,
00688    (0xffff & ~JUMP_PC_INCR_OPCODE_V32),     "N",      0, SIZE_FIX_32,
00689    cris_ver_v32p,
00690    cris_none_reg_mode_jump_op},
00691 
00692   {"jmpu",    0x8930, 0x72c0,               "s",      0, SIZE_FIX_32,
00693    cris_ver_v10,
00694    cris_none_reg_mode_jump_op},
00695 
00696   {"jmpu",    0x8930, 0x72c0,                "S",            0, SIZE_NONE,
00697    cris_ver_v10,
00698    cris_none_reg_mode_jump_op},
00699 
00700   {"lapc",    0x0970, 0x0680,               "U,R",    0, SIZE_NONE,
00701    cris_ver_v32p,
00702    cris_not_implemented_op},
00703 
00704   {"lapc",    0x0D7F, 0x0280,               "dn,R",    0, SIZE_FIX_32,
00705    cris_ver_v32p,
00706    cris_not_implemented_op},
00707 
00708   {"lapcq",   0x0970, 0x0680,               "u,R",     0, SIZE_NONE,
00709    cris_ver_v32p,
00710    cris_addi_op},
00711 
00712   {"lsl",     0x04C0, 0x0B00,               "m r,R",   0, SIZE_NONE,     0,
00713    cris_dstep_logshift_mstep_neg_not_op},
00714 
00715   {"lslq",    0x03c0, 0x0C20,               "c,R",     0, SIZE_NONE,     0,
00716    cris_dstep_logshift_mstep_neg_not_op},
00717 
00718   {"lsr",     0x07C0, 0x0800,               "m r,R",   0, SIZE_NONE,     0,
00719    cris_dstep_logshift_mstep_neg_not_op},
00720 
00721   {"lsrq",    0x03e0, 0x0C00,               "c,R",     0, SIZE_NONE,     0,
00722    cris_dstep_logshift_mstep_neg_not_op},
00723 
00724   {"lz",      0x0730, 0x08C0,               "r,R",     0, SIZE_NONE,
00725    cris_ver_v3p,
00726    cris_not_implemented_op},
00727 
00728   {"mcp",      0x07f0, 0x0800,              "P,r",     0, SIZE_NONE,
00729    cris_ver_v32p,
00730    cris_not_implemented_op},
00731 
00732   {"move",    0x0640, 0x0980,               "m r,R",   0, SIZE_NONE,     0,
00733    cris_reg_mode_add_sub_cmp_and_or_move_op},
00734 
00735   {"move",    0x0A40, 0x0180,               "m s,R",   0, SIZE_FIELD,    0,
00736    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00737 
00738   {"move",    0x0A40, 0x0180,               "m S,D",   0, SIZE_NONE,
00739    cris_ver_v0_10,
00740    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00741 
00742   {"move",    0x0630, 0x09c0,               "r,P",     0, SIZE_NONE,     0,
00743    cris_move_to_preg_op},
00744 
00745   {"move",    0x0670, 0x0980,               "P,r",     0, SIZE_NONE,     0,
00746    cris_reg_mode_move_from_preg_op},
00747 
00748   {"move",    0x0BC0, 0x0000,               "m R,y",   0, SIZE_FIELD,    0,
00749    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00750 
00751   {"move",    0x0BC0, 0x0000,               "m D,S",   0, SIZE_NONE,
00752    cris_ver_v0_10,
00753    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00754 
00755   {"move",
00756    MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
00757    "s,P",   0, SIZE_SPEC_REG, 0,
00758    cris_move_to_preg_op},
00759 
00760   {"move",    0x0A30, 0x01c0,               "S,P",     0, SIZE_NONE,
00761    cris_ver_v0_10,
00762    cris_move_to_preg_op},
00763 
00764   {"move",    0x0A70, 0x0180,               "P,y",     0, SIZE_SPEC_REG, 0,
00765    cris_none_reg_mode_move_from_preg_op},
00766 
00767   {"move",    0x0A70, 0x0180,               "P,S",     0, SIZE_NONE,
00768    cris_ver_v0_10,
00769    cris_none_reg_mode_move_from_preg_op},
00770 
00771   {"move",    0x0B70, 0x0480,               "r,T",     0, SIZE_NONE,
00772    cris_ver_v32p,
00773    cris_not_implemented_op},
00774 
00775   {"move",    0x0F70, 0x0080,               "T,r",     0, SIZE_NONE,
00776    cris_ver_v32p,
00777    cris_not_implemented_op},
00778 
00779   {"movem",   0x0BF0, 0x0000,               "R,y",     0, SIZE_FIX_32,   0,
00780    cris_move_reg_to_mem_movem_op},
00781 
00782   {"movem",   0x0BF0, 0x0000,               "D,S",     0, SIZE_NONE,
00783    cris_ver_v0_10,
00784    cris_move_reg_to_mem_movem_op},
00785 
00786   {"movem",   0x0BB0, 0x0040,               "s,R",     0, SIZE_FIX_32,   0,
00787    cris_move_mem_to_reg_movem_op},
00788 
00789   {"movem",   0x0BB0, 0x0040,               "S,D",     0, SIZE_NONE,
00790    cris_ver_v0_10,
00791    cris_move_mem_to_reg_movem_op},
00792 
00793   {"moveq",   0x0240, 0x0D80,               "i,R",     0, SIZE_NONE,     0,
00794    cris_quick_mode_and_cmp_move_or_op},
00795 
00796   {"movs",    0x0460, 0x0B80,               "z r,R",   0, SIZE_NONE,     0,
00797    cris_reg_mode_add_sub_cmp_and_or_move_op},
00798 
00799   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
00800   {"movs",    0x0860, 0x0380,               "z s,R",   0, SIZE_FIELD,    0,
00801    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00802 
00803   {"movs",    0x0860, 0x0380,               "z S,D",   0, SIZE_NONE,
00804    cris_ver_v0_10,
00805    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00806 
00807   {"movu",    0x0440, 0x0Ba0,               "z r,R",   0, SIZE_NONE,     0,
00808    cris_reg_mode_add_sub_cmp_and_or_move_op},
00809 
00810   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
00811   {"movu",    0x0840, 0x03a0,               "z s,R",   0, SIZE_FIELD,    0,
00812    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00813 
00814   {"movu",    0x0840, 0x03a0,               "z S,D",   0, SIZE_NONE,
00815    cris_ver_v0_10,
00816    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00817 
00818   {"mstep",   0x07f0, 0x0800,               "r,R",     0, SIZE_NONE,
00819    cris_ver_v0_10,
00820    cris_dstep_logshift_mstep_neg_not_op},
00821 
00822   {"muls",    0x0d00, 0x02c0,               "m r,R",   0, SIZE_NONE,
00823    cris_ver_v10p,
00824    cris_muls_op},
00825 
00826   {"mulu",    0x0900, 0x06c0,               "m r,R",   0, SIZE_NONE,
00827    cris_ver_v10p,
00828    cris_mulu_op},
00829 
00830   {"neg",     0x0580, 0x0A40,               "m r,R",   0, SIZE_NONE,     0,
00831    cris_dstep_logshift_mstep_neg_not_op},
00832 
00833   {"nop",     NOP_OPCODE, NOP_Z_BITS,       "",       0, SIZE_NONE,
00834    cris_ver_v0_10,
00835    cris_btst_nop_op},
00836 
00837   {"nop",     NOP_OPCODE_V32, NOP_Z_BITS_V32, "",    0, SIZE_NONE,
00838    cris_ver_v32p,
00839    cris_btst_nop_op},
00840 
00841   {"not",     0x8770, 0x7880,               "r",      0, SIZE_NONE,     0,
00842    cris_dstep_logshift_mstep_neg_not_op},
00843 
00844   {"or",      0x0740, 0x0880,               "m r,R",   0, SIZE_NONE,     0,
00845    cris_reg_mode_add_sub_cmp_and_or_move_op},
00846 
00847   {"or",      0x0B40, 0x0080,               "m s,R",   0, SIZE_FIELD,    0,
00848    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00849 
00850   {"or",      0x0B40, 0x0080,               "m S,D",   0, SIZE_NONE,
00851    cris_ver_v0_10,
00852    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00853 
00854   {"or",      0x0B40, 0x0480,               "m S,R,r", 0, SIZE_NONE,
00855    cris_ver_v0_10,
00856    cris_three_operand_add_sub_cmp_and_or_op},
00857 
00858   {"orq",     0x0340, 0x0C80,               "i,R",     0, SIZE_NONE,     0,
00859    cris_quick_mode_and_cmp_move_or_op},
00860 
00861   {"pop",     0x0E6E, 0x0191,               "!R",            0, SIZE_NONE,
00862    cris_ver_v0_10,
00863    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00864 
00865   {"pop",     0x0e3e, 0x01c1,               "!P",            0, SIZE_NONE,
00866    cris_ver_v0_10,
00867    cris_none_reg_mode_move_from_preg_op},
00868 
00869   {"push",    0x0FEE, 0x0011,               "BR",            0, SIZE_NONE,
00870    cris_ver_v0_10,
00871    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
00872 
00873   {"push",    0x0E7E, 0x0181,               "BP",            0, SIZE_NONE,
00874    cris_ver_v0_10,
00875    cris_move_to_preg_op},
00876 
00877   {"rbf",     0x3b30, 0xc0c0,               "y",      0, SIZE_NONE,
00878    cris_ver_v10,
00879    cris_not_implemented_op},
00880 
00881   {"rbf",     0x3b30, 0xc0c0,               "S",      0, SIZE_NONE,
00882    cris_ver_v10,
00883    cris_not_implemented_op},
00884 
00885   {"rfe",     0x2930, 0xD6CF,               "",       0, SIZE_NONE,
00886    cris_ver_v32p,
00887    cris_not_implemented_op},
00888 
00889   {"rfg",     0x4930, 0xB6CF,               "",       0, SIZE_NONE,
00890    cris_ver_v32p,
00891    cris_not_implemented_op},
00892 
00893   {"rfn",     0x5930, 0xA6CF,               "",       0, SIZE_NONE,
00894    cris_ver_v32p,
00895    cris_not_implemented_op},
00896 
00897   {"ret",     0xB67F, 0x4980,               "",       1, SIZE_NONE,
00898    cris_ver_v0_10,
00899    cris_reg_mode_move_from_preg_op},
00900 
00901   {"ret",     0xB9F0, 0x460F,               "",       1, SIZE_NONE,
00902    cris_ver_v32p,
00903    cris_reg_mode_move_from_preg_op},
00904 
00905   {"retb",    0xe67f, 0x1980,               "",       1, SIZE_NONE,
00906    cris_ver_v0_10,
00907    cris_reg_mode_move_from_preg_op},
00908 
00909   {"rete",     0xA9F0, 0x560F,              "",       1, SIZE_NONE,
00910    cris_ver_v32p,
00911    cris_reg_mode_move_from_preg_op},
00912 
00913   {"reti",    0xA67F, 0x5980,               "",       1, SIZE_NONE,
00914    cris_ver_v0_10,
00915    cris_reg_mode_move_from_preg_op},
00916 
00917   {"retn",     0xC9F0, 0x360F,              "",       1, SIZE_NONE,
00918    cris_ver_v32p,
00919    cris_reg_mode_move_from_preg_op},
00920 
00921   {"sbfs",    0x3b70, 0xc080,               "y",      0, SIZE_NONE,
00922    cris_ver_v10,
00923    cris_not_implemented_op},
00924 
00925   {"sbfs",    0x3b70, 0xc080,               "S",      0, SIZE_NONE,
00926    cris_ver_v10,
00927    cris_not_implemented_op},
00928 
00929   {"sa",
00930    0x0530+CC_A*0x1000,
00931    0x0AC0+(0xf-CC_A)*0x1000,                "r",      0, SIZE_NONE,     0,
00932    cris_scc_op},
00933 
00934   {"ssb",
00935    0x0530+CC_EXT*0x1000,
00936    0x0AC0+(0xf-CC_EXT)*0x1000,              "r",      0, SIZE_NONE,
00937    cris_ver_v32p,
00938    cris_scc_op},
00939 
00940   {"scc",
00941    0x0530+CC_CC*0x1000,
00942    0x0AC0+(0xf-CC_CC)*0x1000,               "r",      0, SIZE_NONE,     0,
00943    cris_scc_op},
00944 
00945   {"scs",
00946    0x0530+CC_CS*0x1000,
00947    0x0AC0+(0xf-CC_CS)*0x1000,               "r",      0, SIZE_NONE,     0,
00948    cris_scc_op},
00949 
00950   {"seq",
00951    0x0530+CC_EQ*0x1000,
00952    0x0AC0+(0xf-CC_EQ)*0x1000,               "r",      0, SIZE_NONE,     0,
00953    cris_scc_op},
00954 
00955   {"setf",    0x05b0, 0x0A40,               "f",      0, SIZE_NONE,     0,
00956    cris_ax_ei_setf_op},
00957 
00958   {"sfe",    0x3930, 0xC6CF,                "",       0, SIZE_NONE,
00959    cris_ver_v32p,
00960    cris_not_implemented_op},
00961 
00962   /* Need to have "swf" in front of "sext" so it is the one displayed in
00963      disassembly.  */
00964   {"swf",
00965    0x0530+CC_EXT*0x1000,
00966    0x0AC0+(0xf-CC_EXT)*0x1000,              "r",      0, SIZE_NONE,
00967    cris_ver_v10,
00968    cris_scc_op},
00969 
00970   {"sext",
00971    0x0530+CC_EXT*0x1000,
00972    0x0AC0+(0xf-CC_EXT)*0x1000,              "r",      0, SIZE_NONE,
00973    cris_ver_v0_3,
00974    cris_scc_op},
00975 
00976   {"sge",
00977    0x0530+CC_GE*0x1000,
00978    0x0AC0+(0xf-CC_GE)*0x1000,               "r",      0, SIZE_NONE,     0,
00979    cris_scc_op},
00980 
00981   {"sgt",
00982    0x0530+CC_GT*0x1000,
00983    0x0AC0+(0xf-CC_GT)*0x1000,               "r",      0, SIZE_NONE,     0,
00984    cris_scc_op},
00985 
00986   {"shi",
00987    0x0530+CC_HI*0x1000,
00988    0x0AC0+(0xf-CC_HI)*0x1000,               "r",      0, SIZE_NONE,     0,
00989    cris_scc_op},
00990 
00991   {"shs",
00992    0x0530+CC_HS*0x1000,
00993    0x0AC0+(0xf-CC_HS)*0x1000,               "r",      0, SIZE_NONE,     0,
00994    cris_scc_op},
00995 
00996   {"sle",
00997    0x0530+CC_LE*0x1000,
00998    0x0AC0+(0xf-CC_LE)*0x1000,               "r",      0, SIZE_NONE,     0,
00999    cris_scc_op},
01000 
01001   {"slo",
01002    0x0530+CC_LO*0x1000,
01003    0x0AC0+(0xf-CC_LO)*0x1000,               "r",      0, SIZE_NONE,     0,
01004    cris_scc_op},
01005 
01006   {"sls",
01007    0x0530+CC_LS*0x1000,
01008    0x0AC0+(0xf-CC_LS)*0x1000,               "r",      0, SIZE_NONE,     0,
01009    cris_scc_op},
01010 
01011   {"slt",
01012    0x0530+CC_LT*0x1000,
01013    0x0AC0+(0xf-CC_LT)*0x1000,               "r",      0, SIZE_NONE,     0,
01014    cris_scc_op},
01015 
01016   {"smi",
01017    0x0530+CC_MI*0x1000,
01018    0x0AC0+(0xf-CC_MI)*0x1000,               "r",      0, SIZE_NONE,     0,
01019    cris_scc_op},
01020 
01021   {"sne",
01022    0x0530+CC_NE*0x1000,
01023    0x0AC0+(0xf-CC_NE)*0x1000,               "r",      0, SIZE_NONE,     0,
01024    cris_scc_op},
01025 
01026   {"spl",
01027    0x0530+CC_PL*0x1000,
01028    0x0AC0+(0xf-CC_PL)*0x1000,               "r",      0, SIZE_NONE,     0,
01029    cris_scc_op},
01030 
01031   {"sub",     0x0680, 0x0940,               "m r,R",   0, SIZE_NONE,     0,
01032    cris_reg_mode_add_sub_cmp_and_or_move_op},
01033 
01034   {"sub",     0x0a80, 0x0140,               "m s,R",   0, SIZE_FIELD,    0,
01035    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
01036 
01037   {"sub",     0x0a80, 0x0140,               "m S,D",   0, SIZE_NONE,
01038    cris_ver_v0_10,
01039    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
01040 
01041   {"sub",     0x0a80, 0x0540,               "m S,R,r", 0, SIZE_NONE,
01042    cris_ver_v0_10,
01043    cris_three_operand_add_sub_cmp_and_or_op},
01044 
01045   {"subq",    0x0280, 0x0d40,               "I,R",     0, SIZE_NONE,     0,
01046    cris_quick_mode_add_sub_op},
01047 
01048   {"subs",    0x04a0, 0x0b40,               "z r,R",   0, SIZE_NONE,     0,
01049    cris_reg_mode_add_sub_cmp_and_or_move_op},
01050 
01051   /* FIXME: SIZE_FIELD_SIGNED and all necessary changes.  */
01052   {"subs",    0x08a0, 0x0340,               "z s,R",   0, SIZE_FIELD,    0,
01053    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
01054 
01055   {"subs",    0x08a0, 0x0340,               "z S,D",   0, SIZE_NONE,
01056    cris_ver_v0_10,
01057    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
01058 
01059   {"subs",    0x08a0, 0x0740,               "z S,R,r", 0, SIZE_NONE,
01060    cris_ver_v0_10,
01061    cris_three_operand_add_sub_cmp_and_or_op},
01062 
01063   {"subu",    0x0480, 0x0b60,               "z r,R",   0, SIZE_NONE,     0,
01064    cris_reg_mode_add_sub_cmp_and_or_move_op},
01065 
01066   /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes.  */
01067   {"subu",    0x0880, 0x0360,               "z s,R",   0, SIZE_FIELD,    0,
01068    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
01069 
01070   {"subu",    0x0880, 0x0360,               "z S,D",   0, SIZE_NONE,
01071    cris_ver_v0_10,
01072    cris_none_reg_mode_add_sub_cmp_and_or_move_op},
01073 
01074   {"subu",    0x0880, 0x0760,               "z S,R,r", 0, SIZE_NONE,
01075    cris_ver_v0_10,
01076    cris_three_operand_add_sub_cmp_and_or_op},
01077 
01078   {"svc",
01079    0x0530+CC_VC*0x1000,
01080    0x0AC0+(0xf-CC_VC)*0x1000,               "r",      0, SIZE_NONE,     0,
01081    cris_scc_op},
01082 
01083   {"svs",
01084    0x0530+CC_VS*0x1000,
01085    0x0AC0+(0xf-CC_VS)*0x1000,               "r",      0, SIZE_NONE,     0,
01086    cris_scc_op},
01087 
01088   /* The insn "swapn" is the same as "not" and will be disassembled as
01089      such, but the swap* family of mnmonics are generally v8-and-higher
01090      only, so count it in.  */
01091   {"swapn",   0x8770, 0x7880,               "r",      0, SIZE_NONE,
01092    cris_ver_v8p,
01093    cris_not_implemented_op},
01094 
01095   {"swapw",   0x4770, 0xb880,               "r",      0, SIZE_NONE,
01096    cris_ver_v8p,
01097    cris_not_implemented_op},
01098 
01099   {"swapnw",  0xc770, 0x3880,               "r",      0, SIZE_NONE,
01100    cris_ver_v8p,
01101    cris_not_implemented_op},
01102 
01103   {"swapb",   0x2770, 0xd880,               "r",      0, SIZE_NONE,
01104    cris_ver_v8p,
01105    cris_not_implemented_op},
01106 
01107   {"swapnb",  0xA770, 0x5880,               "r",      0, SIZE_NONE,
01108    cris_ver_v8p,
01109    cris_not_implemented_op},
01110 
01111   {"swapwb",  0x6770, 0x9880,               "r",      0, SIZE_NONE,
01112    cris_ver_v8p,
01113    cris_not_implemented_op},
01114 
01115   {"swapnwb", 0xE770, 0x1880,               "r",      0, SIZE_NONE,
01116    cris_ver_v8p,
01117    cris_not_implemented_op},
01118 
01119   {"swapr",   0x1770, 0xe880,               "r",      0, SIZE_NONE,
01120    cris_ver_v8p,
01121    cris_not_implemented_op},
01122 
01123   {"swapnr",  0x9770, 0x6880,               "r",      0, SIZE_NONE,
01124    cris_ver_v8p,
01125    cris_not_implemented_op},
01126 
01127   {"swapwr",  0x5770, 0xa880,               "r",      0, SIZE_NONE,
01128    cris_ver_v8p,
01129    cris_not_implemented_op},
01130 
01131   {"swapnwr", 0xd770, 0x2880,               "r",      0, SIZE_NONE,
01132    cris_ver_v8p,
01133    cris_not_implemented_op},
01134 
01135   {"swapbr",  0x3770, 0xc880,               "r",      0, SIZE_NONE,
01136    cris_ver_v8p,
01137    cris_not_implemented_op},
01138 
01139   {"swapnbr", 0xb770, 0x4880,               "r",      0, SIZE_NONE,
01140    cris_ver_v8p,
01141    cris_not_implemented_op},
01142 
01143   {"swapwbr", 0x7770, 0x8880,               "r",      0, SIZE_NONE,
01144    cris_ver_v8p,
01145    cris_not_implemented_op},
01146 
01147   {"swapnwbr", 0xf770, 0x0880,              "r",      0, SIZE_NONE,
01148    cris_ver_v8p,
01149    cris_not_implemented_op},
01150 
01151   {"test",    0x0640, 0x0980,               "m D",     0, SIZE_NONE,
01152    cris_ver_v0_10,
01153    cris_reg_mode_test_op},
01154 
01155   {"test",    0x0b80, 0xf040,               "m y",     0, SIZE_FIELD,    0,
01156    cris_none_reg_mode_clear_test_op},
01157 
01158   {"test",    0x0b80, 0xf040,               "m S",     0, SIZE_NONE,
01159    cris_ver_v0_10,
01160    cris_none_reg_mode_clear_test_op},
01161 
01162   {"xor",     0x07B0, 0x0840,               "r,R",     0, SIZE_NONE,     0,
01163    cris_xor_op},
01164 
01165   {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
01166 };
01167 
01168 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
01169 const char * const
01170 cris_cc_strings[] =
01171 {
01172   "hs",
01173   "lo",
01174   "ne",
01175   "eq",
01176   "vc",
01177   "vs",
01178   "pl",
01179   "mi",
01180   "ls",
01181   "hi",
01182   "ge",
01183   "lt",
01184   "gt",
01185   "le",
01186   "a",
01187   /* This is a placeholder.  In v0, this would be "ext".  In v32, this
01188      is "sb".  See cris_conds15.  */
01189   "wf"
01190 };
01191 
01192 /* Different names and semantics for condition 1111 (0xf).  */
01193 const struct cris_cond15 cris_cond15s[] =
01194 {
01195   /* FIXME: In what version did condition "ext" disappear?  */
01196   {"ext", cris_ver_v0_3},
01197   {"wf", cris_ver_v10},
01198   {"sb", cris_ver_v32p},
01199   {NULL, 0}
01200 };
01201 
01202 
01203 /*
01204  * Local variables:
01205  * eval: (c-set-style "gnu")
01206  * indent-tabs-mode: t
01207  * End:
01208  */