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cell-binutils  2.17cvs20070401
cpu-ia64-opc.c
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00001 /* Copyright 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2006
00002    Free Software Foundation, Inc.
00003    Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
00004 
00005 This file is part of BFD, the Binary File Descriptor library.
00006 
00007 This program is free software; you can redistribute it and/or modify
00008 it under the terms of the GNU General Public License as published by
00009 the Free Software Foundation; either version 2 of the License, or
00010 (at your option) any later version.
00011 
00012 This program is distributed in the hope that it will be useful,
00013 but WITHOUT ANY WARRANTY; without even the implied warranty of
00014 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00015 GNU General Public License for more details.
00016 
00017 You should have received a copy of the GNU General Public License
00018 along with this program; if not, write to the Free Software
00019 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00020 
00021 /* Logically, this code should be part of libopcode but since some of
00022    the operand insertion/extraction functions help bfd to implement
00023    relocations, this code is included as part of cpu-ia64.c.  This
00024    avoids circular dependencies between libopcode and libbfd and also
00025    obviates the need for applications to link in libopcode when all
00026    they really want is libbfd.
00027 
00028    --davidm Mon Apr 13 22:14:02 1998 */
00029 
00030 #include "../opcodes/ia64-opc.h"
00031 
00032 #define NELEMS(a)  ((int) (sizeof (a) / sizeof ((a)[0])))
00033 
00034 static const char*
00035 ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
00036          ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
00037 {
00038   return "internal error---this shouldn't happen";
00039 }
00040 
00041 static const char*
00042 ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
00043          ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
00044 {
00045   return "internal error---this shouldn't happen";
00046 }
00047 
00048 static const char*
00049 ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
00050           ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
00051 {
00052   return 0;
00053 }
00054 
00055 static const char*
00056 ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
00057           ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
00058 {
00059   return 0;
00060 }
00061 
00062 static const char*
00063 ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00064 {
00065   if (value >= 1u << self->field[0].bits)
00066     return "register number out of range";
00067 
00068   *code |= value << self->field[0].shift;
00069   return 0;
00070 }
00071 
00072 static const char*
00073 ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00074 {
00075   *valuep = ((code >> self->field[0].shift)
00076             & ((1u << self->field[0].bits) - 1));
00077   return 0;
00078 }
00079 
00080 static const char*
00081 ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00082 {
00083   ia64_insn new = 0;
00084   int i;
00085 
00086   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
00087     {
00088       new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
00089              << self->field[i].shift);
00090       value >>= self->field[i].bits;
00091     }
00092   if (value)
00093     return "integer operand out of range";
00094 
00095   *code |= new;
00096   return 0;
00097 }
00098 
00099 static const char*
00100 ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00101 {
00102   BFD_HOST_U_64_BIT value = 0;
00103   int i, bits = 0, total = 0;
00104 
00105   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
00106     {
00107       bits = self->field[i].bits;
00108       value |= ((code >> self->field[i].shift)
00109               & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
00110       total += bits;
00111     }
00112   *valuep = value;
00113   return 0;
00114 }
00115 
00116 static const char*
00117 ins_immu5b (const struct ia64_operand *self, ia64_insn value,
00118            ia64_insn *code)
00119 {
00120   if (value < 32 || value > 63)
00121     return "value must be between 32 and 63";
00122   return ins_immu (self, value - 32, code);
00123 }
00124 
00125 static const char*
00126 ext_immu5b (const struct ia64_operand *self, ia64_insn code,
00127            ia64_insn *valuep)
00128 {
00129   const char *result;
00130 
00131   result = ext_immu (self, code, valuep);
00132   if (result)
00133     return result;
00134 
00135   *valuep = *valuep + 32;
00136   return 0;
00137 }
00138 
00139 static const char*
00140 ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00141 {
00142   if (value & 0x7)
00143     return "value not an integer multiple of 8";
00144   return ins_immu (self, value >> 3, code);
00145 }
00146 
00147 static const char*
00148 ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00149 {
00150   const char *result;
00151 
00152   result = ext_immu (self, code, valuep);
00153   if (result)
00154     return result;
00155 
00156   *valuep = *valuep << 3;
00157   return 0;
00158 }
00159 
00160 static const char*
00161 ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
00162                ia64_insn *code, int scale)
00163 {
00164   BFD_HOST_64_BIT svalue = value, sign_bit = 0;
00165   ia64_insn new = 0;
00166   int i;
00167 
00168   svalue >>= scale;
00169 
00170   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
00171     {
00172       new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
00173              << self->field[i].shift);
00174       sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
00175       svalue >>= self->field[i].bits;
00176     }
00177   if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
00178     return "integer operand out of range";
00179 
00180   *code |= new;
00181   return 0;
00182 }
00183 
00184 static const char*
00185 ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
00186                ia64_insn *valuep, int scale)
00187 {
00188   int i, bits = 0, total = 0;
00189   BFD_HOST_64_BIT val = 0, sign;
00190 
00191   for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
00192     {
00193       bits = self->field[i].bits;
00194       val |= ((code >> self->field[i].shift)
00195              & ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
00196       total += bits;
00197     }
00198   /* sign extend: */
00199   sign = (BFD_HOST_64_BIT) 1 << (total - 1);
00200   val = (val ^ sign) - sign;
00201 
00202   *valuep = (val << scale);
00203   return 0;
00204 }
00205 
00206 static const char*
00207 ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00208 {
00209   return ins_imms_scaled (self, value, code, 0);
00210 }
00211 
00212 static const char*
00213 ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00214 {
00215   value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
00216 
00217   return ins_imms_scaled (self, value, code, 0);
00218 }
00219 
00220 static const char*
00221 ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00222 {
00223   return ext_imms_scaled (self, code, valuep, 0);
00224 }
00225 
00226 static const char*
00227 ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00228 {
00229   --value;
00230   return ins_imms_scaled (self, value, code, 0);
00231 }
00232 
00233 static const char*
00234 ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
00235              ia64_insn *code)
00236 {
00237   value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
00238 
00239   --value;
00240   return ins_imms_scaled (self, value, code, 0);
00241 }
00242 
00243 static const char*
00244 ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00245 {
00246   const char *res = ext_imms_scaled (self, code, valuep, 0);
00247 
00248   ++*valuep;
00249   return res;
00250 }
00251 
00252 static const char*
00253 ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00254 {
00255   return ins_imms_scaled (self, value, code, 1);
00256 }
00257 
00258 static const char*
00259 ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00260 {
00261   return ext_imms_scaled (self, code, valuep, 1);
00262 }
00263 
00264 static const char*
00265 ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00266 {
00267   return ins_imms_scaled (self, value, code, 4);
00268 }
00269 
00270 static const char*
00271 ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00272 {
00273   return ext_imms_scaled (self, code, valuep, 4);
00274 }
00275 
00276 static const char*
00277 ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00278 {
00279   return ins_imms_scaled (self, value, code, 16);
00280 }
00281 
00282 static const char*
00283 ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00284 {
00285   return ext_imms_scaled (self, code, valuep, 16);
00286 }
00287 
00288 static const char*
00289 ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00290 {
00291   ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
00292   return ins_immu (self, value ^ mask, code);
00293 }
00294 
00295 static const char*
00296 ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00297 {
00298   const char *result;
00299   ia64_insn mask;
00300 
00301   mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
00302   result = ext_immu (self, code, valuep);
00303   if (!result)
00304     {
00305       mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
00306       *valuep ^= mask;
00307     }
00308   return result;
00309 }
00310 
00311 static const char*
00312 ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00313 {
00314   --value;
00315   if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
00316     return "count out of range";
00317 
00318   *code |= value << self->field[0].shift;
00319   return 0;
00320 }
00321 
00322 static const char*
00323 ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00324 {
00325   *valuep = ((code >> self->field[0].shift)
00326             & ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
00327   return 0;
00328 }
00329 
00330 static const char*
00331 ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00332 {
00333   --value;
00334 
00335   if (value > 2)
00336     return "count must be in range 1..3";
00337 
00338   *code |= value << self->field[0].shift;
00339   return 0;
00340 }
00341 
00342 static const char*
00343 ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00344 {
00345   *valuep = ((code >> self->field[0].shift) & 0x3) + 1;
00346   return 0;
00347 }
00348 
00349 static const char*
00350 ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00351 {
00352   switch (value)
00353     {
00354     case 0:   value = 0; break;
00355     case 7:   value = 1; break;
00356     case 15:  value = 2; break;
00357     case 16:  value = 3; break;
00358     default:  return "count must be 0, 7, 15, or 16";
00359     }
00360   *code |= value << self->field[0].shift;
00361   return 0;
00362 }
00363 
00364 static const char*
00365 ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00366 {
00367   ia64_insn value;
00368 
00369   value = (code >> self->field[0].shift) & 0x3;
00370   switch (value)
00371     {
00372     case 0: value =  0; break;
00373     case 1: value =  7; break;
00374     case 2: value = 15; break;
00375     case 3: value = 16; break;
00376     }
00377   *valuep = value;
00378   return 0;
00379 }
00380 
00381 static const char*
00382 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
00383 {
00384   BFD_HOST_64_BIT val = value;
00385   BFD_HOST_U_64_BIT sign = 0;
00386 
00387   if (val < 0)
00388     {
00389       sign = 0x4;
00390       value = -value;
00391     }
00392   switch (value)
00393     {
00394     case  1:  value = 3; break;
00395     case  4:  value = 2; break;
00396     case  8:  value = 1; break;
00397     case 16:  value = 0; break;
00398     default:  return "count must be +/- 1, 4, 8, or 16";
00399     }
00400   *code |= (sign | value) << self->field[0].shift;
00401   return 0;
00402 }
00403 
00404 static const char*
00405 ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
00406 {
00407   BFD_HOST_64_BIT val;
00408   int negate;
00409 
00410   val = (code >> self->field[0].shift) & 0x7;
00411   negate = val & 0x4;
00412   switch (val & 0x3)
00413     {
00414     case 0: val = 16; break;
00415     case 1: val =  8; break;
00416     case 2: val =  4; break;
00417     case 3: val =  1; break;
00418     }
00419   if (negate)
00420     val = -val;
00421 
00422   *valuep = val;
00423   return 0;
00424 }
00425 
00426 #define CST   IA64_OPND_CLASS_CST
00427 #define REG   IA64_OPND_CLASS_REG
00428 #define IND   IA64_OPND_CLASS_IND
00429 #define ABS   IA64_OPND_CLASS_ABS
00430 #define REL   IA64_OPND_CLASS_REL
00431 
00432 #define SDEC  IA64_OPND_FLAG_DECIMAL_SIGNED
00433 #define UDEC  IA64_OPND_FLAG_DECIMAL_UNSIGNED
00434 
00435 const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
00436   {
00437     /* constants: */
00438     { CST, ins_const, ext_const, "NIL",          {{ 0, 0}}, 0, "<none>" },
00439     { CST, ins_const, ext_const, "ar.csd",       {{ 0, 0}}, 0, "ar.csd" },
00440     { CST, ins_const, ext_const, "ar.ccv",       {{ 0, 0}}, 0, "ar.ccv" },
00441     { CST, ins_const, ext_const, "ar.pfs",       {{ 0, 0}}, 0, "ar.pfs" },
00442     { CST, ins_const, ext_const, "1",            {{ 0, 0}}, 0, "1" },
00443     { CST, ins_const, ext_const, "8",            {{ 0, 0}}, 0, "8" },
00444     { CST, ins_const, ext_const, "16",           {{ 0, 0}}, 0, "16" },
00445     { CST, ins_const, ext_const, "r0",           {{ 0, 0}}, 0, "r0" },
00446     { CST, ins_const, ext_const, "ip",           {{ 0, 0}}, 0, "ip" },
00447     { CST, ins_const, ext_const, "pr",           {{ 0, 0}}, 0, "pr" },
00448     { CST, ins_const, ext_const, "pr.rot",       {{ 0, 0}}, 0, "pr.rot" },
00449     { CST, ins_const, ext_const, "psr",          {{ 0, 0}}, 0, "psr" },
00450     { CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
00451     { CST, ins_const, ext_const, "psr.um",       {{ 0, 0}}, 0, "psr.um" },
00452 
00453     /* register operands: */
00454     { REG, ins_reg,   ext_reg,     "ar", {{ 7, 20}}, 0,        /* AR3 */
00455       "an application register" },
00456     { REG, ins_reg,   ext_reg,      "b", {{ 3,  6}}, 0,        /* B1 */
00457       "a branch register" },
00458     { REG, ins_reg,   ext_reg,      "b", {{ 3, 13}}, 0,        /* B2 */
00459       "a branch register"},
00460     { REG, ins_reg,   ext_reg,     "cr", {{ 7, 20}}, 0,        /* CR */
00461       "a control register"},
00462     { REG, ins_reg,   ext_reg,      "f", {{ 7,  6}}, 0,        /* F1 */
00463       "a floating-point register" },
00464     { REG, ins_reg,   ext_reg,      "f", {{ 7, 13}}, 0,        /* F2 */
00465       "a floating-point register" },
00466     { REG, ins_reg,   ext_reg,      "f", {{ 7, 20}}, 0,        /* F3 */
00467       "a floating-point register" },
00468     { REG, ins_reg,   ext_reg,      "f", {{ 7, 27}}, 0,        /* F4 */
00469       "a floating-point register" },
00470     { REG, ins_reg,   ext_reg,      "p", {{ 6,  6}}, 0,        /* P1 */
00471       "a predicate register" },
00472     { REG, ins_reg,   ext_reg,      "p", {{ 6, 27}}, 0,        /* P2 */
00473       "a predicate register" },
00474     { REG, ins_reg,   ext_reg,      "r", {{ 7,  6}}, 0,        /* R1 */
00475       "a general register" },
00476     { REG, ins_reg,   ext_reg,      "r", {{ 7, 13}}, 0,        /* R2 */
00477       "a general register" },
00478     { REG, ins_reg,   ext_reg,      "r", {{ 7, 20}}, 0,        /* R3 */
00479       "a general register" },
00480     { REG, ins_reg,   ext_reg,      "r", {{ 2, 20}}, 0,        /* R3_2 */
00481       "a general register r0-r3" },
00482 
00483     /* memory operands: */
00484     { IND, ins_reg,   ext_reg,     "",      {{7, 20}}, 0,             /* MR3 */
00485       "a memory address" },
00486 
00487     /* indirect operands: */
00488     { IND, ins_reg,   ext_reg,     "cpuid", {{7, 20}}, 0,             /* CPUID_R3 */
00489       "a cpuid register" },
00490     { IND, ins_reg,   ext_reg,     "dbr",   {{7, 20}}, 0,             /* DBR_R3 */
00491       "a dbr register" },
00492     { IND, ins_reg,   ext_reg,     "dtr",   {{7, 20}}, 0,             /* DTR_R3 */
00493       "a dtr register" },
00494     { IND, ins_reg,   ext_reg,     "itr",   {{7, 20}}, 0,             /* ITR_R3 */
00495       "an itr register" },
00496     { IND, ins_reg,   ext_reg,     "ibr",   {{7, 20}}, 0,             /* IBR_R3 */
00497       "an ibr register" },
00498     { IND, ins_reg,   ext_reg,     "msr",   {{7, 20}}, 0,             /* MSR_R3 */
00499       "an msr register" },
00500     { IND, ins_reg,   ext_reg,     "pkr",   {{7, 20}}, 0,             /* PKR_R3 */
00501       "a pkr register" },
00502     { IND, ins_reg,   ext_reg,     "pmc",   {{7, 20}}, 0,             /* PMC_R3 */
00503       "a pmc register" },
00504     { IND, ins_reg,   ext_reg,     "pmd",   {{7, 20}}, 0,             /* PMD_R3 */
00505       "a pmd register" },
00506     { IND, ins_reg,   ext_reg,     "rr",    {{7, 20}}, 0,             /* RR_R3 */
00507       "an rr register" },
00508 
00509     /* immediate operands: */
00510     { ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC,         /* CCNT5 */
00511       "a 5-bit count (0-31)" },
00512     { ABS, ins_cnt,   ext_cnt,   0, {{ 2, 27 }}, UDEC,         /* CNT2a */
00513       "a 2-bit count (1-4)" },
00514     { ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC,         /* CNT2b */
00515       "a 2-bit count (1-3)" },
00516     { ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC,         /* CNT2c */
00517       "a count (0, 7, 15, or 16)" },
00518     { ABS, ins_immu,  ext_immu,  0, {{ 5, 14}}, UDEC,          /* CNT5 */
00519       "a 5-bit count (0-31)" },
00520     { ABS, ins_immu,  ext_immu,  0, {{ 6, 27}}, UDEC,          /* CNT6 */
00521       "a 6-bit count (0-63)" },
00522     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC,          /* CPOS6a */
00523       "a 6-bit bit pos (0-63)" },
00524     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC,          /* CPOS6b */
00525       "a 6-bit bit pos (0-63)" },
00526     { ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC,          /* CPOS6c */
00527       "a 6-bit bit pos (0-63)" },
00528     { ABS, ins_imms,  ext_imms,  0, {{ 1, 36}}, SDEC,          /* IMM1 */
00529       "a 1-bit integer (-1, 0)" },
00530     { ABS, ins_immu,  ext_immu,  0, {{ 2, 13}}, UDEC,          /* IMMU2 */
00531       "a 2-bit unsigned (0-3)" },
00532     { ABS, ins_immu5b,  ext_immu5b,  0, {{ 5, 14}}, UDEC,      /* IMMU5b */
00533       "a 5-bit unsigned (32 + (0-31))" },
00534     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, 0,             /* IMMU7a */
00535       "a 7-bit unsigned (0-127)" },
00536     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, 0,             /* IMMU7b */
00537       "a 7-bit unsigned (0-127)" },
00538     { ABS, ins_immu,  ext_immu,  0, {{ 7, 13}}, UDEC,          /* SOF */
00539       "a frame size (register count)" },
00540     { ABS, ins_immu,  ext_immu,  0, {{ 7, 20}}, UDEC,          /* SOL */
00541       "a local register count" },
00542     { ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC,          /* SOR */
00543       "a rotating register count (integer multiple of 8)" },
00544     { ABS, ins_imms,  ext_imms,  0,                            /* IMM8 */
00545       {{ 7, 13}, { 1, 36}}, SDEC,
00546       "an 8-bit integer (-128-127)" },
00547     { ABS, ins_immsu4,  ext_imms,  0,                          /* IMM8U4 */
00548       {{ 7, 13}, { 1, 36}}, SDEC,
00549       "an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
00550     { ABS, ins_immsm1,  ext_immsm1,  0,                        /* IMM8M1 */
00551       {{ 7, 13}, { 1, 36}}, SDEC,
00552       "an 8-bit integer (-127-128)" },
00553     { ABS, ins_immsm1u4,  ext_immsm1,  0,               /* IMM8M1U4 */
00554       {{ 7, 13}, { 1, 36}}, SDEC,
00555       "an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
00556     { ABS, ins_immsm1,  ext_immsm1,  0,                        /* IMM8M1U8 */
00557       {{ 7, 13}, { 1, 36}}, SDEC,
00558       "an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
00559     { ABS, ins_immu,  ext_immu,  0, {{ 2, 33}, { 7, 20}}, 0,   /* IMMU9 */
00560       "a 9-bit unsigned (0-511)" },
00561     { ABS, ins_imms,  ext_imms,  0,                            /* IMM9a */
00562       {{ 7,  6}, { 1, 27}, { 1, 36}}, SDEC,
00563       "a 9-bit integer (-256-255)" },
00564     { ABS, ins_imms,  ext_imms, 0,                      /* IMM9b */
00565       {{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
00566       "a 9-bit integer (-256-255)" },
00567     { ABS, ins_imms,  ext_imms, 0,                      /* IMM14 */
00568       {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
00569       "a 14-bit integer (-8192-8191)" },
00570     { ABS, ins_imms1, ext_imms1, 0,                            /* IMM17 */
00571       {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,
00572       "a 17-bit integer (-65536-65535)" },
00573     { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,   /* IMMU21 */
00574       "a 21-bit unsigned" },
00575     { ABS, ins_imms,  ext_imms,  0,                            /* IMM22 */
00576       {{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
00577       "a 22-bit signed integer" },
00578     { ABS, ins_immu,  ext_immu,  0,                            /* IMMU24 */
00579       {{21,  6}, { 2, 31}, { 1, 36}}, 0,
00580       "a 24-bit unsigned" },
00581     { ABS, ins_imms16,ext_imms16,0, {{27,  6}, { 1, 36}}, 0,   /* IMM44 */
00582       "a 44-bit unsigned (least 16 bits ignored/zeroes)" },
00583     { ABS, ins_rsvd,  ext_rsvd,    0, {{0,  0}}, 0,            /* IMMU62 */
00584       "a 62-bit unsigned" },
00585     { ABS, ins_rsvd,  ext_rsvd,    0, {{0,  0}}, 0,            /* IMMU64 */
00586       "a 64-bit unsigned" },
00587     { ABS, ins_inc3,  ext_inc3,  0, {{ 3, 13}}, SDEC,          /* INC3 */
00588       "an increment (+/- 1, 4, 8, or 16)" },
00589     { ABS, ins_cnt,   ext_cnt,   0, {{ 4, 27}}, UDEC,          /* LEN4 */
00590       "a 4-bit length (1-16)" },
00591     { ABS, ins_cnt,   ext_cnt,   0, {{ 6, 27}}, UDEC,          /* LEN6 */
00592       "a 6-bit length (1-64)" },
00593     { ABS, ins_immu,  ext_immu,  0, {{ 4, 20}},  0,            /* MBTYPE4 */
00594       "a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
00595     { ABS, ins_immu,  ext_immu,  0, {{ 8, 20}},  0,            /* MBTYPE8 */
00596       "an 8-bit mix type" },
00597     { ABS, ins_immu,  ext_immu,  0, {{ 6, 14}}, UDEC,          /* POS6 */
00598       "a 6-bit bit pos (0-63)" },
00599     { REL, ins_imms4, ext_imms4, 0, {{ 7,  6}, { 2, 33}}, 0,   /* TAG13 */
00600       "a branch tag" },
00601     { REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0,             /* TAG13b */
00602       "a branch tag" },
00603     { REL, ins_imms4, ext_imms4, 0, {{20,  6}, { 1, 36}}, 0,   /* TGT25 */
00604       "a branch target" },
00605     { REL, ins_imms4, ext_imms4, 0,                            /* TGT25b */
00606       {{ 7,  6}, {13, 20}, { 1, 36}}, 0,
00607       "a branch target" },
00608     { REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0,   /* TGT25c */
00609       "a branch target" },
00610     { REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0,                  /* TGT64  */
00611       "a branch target" },
00612 
00613     { ABS, ins_const, ext_const, 0, {{0, 0}}, 0,        /* LDXMOV */
00614       "ldxmov target" },
00615   };