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cell-binutils  2.17cvs20070401
coff-sh.c
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00001 /* BFD back-end for Renesas Super-H COFF binaries.
00002    Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
00003    2003, 2004, 2005, 2007 Free Software Foundation, Inc.
00004    Contributed by Cygnus Support.
00005    Written by Steve Chamberlain, <sac@cygnus.com>.
00006    Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
00007 
00008    This file is part of BFD, the Binary File Descriptor library.
00009 
00010    This program is free software; you can redistribute it and/or modify
00011    it under the terms of the GNU General Public License as published by
00012    the Free Software Foundation; either version 2 of the License, or
00013    (at your option) any later version.
00014 
00015    This program is distributed in the hope that it will be useful,
00016    but WITHOUT ANY WARRANTY; without even the implied warranty of
00017    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00018    GNU General Public License for more details.
00019 
00020    You should have received a copy of the GNU General Public License
00021    along with this program; if not, write to the Free Software
00022    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00023 
00024 #include "bfd.h"
00025 #include "sysdep.h"
00026 #include "libiberty.h"
00027 #include "libbfd.h"
00028 #include "bfdlink.h"
00029 #include "coff/sh.h"
00030 #include "coff/internal.h"
00031 
00032 #ifdef COFF_WITH_PE
00033 #include "coff/pe.h"
00034 
00035 #ifndef COFF_IMAGE_WITH_PE
00036 static bfd_boolean sh_align_load_span
00037   PARAMS ((bfd *, asection *, bfd_byte *,
00038           bfd_boolean (*) (bfd *, asection *, PTR, bfd_byte *, bfd_vma),
00039           PTR, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bfd_boolean *));
00040 
00041 #define _bfd_sh_align_load_span sh_align_load_span
00042 #endif
00043 #endif
00044 
00045 #include "libcoff.h"
00046 
00047 /* Internal functions.  */
00048 static bfd_reloc_status_type sh_reloc
00049   PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
00050 static long get_symbol_value PARAMS ((asymbol *));
00051 static bfd_boolean sh_relax_section
00052   PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *));
00053 static bfd_boolean sh_relax_delete_bytes
00054   PARAMS ((bfd *, asection *, bfd_vma, int));
00055 #ifndef COFF_IMAGE_WITH_PE
00056 static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
00057 #endif
00058 static bfd_boolean sh_align_loads
00059   PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *,
00060           bfd_boolean *));
00061 static bfd_boolean sh_swap_insns
00062   PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
00063 static bfd_boolean sh_relocate_section
00064   PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
00065           struct internal_reloc *, struct internal_syment *, asection **));
00066 static bfd_byte *sh_coff_get_relocated_section_contents
00067   PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
00068           bfd_byte *, bfd_boolean, asymbol **));
00069 static reloc_howto_type * sh_coff_reloc_type_lookup PARAMS ((bfd *, bfd_reloc_code_real_type));
00070 
00071 #ifdef COFF_WITH_PE
00072 /* Can't build import tables with 2**4 alignment.  */
00073 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER     2
00074 #else
00075 /* Default section alignment to 2**4.  */
00076 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER     4
00077 #endif
00078 
00079 #ifdef COFF_IMAGE_WITH_PE
00080 /* Align PE executables.  */
00081 #define COFF_PAGE_SIZE 0x1000
00082 #endif
00083 
00084 /* Generate long file names.  */
00085 #define COFF_LONG_FILENAMES
00086 
00087 #ifdef COFF_WITH_PE
00088 static bfd_boolean in_reloc_p PARAMS ((bfd *, reloc_howto_type *));
00089 /* Return TRUE if this relocation should
00090    appear in the output .reloc section.  */
00091 static bfd_boolean in_reloc_p (abfd, howto)
00092      bfd * abfd ATTRIBUTE_UNUSED;
00093      reloc_howto_type * howto;
00094 {
00095   return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
00096 }
00097 #endif
00098 
00099 /* The supported relocations.  There are a lot of relocations defined
00100    in coff/internal.h which we do not expect to ever see.  */
00101 static reloc_howto_type sh_coff_howtos[] =
00102 {
00103   EMPTY_HOWTO (0),
00104   EMPTY_HOWTO (1),
00105 #ifdef COFF_WITH_PE
00106   /* Windows CE */
00107   HOWTO (R_SH_IMM32CE,             /* type */
00108         0,                  /* rightshift */
00109         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00110         32,                 /* bitsize */
00111         FALSE,                     /* pc_relative */
00112         0,                  /* bitpos */
00113         complain_overflow_bitfield, /* complain_on_overflow */
00114         sh_reloc,           /* special_function */
00115         "r_imm32ce",        /* name */
00116         TRUE,               /* partial_inplace */
00117         0xffffffff,         /* src_mask */
00118         0xffffffff,         /* dst_mask */
00119         FALSE),             /* pcrel_offset */
00120 #else
00121   EMPTY_HOWTO (2),
00122 #endif
00123   EMPTY_HOWTO (3), /* R_SH_PCREL8 */
00124   EMPTY_HOWTO (4), /* R_SH_PCREL16 */
00125   EMPTY_HOWTO (5), /* R_SH_HIGH8 */
00126   EMPTY_HOWTO (6), /* R_SH_IMM24 */
00127   EMPTY_HOWTO (7), /* R_SH_LOW16 */
00128   EMPTY_HOWTO (8),
00129   EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
00130 
00131   HOWTO (R_SH_PCDISP8BY2,   /* type */
00132         1,                  /* rightshift */
00133         1,                  /* size (0 = byte, 1 = short, 2 = long) */
00134         8,                  /* bitsize */
00135         TRUE,               /* pc_relative */
00136         0,                  /* bitpos */
00137         complain_overflow_signed, /* complain_on_overflow */
00138         sh_reloc,           /* special_function */
00139         "r_pcdisp8by2",     /* name */
00140         TRUE,               /* partial_inplace */
00141         0xff,               /* src_mask */
00142         0xff,               /* dst_mask */
00143         TRUE),                     /* pcrel_offset */
00144 
00145   EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
00146 
00147   HOWTO (R_SH_PCDISP,              /* type */
00148         1,                  /* rightshift */
00149         1,                  /* size (0 = byte, 1 = short, 2 = long) */
00150         12,                 /* bitsize */
00151         TRUE,               /* pc_relative */
00152         0,                  /* bitpos */
00153         complain_overflow_signed, /* complain_on_overflow */
00154         sh_reloc,           /* special_function */
00155         "r_pcdisp12by2",    /* name */
00156         TRUE,               /* partial_inplace */
00157         0xfff,                     /* src_mask */
00158         0xfff,                     /* dst_mask */
00159         TRUE),                     /* pcrel_offset */
00160 
00161   EMPTY_HOWTO (13),
00162 
00163   HOWTO (R_SH_IMM32,        /* type */
00164         0,                  /* rightshift */
00165         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00166         32,                 /* bitsize */
00167         FALSE,                     /* pc_relative */
00168         0,                  /* bitpos */
00169         complain_overflow_bitfield, /* complain_on_overflow */
00170         sh_reloc,           /* special_function */
00171         "r_imm32",          /* name */
00172         TRUE,               /* partial_inplace */
00173         0xffffffff,         /* src_mask */
00174         0xffffffff,         /* dst_mask */
00175         FALSE),             /* pcrel_offset */
00176 
00177   EMPTY_HOWTO (15),
00178 #ifdef COFF_WITH_PE
00179   HOWTO (R_SH_IMAGEBASE,        /* type */
00180         0,                    /* rightshift */
00181         2,                    /* size (0 = byte, 1 = short, 2 = long) */
00182         32,                   /* bitsize */
00183         FALSE,                       /* pc_relative */
00184         0,                    /* bitpos */
00185         complain_overflow_bitfield, /* complain_on_overflow */
00186         sh_reloc,           /* special_function */
00187         "rva32",             /* name */
00188         TRUE,                 /* partial_inplace */
00189         0xffffffff,            /* src_mask */
00190         0xffffffff,            /* dst_mask */
00191         FALSE),                /* pcrel_offset */
00192 #else
00193   EMPTY_HOWTO (16), /* R_SH_IMM8 */
00194 #endif
00195   EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
00196   EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
00197   EMPTY_HOWTO (19), /* R_SH_IMM4 */
00198   EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
00199   EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
00200 
00201   HOWTO (R_SH_PCRELIMM8BY2, /* type */
00202         1,                  /* rightshift */
00203         1,                  /* size (0 = byte, 1 = short, 2 = long) */
00204         8,                  /* bitsize */
00205         TRUE,               /* pc_relative */
00206         0,                  /* bitpos */
00207         complain_overflow_unsigned, /* complain_on_overflow */
00208         sh_reloc,           /* special_function */
00209         "r_pcrelimm8by2",   /* name */
00210         TRUE,               /* partial_inplace */
00211         0xff,               /* src_mask */
00212         0xff,               /* dst_mask */
00213         TRUE),                     /* pcrel_offset */
00214 
00215   HOWTO (R_SH_PCRELIMM8BY4, /* type */
00216         2,                  /* rightshift */
00217         1,                  /* size (0 = byte, 1 = short, 2 = long) */
00218         8,                  /* bitsize */
00219         TRUE,               /* pc_relative */
00220         0,                  /* bitpos */
00221         complain_overflow_unsigned, /* complain_on_overflow */
00222         sh_reloc,           /* special_function */
00223         "r_pcrelimm8by4",   /* name */
00224         TRUE,               /* partial_inplace */
00225         0xff,               /* src_mask */
00226         0xff,               /* dst_mask */
00227         TRUE),                     /* pcrel_offset */
00228 
00229   HOWTO (R_SH_IMM16,        /* type */
00230         0,                  /* rightshift */
00231         1,                  /* size (0 = byte, 1 = short, 2 = long) */
00232         16,                 /* bitsize */
00233         FALSE,                     /* pc_relative */
00234         0,                  /* bitpos */
00235         complain_overflow_bitfield, /* complain_on_overflow */
00236         sh_reloc,           /* special_function */
00237         "r_imm16",          /* name */
00238         TRUE,               /* partial_inplace */
00239         0xffff,             /* src_mask */
00240         0xffff,             /* dst_mask */
00241         FALSE),             /* pcrel_offset */
00242 
00243   HOWTO (R_SH_SWITCH16,            /* type */
00244         0,                  /* rightshift */
00245         1,                  /* size (0 = byte, 1 = short, 2 = long) */
00246         16,                 /* bitsize */
00247         FALSE,                     /* pc_relative */
00248         0,                  /* bitpos */
00249         complain_overflow_bitfield, /* complain_on_overflow */
00250         sh_reloc,           /* special_function */
00251         "r_switch16",              /* name */
00252         TRUE,               /* partial_inplace */
00253         0xffff,             /* src_mask */
00254         0xffff,             /* dst_mask */
00255         FALSE),             /* pcrel_offset */
00256 
00257   HOWTO (R_SH_SWITCH32,            /* type */
00258         0,                  /* rightshift */
00259         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00260         32,                 /* bitsize */
00261         FALSE,                     /* pc_relative */
00262         0,                  /* bitpos */
00263         complain_overflow_bitfield, /* complain_on_overflow */
00264         sh_reloc,           /* special_function */
00265         "r_switch32",              /* name */
00266         TRUE,               /* partial_inplace */
00267         0xffffffff,         /* src_mask */
00268         0xffffffff,         /* dst_mask */
00269         FALSE),             /* pcrel_offset */
00270 
00271   HOWTO (R_SH_USES,         /* type */
00272         0,                  /* rightshift */
00273         1,                  /* size (0 = byte, 1 = short, 2 = long) */
00274         16,                 /* bitsize */
00275         FALSE,                     /* pc_relative */
00276         0,                  /* bitpos */
00277         complain_overflow_bitfield, /* complain_on_overflow */
00278         sh_reloc,           /* special_function */
00279         "r_uses",           /* name */
00280         TRUE,               /* partial_inplace */
00281         0xffff,             /* src_mask */
00282         0xffff,             /* dst_mask */
00283         FALSE),             /* pcrel_offset */
00284 
00285   HOWTO (R_SH_COUNT,        /* type */
00286         0,                  /* rightshift */
00287         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00288         32,                 /* bitsize */
00289         FALSE,                     /* pc_relative */
00290         0,                  /* bitpos */
00291         complain_overflow_bitfield, /* complain_on_overflow */
00292         sh_reloc,           /* special_function */
00293         "r_count",          /* name */
00294         TRUE,               /* partial_inplace */
00295         0xffffffff,         /* src_mask */
00296         0xffffffff,         /* dst_mask */
00297         FALSE),             /* pcrel_offset */
00298 
00299   HOWTO (R_SH_ALIGN,        /* type */
00300         0,                  /* rightshift */
00301         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00302         32,                 /* bitsize */
00303         FALSE,                     /* pc_relative */
00304         0,                  /* bitpos */
00305         complain_overflow_bitfield, /* complain_on_overflow */
00306         sh_reloc,           /* special_function */
00307         "r_align",          /* name */
00308         TRUE,               /* partial_inplace */
00309         0xffffffff,         /* src_mask */
00310         0xffffffff,         /* dst_mask */
00311         FALSE),             /* pcrel_offset */
00312 
00313   HOWTO (R_SH_CODE,         /* type */
00314         0,                  /* rightshift */
00315         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00316         32,                 /* bitsize */
00317         FALSE,                     /* pc_relative */
00318         0,                  /* bitpos */
00319         complain_overflow_bitfield, /* complain_on_overflow */
00320         sh_reloc,           /* special_function */
00321         "r_code",           /* name */
00322         TRUE,               /* partial_inplace */
00323         0xffffffff,         /* src_mask */
00324         0xffffffff,         /* dst_mask */
00325         FALSE),             /* pcrel_offset */
00326 
00327   HOWTO (R_SH_DATA,         /* type */
00328         0,                  /* rightshift */
00329         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00330         32,                 /* bitsize */
00331         FALSE,                     /* pc_relative */
00332         0,                  /* bitpos */
00333         complain_overflow_bitfield, /* complain_on_overflow */
00334         sh_reloc,           /* special_function */
00335         "r_data",           /* name */
00336         TRUE,               /* partial_inplace */
00337         0xffffffff,         /* src_mask */
00338         0xffffffff,         /* dst_mask */
00339         FALSE),             /* pcrel_offset */
00340 
00341   HOWTO (R_SH_LABEL,        /* type */
00342         0,                  /* rightshift */
00343         2,                  /* size (0 = byte, 1 = short, 2 = long) */
00344         32,                 /* bitsize */
00345         FALSE,                     /* pc_relative */
00346         0,                  /* bitpos */
00347         complain_overflow_bitfield, /* complain_on_overflow */
00348         sh_reloc,           /* special_function */
00349         "r_label",          /* name */
00350         TRUE,               /* partial_inplace */
00351         0xffffffff,         /* src_mask */
00352         0xffffffff,         /* dst_mask */
00353         FALSE),             /* pcrel_offset */
00354 
00355   HOWTO (R_SH_SWITCH8,             /* type */
00356         0,                  /* rightshift */
00357         0,                  /* size (0 = byte, 1 = short, 2 = long) */
00358         8,                  /* bitsize */
00359         FALSE,                     /* pc_relative */
00360         0,                  /* bitpos */
00361         complain_overflow_bitfield, /* complain_on_overflow */
00362         sh_reloc,           /* special_function */
00363         "r_switch8",        /* name */
00364         TRUE,               /* partial_inplace */
00365         0xff,               /* src_mask */
00366         0xff,               /* dst_mask */
00367         FALSE)                     /* pcrel_offset */
00368 };
00369 
00370 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
00371 
00372 /* Check for a bad magic number.  */
00373 #define BADMAG(x) SHBADMAG(x)
00374 
00375 /* Customize coffcode.h (this is not currently used).  */
00376 #define SH 1
00377 
00378 /* FIXME: This should not be set here.  */
00379 #define __A_MAGIC_SET__
00380 
00381 #ifndef COFF_WITH_PE
00382 /* Swap the r_offset field in and out.  */
00383 #define SWAP_IN_RELOC_OFFSET  H_GET_32
00384 #define SWAP_OUT_RELOC_OFFSET H_PUT_32
00385 
00386 /* Swap out extra information in the reloc structure.  */
00387 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst)     \
00388   do                                      \
00389     {                                     \
00390       dst->r_stuff[0] = 'S';                     \
00391       dst->r_stuff[1] = 'C';                     \
00392     }                                     \
00393   while (0)
00394 #endif
00395 
00396 /* Get the value of a symbol, when performing a relocation.  */
00397 
00398 static long
00399 get_symbol_value (symbol)
00400      asymbol *symbol;
00401 {
00402   bfd_vma relocation;
00403 
00404   if (bfd_is_com_section (symbol->section))
00405     relocation = 0;
00406   else
00407     relocation = (symbol->value +
00408                 symbol->section->output_section->vma +
00409                 symbol->section->output_offset);
00410 
00411   return relocation;
00412 }
00413 
00414 #ifdef COFF_WITH_PE
00415 /* Convert an rtype to howto for the COFF backend linker.
00416    Copied from coff-i386.  */
00417 #define coff_rtype_to_howto coff_sh_rtype_to_howto
00418 static reloc_howto_type * coff_sh_rtype_to_howto PARAMS ((bfd *, asection *, struct internal_reloc *, struct coff_link_hash_entry *, struct internal_syment *, bfd_vma *));
00419 
00420 static reloc_howto_type *
00421 coff_sh_rtype_to_howto (abfd, sec, rel, h, sym, addendp)
00422      bfd * abfd ATTRIBUTE_UNUSED;
00423      asection * sec;
00424      struct internal_reloc * rel;
00425      struct coff_link_hash_entry * h;
00426      struct internal_syment * sym;
00427      bfd_vma * addendp;
00428 {
00429   reloc_howto_type * howto;
00430 
00431   howto = sh_coff_howtos + rel->r_type;
00432 
00433   *addendp = 0;
00434 
00435   if (howto->pc_relative)
00436     *addendp += sec->vma;
00437 
00438   if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
00439     {
00440       /* This is a common symbol.  The section contents include the
00441         size (sym->n_value) as an addend.  The relocate_section
00442         function will be adding in the final value of the symbol.  We
00443         need to subtract out the current size in order to get the
00444         correct result.  */
00445       BFD_ASSERT (h != NULL);
00446     }
00447 
00448   if (howto->pc_relative)
00449     {
00450       *addendp -= 4;
00451 
00452       /* If the symbol is defined, then the generic code is going to
00453          add back the symbol value in order to cancel out an
00454          adjustment it made to the addend.  However, we set the addend
00455          to 0 at the start of this function.  We need to adjust here,
00456          to avoid the adjustment the generic code will make.  FIXME:
00457          This is getting a bit hackish.  */
00458       if (sym != NULL && sym->n_scnum != 0)
00459        *addendp -= sym->n_value;
00460     }
00461 
00462   if (rel->r_type == R_SH_IMAGEBASE)
00463     *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
00464 
00465   return howto;
00466 }
00467 
00468 #endif /* COFF_WITH_PE */
00469 
00470 /* This structure is used to map BFD reloc codes to SH PE relocs.  */
00471 struct shcoff_reloc_map
00472 {
00473   bfd_reloc_code_real_type bfd_reloc_val;
00474   unsigned char shcoff_reloc_val;
00475 };
00476 
00477 #ifdef COFF_WITH_PE
00478 /* An array mapping BFD reloc codes to SH PE relocs.  */
00479 static const struct shcoff_reloc_map sh_reloc_map[] =
00480 {
00481   { BFD_RELOC_32, R_SH_IMM32CE },
00482   { BFD_RELOC_RVA, R_SH_IMAGEBASE },
00483   { BFD_RELOC_CTOR, R_SH_IMM32CE },
00484 };
00485 #else
00486 /* An array mapping BFD reloc codes to SH PE relocs.  */
00487 static const struct shcoff_reloc_map sh_reloc_map[] =
00488 {
00489   { BFD_RELOC_32, R_SH_IMM32 },
00490   { BFD_RELOC_CTOR, R_SH_IMM32 },
00491 };
00492 #endif
00493 
00494 /* Given a BFD reloc code, return the howto structure for the
00495    corresponding SH PE reloc.  */
00496 #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
00497 #define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
00498 
00499 static reloc_howto_type *
00500 sh_coff_reloc_type_lookup (abfd, code)
00501      bfd * abfd ATTRIBUTE_UNUSED;
00502      bfd_reloc_code_real_type code;
00503 {
00504   unsigned int i;
00505 
00506   for (i = ARRAY_SIZE (sh_reloc_map); i--;)
00507     if (sh_reloc_map[i].bfd_reloc_val == code)
00508       return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
00509 
00510   fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
00511   return NULL;
00512 }
00513 
00514 static reloc_howto_type *
00515 sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
00516                         const char *r_name)
00517 {
00518   unsigned int i;
00519 
00520   for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
00521     if (sh_coff_howtos[i].name != NULL
00522        && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
00523       return &sh_coff_howtos[i];
00524 
00525   return NULL;
00526 }
00527 
00528 /* This macro is used in coffcode.h to get the howto corresponding to
00529    an internal reloc.  */
00530 
00531 #define RTYPE2HOWTO(relent, internal)            \
00532   ((relent)->howto =                      \
00533    ((internal)->r_type < SH_COFF_HOWTO_COUNT     \
00534     ? &sh_coff_howtos[(internal)->r_type] \
00535     : (reloc_howto_type *) NULL))
00536 
00537 /* This is the same as the macro in coffcode.h, except that it copies
00538    r_offset into reloc_entry->addend for some relocs.  */
00539 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr)                \
00540   {                                                             \
00541     coff_symbol_type *coffsym = (coff_symbol_type *) NULL;      \
00542     if (ptr && bfd_asymbol_bfd (ptr) != abfd)                   \
00543       coffsym = (obj_symbols (abfd)                             \
00544                  + (cache_ptr->sym_ptr_ptr - symbols));         \
00545     else if (ptr)                                               \
00546       coffsym = coff_symbol_from (abfd, ptr);                   \
00547     if (coffsym != (coff_symbol_type *) NULL                    \
00548         && coffsym->native->u.syment.n_scnum == 0)              \
00549       cache_ptr->addend = 0;                                    \
00550     else if (ptr && bfd_asymbol_bfd (ptr) == abfd               \
00551              && ptr->section != (asection *) NULL)              \
00552       cache_ptr->addend = - (ptr->section->vma + ptr->value);   \
00553     else                                                        \
00554       cache_ptr->addend = 0;                                    \
00555     if ((reloc).r_type == R_SH_SWITCH8                         \
00556        || (reloc).r_type == R_SH_SWITCH16               \
00557        || (reloc).r_type == R_SH_SWITCH32               \
00558        || (reloc).r_type == R_SH_USES                          \
00559        || (reloc).r_type == R_SH_COUNT                         \
00560        || (reloc).r_type == R_SH_ALIGN)                 \
00561       cache_ptr->addend = (reloc).r_offset;                    \
00562   }
00563 
00564 /* This is the howto function for the SH relocations.  */
00565 
00566 static bfd_reloc_status_type
00567 sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
00568          error_message)
00569      bfd *abfd;
00570      arelent *reloc_entry;
00571      asymbol *symbol_in;
00572      PTR data;
00573      asection *input_section;
00574      bfd *output_bfd;
00575      char **error_message ATTRIBUTE_UNUSED;
00576 {
00577   unsigned long insn;
00578   bfd_vma sym_value;
00579   unsigned short r_type;
00580   bfd_vma addr = reloc_entry->address;
00581   bfd_byte *hit_data = addr + (bfd_byte *) data;
00582 
00583   r_type = reloc_entry->howto->type;
00584 
00585   if (output_bfd != NULL)
00586     {
00587       /* Partial linking--do nothing.  */
00588       reloc_entry->address += input_section->output_offset;
00589       return bfd_reloc_ok;
00590     }
00591 
00592   /* Almost all relocs have to do with relaxing.  If any work must be
00593      done for them, it has been done in sh_relax_section.  */
00594   if (r_type != R_SH_IMM32
00595 #ifdef COFF_WITH_PE
00596       && r_type != R_SH_IMM32CE
00597       && r_type != R_SH_IMAGEBASE
00598 #endif
00599       && (r_type != R_SH_PCDISP
00600          || (symbol_in->flags & BSF_LOCAL) != 0))
00601     return bfd_reloc_ok;
00602 
00603   if (symbol_in != NULL
00604       && bfd_is_und_section (symbol_in->section))
00605     return bfd_reloc_undefined;
00606 
00607   sym_value = get_symbol_value (symbol_in);
00608 
00609   switch (r_type)
00610     {
00611     case R_SH_IMM32:
00612 #ifdef COFF_WITH_PE
00613     case R_SH_IMM32CE:
00614 #endif
00615       insn = bfd_get_32 (abfd, hit_data);
00616       insn += sym_value + reloc_entry->addend;
00617       bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
00618       break;
00619 #ifdef COFF_WITH_PE
00620     case R_SH_IMAGEBASE:
00621       insn = bfd_get_32 (abfd, hit_data);
00622       insn += sym_value + reloc_entry->addend;
00623       insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
00624       bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
00625       break;
00626 #endif
00627     case R_SH_PCDISP:
00628       insn = bfd_get_16 (abfd, hit_data);
00629       sym_value += reloc_entry->addend;
00630       sym_value -= (input_section->output_section->vma
00631                   + input_section->output_offset
00632                   + addr
00633                   + 4);
00634       sym_value += (insn & 0xfff) << 1;
00635       if (insn & 0x800)
00636        sym_value -= 0x1000;
00637       insn = (insn & 0xf000) | (sym_value & 0xfff);
00638       bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
00639       if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
00640        return bfd_reloc_overflow;
00641       break;
00642     default:
00643       abort ();
00644       break;
00645     }
00646 
00647   return bfd_reloc_ok;
00648 }
00649 
00650 #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
00651 
00652 /* We can do relaxing.  */
00653 #define coff_bfd_relax_section sh_relax_section
00654 
00655 /* We use the special COFF backend linker.  */
00656 #define coff_relocate_section sh_relocate_section
00657 
00658 /* When relaxing, we need to use special code to get the relocated
00659    section contents.  */
00660 #define coff_bfd_get_relocated_section_contents \
00661   sh_coff_get_relocated_section_contents
00662 
00663 #include "coffcode.h"
00664 
00665 /* This function handles relaxing on the SH.
00666 
00667    Function calls on the SH look like this:
00668 
00669        movl  L1,r0
00670        ...
00671        jsr   @r0
00672        ...
00673      L1:
00674        .long function
00675 
00676    The compiler and assembler will cooperate to create R_SH_USES
00677    relocs on the jsr instructions.  The r_offset field of the
00678    R_SH_USES reloc is the PC relative offset to the instruction which
00679    loads the register (the r_offset field is computed as though it
00680    were a jump instruction, so the offset value is actually from four
00681    bytes past the instruction).  The linker can use this reloc to
00682    determine just which function is being called, and thus decide
00683    whether it is possible to replace the jsr with a bsr.
00684 
00685    If multiple function calls are all based on a single register load
00686    (i.e., the same function is called multiple times), the compiler
00687    guarantees that each function call will have an R_SH_USES reloc.
00688    Therefore, if the linker is able to convert each R_SH_USES reloc
00689    which refers to that address, it can safely eliminate the register
00690    load.
00691 
00692    When the assembler creates an R_SH_USES reloc, it examines it to
00693    determine which address is being loaded (L1 in the above example).
00694    It then counts the number of references to that address, and
00695    creates an R_SH_COUNT reloc at that address.  The r_offset field of
00696    the R_SH_COUNT reloc will be the number of references.  If the
00697    linker is able to eliminate a register load, it can use the
00698    R_SH_COUNT reloc to see whether it can also eliminate the function
00699    address.
00700 
00701    SH relaxing also handles another, unrelated, matter.  On the SH, if
00702    a load or store instruction is not aligned on a four byte boundary,
00703    the memory cycle interferes with the 32 bit instruction fetch,
00704    causing a one cycle bubble in the pipeline.  Therefore, we try to
00705    align load and store instructions on four byte boundaries if we
00706    can, by swapping them with one of the adjacent instructions.  */
00707 
00708 static bfd_boolean
00709 sh_relax_section (abfd, sec, link_info, again)
00710      bfd *abfd;
00711      asection *sec;
00712      struct bfd_link_info *link_info;
00713      bfd_boolean *again;
00714 {
00715   struct internal_reloc *internal_relocs;
00716   bfd_boolean have_code;
00717   struct internal_reloc *irel, *irelend;
00718   bfd_byte *contents = NULL;
00719 
00720   *again = FALSE;
00721 
00722   if (link_info->relocatable
00723       || (sec->flags & SEC_RELOC) == 0
00724       || sec->reloc_count == 0)
00725     return TRUE;
00726 
00727   if (coff_section_data (abfd, sec) == NULL)
00728     {
00729       bfd_size_type amt = sizeof (struct coff_section_tdata);
00730       sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
00731       if (sec->used_by_bfd == NULL)
00732        return FALSE;
00733     }
00734 
00735   internal_relocs = (_bfd_coff_read_internal_relocs
00736                    (abfd, sec, link_info->keep_memory,
00737                     (bfd_byte *) NULL, FALSE,
00738                     (struct internal_reloc *) NULL));
00739   if (internal_relocs == NULL)
00740     goto error_return;
00741 
00742   have_code = FALSE;
00743 
00744   irelend = internal_relocs + sec->reloc_count;
00745   for (irel = internal_relocs; irel < irelend; irel++)
00746     {
00747       bfd_vma laddr, paddr, symval;
00748       unsigned short insn;
00749       struct internal_reloc *irelfn, *irelscan, *irelcount;
00750       struct internal_syment sym;
00751       bfd_signed_vma foff;
00752 
00753       if (irel->r_type == R_SH_CODE)
00754        have_code = TRUE;
00755 
00756       if (irel->r_type != R_SH_USES)
00757        continue;
00758 
00759       /* Get the section contents.  */
00760       if (contents == NULL)
00761        {
00762          if (coff_section_data (abfd, sec)->contents != NULL)
00763            contents = coff_section_data (abfd, sec)->contents;
00764          else
00765            {
00766              if (!bfd_malloc_and_get_section (abfd, sec, &contents))
00767               goto error_return;
00768            }
00769        }
00770 
00771       /* The r_offset field of the R_SH_USES reloc will point us to
00772          the register load.  The 4 is because the r_offset field is
00773          computed as though it were a jump offset, which are based
00774          from 4 bytes after the jump instruction.  */
00775       laddr = irel->r_vaddr - sec->vma + 4;
00776       /* Careful to sign extend the 32-bit offset.  */
00777       laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
00778       if (laddr >= sec->size)
00779        {
00780          (*_bfd_error_handler) ("%B: 0x%lx: warning: bad R_SH_USES offset",
00781                              abfd, (unsigned long) irel->r_vaddr);
00782          continue;
00783        }
00784       insn = bfd_get_16 (abfd, contents + laddr);
00785 
00786       /* If the instruction is not mov.l NN,rN, we don't know what to do.  */
00787       if ((insn & 0xf000) != 0xd000)
00788        {
00789          ((*_bfd_error_handler)
00790           ("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
00791            abfd, (unsigned long) irel->r_vaddr, insn));
00792          continue;
00793        }
00794 
00795       /* Get the address from which the register is being loaded.  The
00796         displacement in the mov.l instruction is quadrupled.  It is a
00797         displacement from four bytes after the movl instruction, but,
00798         before adding in the PC address, two least significant bits
00799         of the PC are cleared.  We assume that the section is aligned
00800         on a four byte boundary.  */
00801       paddr = insn & 0xff;
00802       paddr *= 4;
00803       paddr += (laddr + 4) &~ (bfd_vma) 3;
00804       if (paddr >= sec->size)
00805        {
00806          ((*_bfd_error_handler)
00807           ("%B: 0x%lx: warning: bad R_SH_USES load offset",
00808            abfd, (unsigned long) irel->r_vaddr));
00809          continue;
00810        }
00811 
00812       /* Get the reloc for the address from which the register is
00813          being loaded.  This reloc will tell us which function is
00814          actually being called.  */
00815       paddr += sec->vma;
00816       for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
00817        if (irelfn->r_vaddr == paddr
00818 #ifdef COFF_WITH_PE
00819            && (irelfn->r_type == R_SH_IMM32
00820               || irelfn->r_type == R_SH_IMM32CE
00821               || irelfn->r_type == R_SH_IMAGEBASE)
00822 
00823 #else
00824            && irelfn->r_type == R_SH_IMM32
00825 #endif
00826            )
00827          break;
00828       if (irelfn >= irelend)
00829        {
00830          ((*_bfd_error_handler)
00831           ("%B: 0x%lx: warning: could not find expected reloc",
00832            abfd, (unsigned long) paddr));
00833          continue;
00834        }
00835 
00836       /* Get the value of the symbol referred to by the reloc.  */
00837       if (! _bfd_coff_get_external_symbols (abfd))
00838        goto error_return;
00839       bfd_coff_swap_sym_in (abfd,
00840                          ((bfd_byte *) obj_coff_external_syms (abfd)
00841                           + (irelfn->r_symndx
00842                             * bfd_coff_symesz (abfd))),
00843                          &sym);
00844       if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
00845        {
00846          ((*_bfd_error_handler)
00847           ("%B: 0x%lx: warning: symbol in unexpected section",
00848            abfd, (unsigned long) paddr));
00849          continue;
00850        }
00851 
00852       if (sym.n_sclass != C_EXT)
00853        {
00854          symval = (sym.n_value
00855                   - sec->vma
00856                   + sec->output_section->vma
00857                   + sec->output_offset);
00858        }
00859       else
00860        {
00861          struct coff_link_hash_entry *h;
00862 
00863          h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
00864          BFD_ASSERT (h != NULL);
00865          if (h->root.type != bfd_link_hash_defined
00866              && h->root.type != bfd_link_hash_defweak)
00867            {
00868              /* This appears to be a reference to an undefined
00869                  symbol.  Just ignore it--it will be caught by the
00870                  regular reloc processing.  */
00871              continue;
00872            }
00873 
00874          symval = (h->root.u.def.value
00875                   + h->root.u.def.section->output_section->vma
00876                   + h->root.u.def.section->output_offset);
00877        }
00878 
00879       symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
00880 
00881       /* See if this function call can be shortened.  */
00882       foff = (symval
00883              - (irel->r_vaddr
00884                - sec->vma
00885                + sec->output_section->vma
00886                + sec->output_offset
00887                + 4));
00888       if (foff < -0x1000 || foff >= 0x1000)
00889        {
00890          /* After all that work, we can't shorten this function call.  */
00891          continue;
00892        }
00893 
00894       /* Shorten the function call.  */
00895 
00896       /* For simplicity of coding, we are going to modify the section
00897         contents, the section relocs, and the BFD symbol table.  We
00898         must tell the rest of the code not to free up this
00899         information.  It would be possible to instead create a table
00900         of changes which have to be made, as is done in coff-mips.c;
00901         that would be more work, but would require less memory when
00902         the linker is run.  */
00903 
00904       coff_section_data (abfd, sec)->relocs = internal_relocs;
00905       coff_section_data (abfd, sec)->keep_relocs = TRUE;
00906 
00907       coff_section_data (abfd, sec)->contents = contents;
00908       coff_section_data (abfd, sec)->keep_contents = TRUE;
00909 
00910       obj_coff_keep_syms (abfd) = TRUE;
00911 
00912       /* Replace the jsr with a bsr.  */
00913 
00914       /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
00915          replace the jsr with a bsr.  */
00916       irel->r_type = R_SH_PCDISP;
00917       irel->r_symndx = irelfn->r_symndx;
00918       if (sym.n_sclass != C_EXT)
00919        {
00920          /* If this needs to be changed because of future relaxing,
00921              it will be handled here like other internal PCDISP
00922              relocs.  */
00923          bfd_put_16 (abfd,
00924                     (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
00925                     contents + irel->r_vaddr - sec->vma);
00926        }
00927       else
00928        {
00929          /* We can't fully resolve this yet, because the external
00930              symbol value may be changed by future relaxing.  We let
00931              the final link phase handle it.  */
00932          bfd_put_16 (abfd, (bfd_vma) 0xb000,
00933                     contents + irel->r_vaddr - sec->vma);
00934        }
00935 
00936       /* See if there is another R_SH_USES reloc referring to the same
00937          register load.  */
00938       for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
00939        if (irelscan->r_type == R_SH_USES
00940            && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
00941          break;
00942       if (irelscan < irelend)
00943        {
00944          /* Some other function call depends upon this register load,
00945             and we have not yet converted that function call.
00946             Indeed, we may never be able to convert it.  There is
00947             nothing else we can do at this point.  */
00948          continue;
00949        }
00950 
00951       /* Look for a R_SH_COUNT reloc on the location where the
00952          function address is stored.  Do this before deleting any
00953          bytes, to avoid confusion about the address.  */
00954       for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
00955        if (irelcount->r_vaddr == paddr
00956            && irelcount->r_type == R_SH_COUNT)
00957          break;
00958 
00959       /* Delete the register load.  */
00960       if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
00961        goto error_return;
00962 
00963       /* That will change things, so, just in case it permits some
00964          other function call to come within range, we should relax
00965          again.  Note that this is not required, and it may be slow.  */
00966       *again = TRUE;
00967 
00968       /* Now check whether we got a COUNT reloc.  */
00969       if (irelcount >= irelend)
00970        {
00971          ((*_bfd_error_handler)
00972           ("%B: 0x%lx: warning: could not find expected COUNT reloc",
00973            abfd, (unsigned long) paddr));
00974          continue;
00975        }
00976 
00977       /* The number of uses is stored in the r_offset field.  We've
00978          just deleted one.  */
00979       if (irelcount->r_offset == 0)
00980        {
00981          ((*_bfd_error_handler) ("%B: 0x%lx: warning: bad count",
00982                               abfd, (unsigned long) paddr));
00983          continue;
00984        }
00985 
00986       --irelcount->r_offset;
00987 
00988       /* If there are no more uses, we can delete the address.  Reload
00989          the address from irelfn, in case it was changed by the
00990          previous call to sh_relax_delete_bytes.  */
00991       if (irelcount->r_offset == 0)
00992        {
00993          if (! sh_relax_delete_bytes (abfd, sec,
00994                                    irelfn->r_vaddr - sec->vma, 4))
00995            goto error_return;
00996        }
00997 
00998       /* We've done all we can with that function call.  */
00999     }
01000 
01001   /* Look for load and store instructions that we can align on four
01002      byte boundaries.  */
01003   if (have_code)
01004     {
01005       bfd_boolean swapped;
01006 
01007       /* Get the section contents.  */
01008       if (contents == NULL)
01009        {
01010          if (coff_section_data (abfd, sec)->contents != NULL)
01011            contents = coff_section_data (abfd, sec)->contents;
01012          else
01013            {
01014              if (!bfd_malloc_and_get_section (abfd, sec, &contents))
01015               goto error_return;
01016            }
01017        }
01018 
01019       if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
01020        goto error_return;
01021 
01022       if (swapped)
01023        {
01024          coff_section_data (abfd, sec)->relocs = internal_relocs;
01025          coff_section_data (abfd, sec)->keep_relocs = TRUE;
01026 
01027          coff_section_data (abfd, sec)->contents = contents;
01028          coff_section_data (abfd, sec)->keep_contents = TRUE;
01029 
01030          obj_coff_keep_syms (abfd) = TRUE;
01031        }
01032     }
01033 
01034   if (internal_relocs != NULL
01035       && internal_relocs != coff_section_data (abfd, sec)->relocs)
01036     {
01037       if (! link_info->keep_memory)
01038        free (internal_relocs);
01039       else
01040        coff_section_data (abfd, sec)->relocs = internal_relocs;
01041     }
01042 
01043   if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
01044     {
01045       if (! link_info->keep_memory)
01046        free (contents);
01047       else
01048        /* Cache the section contents for coff_link_input_bfd.  */
01049        coff_section_data (abfd, sec)->contents = contents;
01050     }
01051 
01052   return TRUE;
01053 
01054  error_return:
01055   if (internal_relocs != NULL
01056       && internal_relocs != coff_section_data (abfd, sec)->relocs)
01057     free (internal_relocs);
01058   if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
01059     free (contents);
01060   return FALSE;
01061 }
01062 
01063 /* Delete some bytes from a section while relaxing.  */
01064 
01065 static bfd_boolean
01066 sh_relax_delete_bytes (abfd, sec, addr, count)
01067      bfd *abfd;
01068      asection *sec;
01069      bfd_vma addr;
01070      int count;
01071 {
01072   bfd_byte *contents;
01073   struct internal_reloc *irel, *irelend;
01074   struct internal_reloc *irelalign;
01075   bfd_vma toaddr;
01076   bfd_byte *esym, *esymend;
01077   bfd_size_type symesz;
01078   struct coff_link_hash_entry **sym_hash;
01079   asection *o;
01080 
01081   contents = coff_section_data (abfd, sec)->contents;
01082 
01083   /* The deletion must stop at the next ALIGN reloc for an aligment
01084      power larger than the number of bytes we are deleting.  */
01085 
01086   irelalign = NULL;
01087   toaddr = sec->size;
01088 
01089   irel = coff_section_data (abfd, sec)->relocs;
01090   irelend = irel + sec->reloc_count;
01091   for (; irel < irelend; irel++)
01092     {
01093       if (irel->r_type == R_SH_ALIGN
01094          && irel->r_vaddr - sec->vma > addr
01095          && count < (1 << irel->r_offset))
01096        {
01097          irelalign = irel;
01098          toaddr = irel->r_vaddr - sec->vma;
01099          break;
01100        }
01101     }
01102 
01103   /* Actually delete the bytes.  */
01104   memmove (contents + addr, contents + addr + count,
01105           (size_t) (toaddr - addr - count));
01106   if (irelalign == NULL)
01107     sec->size -= count;
01108   else
01109     {
01110       int i;
01111 
01112 #define NOP_OPCODE (0x0009)
01113 
01114       BFD_ASSERT ((count & 1) == 0);
01115       for (i = 0; i < count; i += 2)
01116        bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
01117     }
01118 
01119   /* Adjust all the relocs.  */
01120   for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
01121     {
01122       bfd_vma nraddr, stop;
01123       bfd_vma start = 0;
01124       int insn = 0;
01125       struct internal_syment sym;
01126       int off, adjust, oinsn;
01127       bfd_signed_vma voff = 0;
01128       bfd_boolean overflow;
01129 
01130       /* Get the new reloc address.  */
01131       nraddr = irel->r_vaddr - sec->vma;
01132       if ((irel->r_vaddr - sec->vma > addr
01133           && irel->r_vaddr - sec->vma < toaddr)
01134          || (irel->r_type == R_SH_ALIGN
01135              && irel->r_vaddr - sec->vma == toaddr))
01136        nraddr -= count;
01137 
01138       /* See if this reloc was for the bytes we have deleted, in which
01139         case we no longer care about it.  Don't delete relocs which
01140         represent addresses, though.  */
01141       if (irel->r_vaddr - sec->vma >= addr
01142          && irel->r_vaddr - sec->vma < addr + count
01143          && irel->r_type != R_SH_ALIGN
01144          && irel->r_type != R_SH_CODE
01145          && irel->r_type != R_SH_DATA
01146          && irel->r_type != R_SH_LABEL)
01147        irel->r_type = R_SH_UNUSED;
01148 
01149       /* If this is a PC relative reloc, see if the range it covers
01150          includes the bytes we have deleted.  */
01151       switch (irel->r_type)
01152        {
01153        default:
01154          break;
01155 
01156        case R_SH_PCDISP8BY2:
01157        case R_SH_PCDISP:
01158        case R_SH_PCRELIMM8BY2:
01159        case R_SH_PCRELIMM8BY4:
01160          start = irel->r_vaddr - sec->vma;
01161          insn = bfd_get_16 (abfd, contents + nraddr);
01162          break;
01163        }
01164 
01165       switch (irel->r_type)
01166        {
01167        default:
01168          start = stop = addr;
01169          break;
01170 
01171        case R_SH_IMM32:
01172 #ifdef COFF_WITH_PE
01173        case R_SH_IMM32CE:
01174        case R_SH_IMAGEBASE:
01175 #endif
01176          /* If this reloc is against a symbol defined in this
01177              section, and the symbol will not be adjusted below, we
01178              must check the addend to see it will put the value in
01179              range to be adjusted, and hence must be changed.  */
01180          bfd_coff_swap_sym_in (abfd,
01181                             ((bfd_byte *) obj_coff_external_syms (abfd)
01182                              + (irel->r_symndx
01183                                 * bfd_coff_symesz (abfd))),
01184                             &sym);
01185          if (sym.n_sclass != C_EXT
01186              && sym.n_scnum == sec->target_index
01187              && ((bfd_vma) sym.n_value <= addr
01188                 || (bfd_vma) sym.n_value >= toaddr))
01189            {
01190              bfd_vma val;
01191 
01192              val = bfd_get_32 (abfd, contents + nraddr);
01193              val += sym.n_value;
01194              if (val > addr && val < toaddr)
01195               bfd_put_32 (abfd, val - count, contents + nraddr);
01196            }
01197          start = stop = addr;
01198          break;
01199 
01200        case R_SH_PCDISP8BY2:
01201          off = insn & 0xff;
01202          if (off & 0x80)
01203            off -= 0x100;
01204          stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
01205          break;
01206 
01207        case R_SH_PCDISP:
01208          bfd_coff_swap_sym_in (abfd,
01209                             ((bfd_byte *) obj_coff_external_syms (abfd)
01210                              + (irel->r_symndx
01211                                 * bfd_coff_symesz (abfd))),
01212                             &sym);
01213          if (sym.n_sclass == C_EXT)
01214            start = stop = addr;
01215          else
01216            {
01217              off = insn & 0xfff;
01218              if (off & 0x800)
01219               off -= 0x1000;
01220              stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
01221            }
01222          break;
01223 
01224        case R_SH_PCRELIMM8BY2:
01225          off = insn & 0xff;
01226          stop = start + 4 + off * 2;
01227          break;
01228 
01229        case R_SH_PCRELIMM8BY4:
01230          off = insn & 0xff;
01231          stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
01232          break;
01233 
01234        case R_SH_SWITCH8:
01235        case R_SH_SWITCH16:
01236        case R_SH_SWITCH32:
01237          /* These relocs types represent
01238               .word L2-L1
01239             The r_offset field holds the difference between the reloc
01240             address and L1.  That is the start of the reloc, and
01241             adding in the contents gives us the top.  We must adjust
01242             both the r_offset field and the section contents.  */
01243 
01244          start = irel->r_vaddr - sec->vma;
01245          stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
01246 
01247          if (start > addr
01248              && start < toaddr
01249              && (stop <= addr || stop >= toaddr))
01250            irel->r_offset += count;
01251          else if (stop > addr
01252                  && stop < toaddr
01253                  && (start <= addr || start >= toaddr))
01254            irel->r_offset -= count;
01255 
01256          start = stop;
01257 
01258          if (irel->r_type == R_SH_SWITCH16)
01259            voff = bfd_get_signed_16 (abfd, contents + nraddr);
01260          else if (irel->r_type == R_SH_SWITCH8)
01261            voff = bfd_get_8 (abfd, contents + nraddr);
01262          else
01263            voff = bfd_get_signed_32 (abfd, contents + nraddr);
01264          stop = (bfd_vma) ((bfd_signed_vma) start + voff);
01265 
01266          break;
01267 
01268        case R_SH_USES:
01269          start = irel->r_vaddr - sec->vma;
01270          stop = (bfd_vma) ((bfd_signed_vma) start
01271                          + (long) irel->r_offset
01272                          + 4);
01273          break;
01274        }
01275 
01276       if (start > addr
01277          && start < toaddr
01278          && (stop <= addr || stop >= toaddr))
01279        adjust = count;
01280       else if (stop > addr
01281               && stop < toaddr
01282               && (start <= addr || start >= toaddr))
01283        adjust = - count;
01284       else
01285        adjust = 0;
01286 
01287       if (adjust != 0)
01288        {
01289          oinsn = insn;
01290          overflow = FALSE;
01291          switch (irel->r_type)
01292            {
01293            default:
01294              abort ();
01295              break;
01296 
01297            case R_SH_PCDISP8BY2:
01298            case R_SH_PCRELIMM8BY2:
01299              insn += adjust / 2;
01300              if ((oinsn & 0xff00) != (insn & 0xff00))
01301               overflow = TRUE;
01302              bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
01303              break;
01304 
01305            case R_SH_PCDISP:
01306              insn += adjust / 2;
01307              if ((oinsn & 0xf000) != (insn & 0xf000))
01308               overflow = TRUE;
01309              bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
01310              break;
01311 
01312            case R_SH_PCRELIMM8BY4:
01313              BFD_ASSERT (adjust == count || count >= 4);
01314              if (count >= 4)
01315               insn += adjust / 4;
01316              else
01317               {
01318                 if ((irel->r_vaddr & 3) == 0)
01319                   ++insn;
01320               }
01321              if ((oinsn & 0xff00) != (insn & 0xff00))
01322               overflow = TRUE;
01323              bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
01324              break;
01325 
01326            case R_SH_SWITCH8:
01327              voff += adjust;
01328              if (voff < 0 || voff >= 0xff)
01329               overflow = TRUE;
01330              bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
01331              break;
01332 
01333            case R_SH_SWITCH16:
01334              voff += adjust;
01335              if (voff < - 0x8000 || voff >= 0x8000)
01336               overflow = TRUE;
01337              bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
01338              break;
01339 
01340            case R_SH_SWITCH32:
01341              voff += adjust;
01342              bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
01343              break;
01344 
01345            case R_SH_USES:
01346              irel->r_offset += adjust;
01347              break;
01348            }
01349 
01350          if (overflow)
01351            {
01352              ((*_bfd_error_handler)
01353               ("%B: 0x%lx: fatal: reloc overflow while relaxing",
01354               abfd, (unsigned long) irel->r_vaddr));
01355              bfd_set_error (bfd_error_bad_value);
01356              return FALSE;
01357            }
01358        }
01359 
01360       irel->r_vaddr = nraddr + sec->vma;
01361     }
01362 
01363   /* Look through all the other sections.  If there contain any IMM32
01364      relocs against internal symbols which we are not going to adjust
01365      below, we may need to adjust the addends.  */
01366   for (o = abfd->sections; o != NULL; o = o->next)
01367     {
01368       struct internal_reloc *internal_relocs;
01369       struct internal_reloc *irelscan, *irelscanend;
01370       bfd_byte *ocontents;
01371 
01372       if (o == sec
01373          || (o->flags & SEC_RELOC) == 0
01374          || o->reloc_count == 0)
01375        continue;
01376 
01377       /* We always cache the relocs.  Perhaps, if info->keep_memory is
01378          FALSE, we should free them, if we are permitted to, when we
01379          leave sh_coff_relax_section.  */
01380       internal_relocs = (_bfd_coff_read_internal_relocs
01381                       (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
01382                        (struct internal_reloc *) NULL));
01383       if (internal_relocs == NULL)
01384        return FALSE;
01385 
01386       ocontents = NULL;
01387       irelscanend = internal_relocs + o->reloc_count;
01388       for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
01389        {
01390          struct internal_syment sym;
01391 
01392 #ifdef COFF_WITH_PE
01393          if (irelscan->r_type != R_SH_IMM32
01394              && irelscan->r_type != R_SH_IMAGEBASE
01395              && irelscan->r_type != R_SH_IMM32CE)
01396 #else
01397          if (irelscan->r_type != R_SH_IMM32)
01398 #endif
01399            continue;
01400 
01401          bfd_coff_swap_sym_in (abfd,
01402                             ((bfd_byte *) obj_coff_external_syms (abfd)
01403                              + (irelscan->r_symndx
01404                                 * bfd_coff_symesz (abfd))),
01405                             &sym);
01406          if (sym.n_sclass != C_EXT
01407              && sym.n_scnum == sec->target_index
01408              && ((bfd_vma) sym.n_value <= addr
01409                 || (bfd_vma) sym.n_value >= toaddr))
01410            {
01411              bfd_vma val;
01412 
01413              if (ocontents == NULL)
01414               {
01415                 if (coff_section_data (abfd, o)->contents != NULL)
01416                   ocontents = coff_section_data (abfd, o)->contents;
01417                 else
01418                   {
01419                     if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
01420                      return FALSE;
01421                     /* We always cache the section contents.
01422                          Perhaps, if info->keep_memory is FALSE, we
01423                          should free them, if we are permitted to,
01424                          when we leave sh_coff_relax_section.  */
01425                     coff_section_data (abfd, o)->contents = ocontents;
01426                   }
01427               }
01428 
01429              val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
01430              val += sym.n_value;
01431              if (val > addr && val < toaddr)
01432               bfd_put_32 (abfd, val - count,
01433                          ocontents + irelscan->r_vaddr - o->vma);
01434 
01435              coff_section_data (abfd, o)->keep_contents = TRUE;
01436            }
01437        }
01438     }
01439 
01440   /* Adjusting the internal symbols will not work if something has
01441      already retrieved the generic symbols.  It would be possible to
01442      make this work by adjusting the generic symbols at the same time.
01443      However, this case should not arise in normal usage.  */
01444   if (obj_symbols (abfd) != NULL
01445       || obj_raw_syments (abfd) != NULL)
01446     {
01447       ((*_bfd_error_handler)
01448        ("%B: fatal: generic symbols retrieved before relaxing", abfd));
01449       bfd_set_error (bfd_error_invalid_operation);
01450       return FALSE;
01451     }
01452 
01453   /* Adjust all the symbols.  */
01454   sym_hash = obj_coff_sym_hashes (abfd);
01455   symesz = bfd_coff_symesz (abfd);
01456   esym = (bfd_byte *) obj_coff_external_syms (abfd);
01457   esymend = esym + obj_raw_syment_count (abfd) * symesz;
01458   while (esym < esymend)
01459     {
01460       struct internal_syment isym;
01461 
01462       bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
01463 
01464       if (isym.n_scnum == sec->target_index
01465          && (bfd_vma) isym.n_value > addr
01466          && (bfd_vma) isym.n_value < toaddr)
01467        {
01468          isym.n_value -= count;
01469 
01470          bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
01471 
01472          if (*sym_hash != NULL)
01473            {
01474              BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
01475                        || (*sym_hash)->root.type == bfd_link_hash_defweak);
01476              BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
01477                        && (*sym_hash)->root.u.def.value < toaddr);
01478              (*sym_hash)->root.u.def.value -= count;
01479            }
01480        }
01481 
01482       esym += (isym.n_numaux + 1) * symesz;
01483       sym_hash += isym.n_numaux + 1;
01484     }
01485 
01486   /* See if we can move the ALIGN reloc forward.  We have adjusted
01487      r_vaddr for it already.  */
01488   if (irelalign != NULL)
01489     {
01490       bfd_vma alignto, alignaddr;
01491 
01492       alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
01493       alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
01494                           1 << irelalign->r_offset);
01495       if (alignto != alignaddr)
01496        {
01497          /* Tail recursion.  */
01498          return sh_relax_delete_bytes (abfd, sec, alignaddr,
01499                                    (int) (alignto - alignaddr));
01500        }
01501     }
01502 
01503   return TRUE;
01504 }
01505 
01506 /* This is yet another version of the SH opcode table, used to rapidly
01507    get information about a particular instruction.  */
01508 
01509 /* The opcode map is represented by an array of these structures.  The
01510    array is indexed by the high order four bits in the instruction.  */
01511 
01512 struct sh_major_opcode
01513 {
01514   /* A pointer to the instruction list.  This is an array which
01515      contains all the instructions with this major opcode.  */
01516   const struct sh_minor_opcode *minor_opcodes;
01517   /* The number of elements in minor_opcodes.  */
01518   unsigned short count;
01519 };
01520 
01521 /* This structure holds information for a set of SH opcodes.  The
01522    instruction code is anded with the mask value, and the resulting
01523    value is used to search the order opcode list.  */
01524 
01525 struct sh_minor_opcode
01526 {
01527   /* The sorted opcode list.  */
01528   const struct sh_opcode *opcodes;
01529   /* The number of elements in opcodes.  */
01530   unsigned short count;
01531   /* The mask value to use when searching the opcode list.  */
01532   unsigned short mask;
01533 };
01534 
01535 /* This structure holds information for an SH instruction.  An array
01536    of these structures is sorted in order by opcode.  */
01537 
01538 struct sh_opcode
01539 {
01540   /* The code for this instruction, after it has been anded with the
01541      mask value in the sh_major_opcode structure.  */
01542   unsigned short opcode;
01543   /* Flags for this instruction.  */
01544   unsigned long flags;
01545 };
01546 
01547 /* Flag which appear in the sh_opcode structure.  */
01548 
01549 /* This instruction loads a value from memory.  */
01550 #define LOAD (0x1)
01551 
01552 /* This instruction stores a value to memory.  */
01553 #define STORE (0x2)
01554 
01555 /* This instruction is a branch.  */
01556 #define BRANCH (0x4)
01557 
01558 /* This instruction has a delay slot.  */
01559 #define DELAY (0x8)
01560 
01561 /* This instruction uses the value in the register in the field at
01562    mask 0x0f00 of the instruction.  */
01563 #define USES1 (0x10)
01564 #define USES1_REG(x) ((x & 0x0f00) >> 8)
01565 
01566 /* This instruction uses the value in the register in the field at
01567    mask 0x00f0 of the instruction.  */
01568 #define USES2 (0x20)
01569 #define USES2_REG(x) ((x & 0x00f0) >> 4)
01570 
01571 /* This instruction uses the value in register 0.  */
01572 #define USESR0 (0x40)
01573 
01574 /* This instruction sets the value in the register in the field at
01575    mask 0x0f00 of the instruction.  */
01576 #define SETS1 (0x80)
01577 #define SETS1_REG(x) ((x & 0x0f00) >> 8)
01578 
01579 /* This instruction sets the value in the register in the field at
01580    mask 0x00f0 of the instruction.  */
01581 #define SETS2 (0x100)
01582 #define SETS2_REG(x) ((x & 0x00f0) >> 4)
01583 
01584 /* This instruction sets register 0.  */
01585 #define SETSR0 (0x200)
01586 
01587 /* This instruction sets a special register.  */
01588 #define SETSSP (0x400)
01589 
01590 /* This instruction uses a special register.  */
01591 #define USESSP (0x800)
01592 
01593 /* This instruction uses the floating point register in the field at
01594    mask 0x0f00 of the instruction.  */
01595 #define USESF1 (0x1000)
01596 #define USESF1_REG(x) ((x & 0x0f00) >> 8)
01597 
01598 /* This instruction uses the floating point register in the field at
01599    mask 0x00f0 of the instruction.  */
01600 #define USESF2 (0x2000)
01601 #define USESF2_REG(x) ((x & 0x00f0) >> 4)
01602 
01603 /* This instruction uses floating point register 0.  */
01604 #define USESF0 (0x4000)
01605 
01606 /* This instruction sets the floating point register in the field at
01607    mask 0x0f00 of the instruction.  */
01608 #define SETSF1 (0x8000)
01609 #define SETSF1_REG(x) ((x & 0x0f00) >> 8)
01610 
01611 #define USESAS (0x10000)
01612 #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
01613 #define USESR8 (0x20000)
01614 #define SETSAS (0x40000)
01615 #define SETSAS_REG(x) USESAS_REG (x)
01616 
01617 #define MAP(a) a, sizeof a / sizeof a[0]
01618 
01619 #ifndef COFF_IMAGE_WITH_PE
01620 static bfd_boolean sh_insn_uses_reg
01621   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
01622 static bfd_boolean sh_insn_sets_reg
01623   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
01624 static bfd_boolean sh_insn_uses_or_sets_reg
01625   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
01626 static bfd_boolean sh_insn_uses_freg
01627   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
01628 static bfd_boolean sh_insn_sets_freg
01629   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
01630 static bfd_boolean sh_insn_uses_or_sets_freg
01631   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
01632 static bfd_boolean sh_insns_conflict
01633   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
01634           const struct sh_opcode *));
01635 static bfd_boolean sh_load_use
01636   PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
01637           const struct sh_opcode *));
01638 
01639 /* The opcode maps.  */
01640 
01641 static const struct sh_opcode sh_opcode00[] =
01642 {
01643   { 0x0008, SETSSP },                     /* clrt */
01644   { 0x0009, 0 },                   /* nop */
01645   { 0x000b, BRANCH | DELAY | USESSP },    /* rts */
01646   { 0x0018, SETSSP },                     /* sett */
01647   { 0x0019, SETSSP },                     /* div0u */
01648   { 0x001b, 0 },                   /* sleep */
01649   { 0x0028, SETSSP },                     /* clrmac */
01650   { 0x002b, BRANCH | DELAY | SETSSP },    /* rte */
01651   { 0x0038, USESSP | SETSSP },            /* ldtlb */
01652   { 0x0048, SETSSP },                     /* clrs */
01653   { 0x0058, SETSSP }               /* sets */
01654 };
01655 
01656 static const struct sh_opcode sh_opcode01[] =
01657 {
01658   { 0x0003, BRANCH | DELAY | USES1 | SETSSP },   /* bsrf rn */
01659   { 0x000a, SETS1 | USESSP },                    /* sts mach,rn */
01660   { 0x001a, SETS1 | USESSP },                    /* sts macl,rn */
01661   { 0x0023, BRANCH | DELAY | USES1 },            /* braf rn */
01662   { 0x0029, SETS1 | USESSP },                    /* movt rn */
01663   { 0x002a, SETS1 | USESSP },                    /* sts pr,rn */
01664   { 0x005a, SETS1 | USESSP },                    /* sts fpul,rn */
01665   { 0x006a, SETS1 | USESSP },                    /* sts fpscr,rn / sts dsr,rn */
01666   { 0x0083, LOAD | USES1 },               /* pref @rn */
01667   { 0x007a, SETS1 | USESSP },                    /* sts a0,rn */
01668   { 0x008a, SETS1 | USESSP },                    /* sts x0,rn */
01669   { 0x009a, SETS1 | USESSP },                    /* sts x1,rn */
01670   { 0x00aa, SETS1 | USESSP },                    /* sts y0,rn */
01671   { 0x00ba, SETS1 | USESSP }                     /* sts y1,rn */
01672 };
01673 
01674 static const struct sh_opcode sh_opcode02[] =
01675 {
01676   { 0x0002, SETS1 | USESSP },                    /* stc <special_reg>,rn */
01677   { 0x0004, STORE | USES1 | USES2 | USESR0 },    /* mov.b rm,@(r0,rn) */
01678   { 0x0005, STORE | USES1 | USES2 | USESR0 },    /* mov.w rm,@(r0,rn) */
01679   { 0x0006, STORE | USES1 | USES2 | USESR0 },    /* mov.l rm,@(r0,rn) */
01680   { 0x0007, SETSSP | USES1 | USES2 },            /* mul.l rm,rn */
01681   { 0x000c, LOAD | SETS1 | USES2 | USESR0 },     /* mov.b @(r0,rm),rn */
01682   { 0x000d, LOAD | SETS1 | USES2 | USESR0 },     /* mov.w @(r0,rm),rn */
01683   { 0x000e, LOAD | SETS1 | USES2 | USESR0 },     /* mov.l @(r0,rm),rn */
01684   { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
01685 };
01686 
01687 static const struct sh_minor_opcode sh_opcode0[] =
01688 {
01689   { MAP (sh_opcode00), 0xffff },
01690   { MAP (sh_opcode01), 0xf0ff },
01691   { MAP (sh_opcode02), 0xf00f }
01692 };
01693 
01694 static const struct sh_opcode sh_opcode10[] =
01695 {
01696   { 0x1000, STORE | USES1 | USES2 }       /* mov.l rm,@(disp,rn) */
01697 };
01698 
01699 static const struct sh_minor_opcode sh_opcode1[] =
01700 {
01701   { MAP (sh_opcode10), 0xf000 }
01702 };
01703 
01704 static const struct sh_opcode sh_opcode20[] =
01705 {
01706   { 0x2000, STORE | USES1 | USES2 },             /* mov.b rm,@rn */
01707   { 0x2001, STORE | USES1 | USES2 },             /* mov.w rm,@rn */
01708   { 0x2002, STORE | USES1 | USES2 },             /* mov.l rm,@rn */
01709   { 0x2004, STORE | SETS1 | USES1 | USES2 },     /* mov.b rm,@-rn */
01710   { 0x2005, STORE | SETS1 | USES1 | USES2 },     /* mov.w rm,@-rn */
01711   { 0x2006, STORE | SETS1 | USES1 | USES2 },     /* mov.l rm,@-rn */
01712   { 0x2007, SETSSP | USES1 | USES2 | USESSP },   /* div0s */
01713   { 0x2008, SETSSP | USES1 | USES2 },            /* tst rm,rn */
01714   { 0x2009, SETS1 | USES1 | USES2 },             /* and rm,rn */
01715   { 0x200a, SETS1 | USES1 | USES2 },             /* xor rm,rn */
01716   { 0x200b, SETS1 | USES1 | USES2 },             /* or rm,rn */
01717   { 0x200c, SETSSP | USES1 | USES2 },            /* cmp/str rm,rn */
01718   { 0x200d, SETS1 | USES1 | USES2 },             /* xtrct rm,rn */
01719   { 0x200e, SETSSP | USES1 | USES2 },            /* mulu.w rm,rn */
01720   { 0x200f, SETSSP | USES1 | USES2 }             /* muls.w rm,rn */
01721 };
01722 
01723 static const struct sh_minor_opcode sh_opcode2[] =
01724 {
01725   { MAP (sh_opcode20), 0xf00f }
01726 };
01727 
01728 static const struct sh_opcode sh_opcode30[] =
01729 {
01730   { 0x3000, SETSSP | USES1 | USES2 },            /* cmp/eq rm,rn */
01731   { 0x3002, SETSSP | USES1 | USES2 },            /* cmp/hs rm,rn */
01732   { 0x3003, SETSSP | USES1 | USES2 },            /* cmp/ge rm,rn */
01733   { 0x3004, SETSSP | USESSP | USES1 | USES2 },   /* div1 rm,rn */
01734   { 0x3005, SETSSP | USES1 | USES2 },            /* dmulu.l rm,rn */
01735   { 0x3006, SETSSP | USES1 | USES2 },            /* cmp/hi rm,rn */
01736   { 0x3007, SETSSP | USES1 | USES2 },            /* cmp/gt rm,rn */
01737   { 0x3008, SETS1 | USES1 | USES2 },             /* sub rm,rn */
01738   { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
01739   { 0x300b, SETS1 | SETSSP | USES1 | USES2 },    /* subv rm,rn */
01740   { 0x300c, SETS1 | USES1 | USES2 },             /* add rm,rn */
01741   { 0x300d, SETSSP | USES1 | USES2 },            /* dmuls.l rm,rn */
01742   { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
01743   { 0x300f, SETS1 | SETSSP | USES1 | USES2 }     /* addv rm,rn */
01744 };
01745 
01746 static const struct sh_minor_opcode sh_opcode3[] =
01747 {
01748   { MAP (sh_opcode30), 0xf00f }
01749 };
01750 
01751 static const struct sh_opcode sh_opcode40[] =
01752 {
01753   { 0x4000, SETS1 | SETSSP | USES1 },            /* shll rn */
01754   { 0x4001, SETS1 | SETSSP | USES1 },            /* shlr rn */
01755   { 0x4002, STORE | SETS1 | USES1 | USESSP },    /* sts.l mach,@-rn */
01756   { 0x4004, SETS1 | SETSSP | USES1 },            /* rotl rn */
01757   { 0x4005, SETS1 | SETSSP | USES1 },            /* rotr rn */
01758   { 0x4006, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,mach */
01759   { 0x4008, SETS1 | USES1 },                     /* shll2 rn */
01760   { 0x4009, SETS1 | USES1 },                     /* shlr2 rn */
01761   { 0x400a, SETSSP | USES1 },                    /* lds rm,mach */
01762   { 0x400b, BRANCH | DELAY | USES1 },            /* jsr @rn */
01763   { 0x4010, SETS1 | SETSSP | USES1 },            /* dt rn */
01764   { 0x4011, SETSSP | USES1 },                    /* cmp/pz rn */
01765   { 0x4012, STORE | SETS1 | USES1 | USESSP },    /* sts.l macl,@-rn */
01766   { 0x4014, SETSSP | USES1 },                    /* setrc rm */
01767   { 0x4015, SETSSP | USES1 },                    /* cmp/pl rn */
01768   { 0x4016, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,macl */
01769   { 0x4018, SETS1 | USES1 },                     /* shll8 rn */
01770   { 0x4019, SETS1 | USES1 },                     /* shlr8 rn */
01771   { 0x401a, SETSSP | USES1 },                    /* lds rm,macl */
01772   { 0x401b, LOAD | SETSSP | USES1 },             /* tas.b @rn */
01773   { 0x4020, SETS1 | SETSSP | USES1 },            /* shal rn */
01774   { 0x4021, SETS1 | SETSSP | USES1 },            /* shar rn */
01775   { 0x4022, STORE | SETS1 | USES1 | USESSP },    /* sts.l pr,@-rn */
01776   { 0x4024, SETS1 | SETSSP | USES1 | USESSP },   /* rotcl rn */
01777   { 0x4025, SETS1 | SETSSP | USES1 | USESSP },   /* rotcr rn */
01778   { 0x4026, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,pr */
01779   { 0x4028, SETS1 | USES1 },                     /* shll16 rn */
01780   { 0x4029, SETS1 | USES1 },                     /* shlr16 rn */
01781   { 0x402a, SETSSP | USES1 },                    /* lds rm,pr */
01782   { 0x402b, BRANCH | DELAY | USES1 },            /* jmp @rn */
01783   { 0x4052, STORE | SETS1 | USES1 | USESSP },    /* sts.l fpul,@-rn */
01784   { 0x4056, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,fpul */
01785   { 0x405a, SETSSP | USES1 },                    /* lds.l rm,fpul */
01786   { 0x4062, STORE | SETS1 | USES1 | USESSP },    /* sts.l fpscr / dsr,@-rn */
01787   { 0x4066, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,fpscr / dsr */
01788   { 0x406a, SETSSP | USES1 },                    /* lds rm,fpscr / lds rm,dsr */
01789   { 0x4072, STORE | SETS1 | USES1 | USESSP },    /* sts.l a0,@-rn */
01790   { 0x4076, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,a0 */
01791   { 0x407a, SETSSP | USES1 },                    /* lds.l rm,a0 */
01792   { 0x4082, STORE | SETS1 | USES1 | USESSP },    /* sts.l x0,@-rn */
01793   { 0x4086, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,x0 */
01794   { 0x408a, SETSSP | USES1 },                    /* lds.l rm,x0 */
01795   { 0x4092, STORE | SETS1 | USES1 | USESSP },    /* sts.l x1,@-rn */
01796   { 0x4096, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,x1 */
01797   { 0x409a, SETSSP | USES1 },                    /* lds.l rm,x1 */
01798   { 0x40a2, STORE | SETS1 | USES1 | USESSP },    /* sts.l y0,@-rn */
01799   { 0x40a6, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,y0 */
01800   { 0x40aa, SETSSP | USES1 },                    /* lds.l rm,y0 */
01801   { 0x40b2, STORE | SETS1 | USES1 | USESSP },    /* sts.l y1,@-rn */
01802   { 0x40b6, LOAD | SETS1 | SETSSP | USES1 },     /* lds.l @rm+,y1 */
01803   { 0x40ba, SETSSP | USES1 }                     /* lds.l rm,y1 */
01804 };
01805 
01806 static const struct sh_opcode sh_opcode41[] =
01807 {
01808   { 0x4003, STORE | SETS1 | USES1 | USESSP },    /* stc.l <special_reg>,@-rn */
01809   { 0x4007, LOAD | SETS1 | SETSSP | USES1 },     /* ldc.l @rm+,<special_reg> */
01810   { 0x400c, SETS1 | USES1 | USES2 },             /* shad rm,rn */
01811   { 0x400d, SETS1 | USES1 | USES2 },             /* shld rm,rn */
01812   { 0x400e, SETSSP | USES1 },                    /* ldc rm,<special_reg> */
01813   { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
01814 };
01815 
01816 static const struct sh_minor_opcode sh_opcode4[] =
01817 {
01818   { MAP (sh_opcode40), 0xf0ff },
01819   { MAP (sh_opcode41), 0xf00f }
01820 };
01821 
01822 static const struct sh_opcode sh_opcode50[] =
01823 {
01824   { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
01825 };
01826 
01827 static const struct sh_minor_opcode sh_opcode5[] =
01828 {
01829   { MAP (sh_opcode50), 0xf000 }
01830 };
01831 
01832 static const struct sh_opcode sh_opcode60[] =
01833 {
01834   { 0x6000, LOAD | SETS1 | USES2 },              /* mov.b @rm,rn */
01835   { 0x6001, LOAD | SETS1 | USES2 },              /* mov.w @rm,rn */
01836   { 0x6002, LOAD | SETS1 | USES2 },              /* mov.l @rm,rn */
01837   { 0x6003, SETS1 | USES2 },                     /* mov rm,rn */
01838   { 0x6004, LOAD | SETS1 | SETS2 | USES2 },      /* mov.b @rm+,rn */
01839   { 0x6005, LOAD | SETS1 | SETS2 | USES2 },      /* mov.w @rm+,rn */
01840   { 0x6006, LOAD | SETS1 | SETS2 | USES2 },      /* mov.l @rm+,rn */
01841   { 0x6007, SETS1 | USES2 },                     /* not rm,rn */
01842   { 0x6008, SETS1 | USES2 },                     /* swap.b rm,rn */
01843   { 0x6009, SETS1 | USES2 },                     /* swap.w rm,rn */
01844   { 0x600a, SETS1 | SETSSP | USES2 | USESSP },   /* negc rm,rn */
01845   { 0x600b, SETS1 | USES2 },                     /* neg rm,rn */
01846   { 0x600c, SETS1 | USES2 },                     /* extu.b rm,rn */
01847   { 0x600d, SETS1 | USES2 },                     /* extu.w rm,rn */
01848   { 0x600e, SETS1 | USES2 },                     /* exts.b rm,rn */
01849   { 0x600f, SETS1 | USES2 }               /* exts.w rm,rn */
01850 };
01851 
01852 static const struct sh_minor_opcode sh_opcode6[] =
01853 {
01854   { MAP (sh_opcode60), 0xf00f }
01855 };
01856 
01857 static const struct sh_opcode sh_opcode70[] =
01858 {
01859   { 0x7000, SETS1 | USES1 }        /* add #imm,rn */
01860 };
01861 
01862 static const struct sh_minor_opcode sh_opcode7[] =
01863 {
01864   { MAP (sh_opcode70), 0xf000 }
01865 };
01866 
01867 static const struct sh_opcode sh_opcode80[] =
01868 {
01869   { 0x8000, STORE | USES2 | USESR0 },     /* mov.b r0,@(disp,rn) */
01870   { 0x8100, STORE | USES2 | USESR0 },     /* mov.w r0,@(disp,rn) */
01871   { 0x8200, SETSSP },                     /* setrc #imm */
01872   { 0x8400, LOAD | SETSR0 | USES2 },      /* mov.b @(disp,rm),r0 */
01873   { 0x8500, LOAD | SETSR0 | USES2 },      /* mov.w @(disp,rn),r0 */
01874   { 0x8800, SETSSP | USESR0 },            /* cmp/eq #imm,r0 */
01875   { 0x8900, BRANCH | USESSP },            /* bt label */
01876   { 0x8b00, BRANCH | USESSP },            /* bf label */
01877   { 0x8c00, SETSSP },                     /* ldrs @(disp,pc) */
01878   { 0x8d00, BRANCH | DELAY | USESSP },    /* bt/s label */
01879   { 0x8e00, SETSSP },                     /* ldre @(disp,pc) */
01880   { 0x8f00, BRANCH | DELAY | USESSP }     /* bf/s label */
01881 };
01882 
01883 static const struct sh_minor_opcode sh_opcode8[] =
01884 {
01885   { MAP (sh_opcode80), 0xff00 }
01886 };
01887 
01888 static const struct sh_opcode sh_opcode90[] =
01889 {
01890   { 0x9000, LOAD | SETS1 }  /* mov.w @(disp,pc),rn */
01891 };
01892 
01893 static const struct sh_minor_opcode sh_opcode9[] =
01894 {
01895   { MAP (sh_opcode90), 0xf000 }
01896 };
01897 
01898 static const struct sh_opcode sh_opcodea0[] =
01899 {
01900   { 0xa000, BRANCH | DELAY }       /* bra label */
01901 };
01902 
01903 static const struct sh_minor_opcode sh_opcodea[] =
01904 {
01905   { MAP (sh_opcodea0), 0xf000 }
01906 };
01907 
01908 static const struct sh_opcode sh_opcodeb0[] =
01909 {
01910   { 0xb000, BRANCH | DELAY }       /* bsr label */
01911 };
01912 
01913 static const struct sh_minor_opcode sh_opcodeb[] =
01914 {
01915   { MAP (sh_opcodeb0), 0xf000 }
01916 };
01917 
01918 static const struct sh_opcode sh_opcodec0[] =
01919 {
01920   { 0xc000, STORE | USESR0 | USESSP },           /* mov.b r0,@(disp,gbr) */
01921   { 0xc100, STORE | USESR0 | USESSP },           /* mov.w r0,@(disp,gbr) */
01922   { 0xc200, STORE | USESR0 | USESSP },           /* mov.l r0,@(disp,gbr) */
01923   { 0xc300, BRANCH | USESSP },                   /* trapa #imm */
01924   { 0xc400, LOAD | SETSR0 | USESSP },            /* mov.b @(disp,gbr),r0 */
01925   { 0xc500, LOAD | SETSR0 | USESSP },            /* mov.w @(disp,gbr),r0 */
01926   { 0xc600, LOAD | SETSR0 | USESSP },            /* mov.l @(disp,gbr),r0 */
01927   { 0xc700, SETSR0 },                            /* mova @(disp,pc),r0 */
01928   { 0xc800, SETSSP | USESR0 },                   /* tst #imm,r0 */
01929   { 0xc900, SETSR0 | USESR0 },                   /* and #imm,r0 */
01930   { 0xca00, SETSR0 | USESR0 },                   /* xor #imm,r0 */
01931   { 0xcb00, SETSR0 | USESR0 },                   /* or #imm,r0 */
01932   { 0xcc00, LOAD | SETSSP | USESR0 | USESSP },   /* tst.b #imm,@(r0,gbr) */
01933   { 0xcd00, LOAD | STORE | USESR0 | USESSP },    /* and.b #imm,@(r0,gbr) */
01934   { 0xce00, LOAD | STORE | USESR0 | USESSP },    /* xor.b #imm,@(r0,gbr) */
01935   { 0xcf00, LOAD | STORE | USESR0 | USESSP }     /* or.b #imm,@(r0,gbr) */
01936 };
01937 
01938 static const struct sh_minor_opcode sh_opcodec[] =
01939 {
01940   { MAP (sh_opcodec0), 0xff00 }
01941 };
01942 
01943 static const struct sh_opcode sh_opcoded0[] =
01944 {
01945   { 0xd000, LOAD | SETS1 }         /* mov.l @(disp,pc),rn */
01946 };
01947 
01948 static const struct sh_minor_opcode sh_opcoded[] =
01949 {
01950   { MAP (sh_opcoded0), 0xf000 }
01951 };
01952 
01953 static const struct sh_opcode sh_opcodee0[] =
01954 {
01955   { 0xe000, SETS1 }         /* mov #imm,rn */
01956 };
01957 
01958 static const struct sh_minor_opcode sh_opcodee[] =
01959 {
01960   { MAP (sh_opcodee0), 0xf000 }
01961 };
01962 
01963 static const struct sh_opcode sh_opcodef0[] =
01964 {
01965   { 0xf000, SETSF1 | USESF1 | USESF2 },          /* fadd fm,fn */
01966   { 0xf001, SETSF1 | USESF1 | USESF2 },          /* fsub fm,fn */
01967   { 0xf002, SETSF1 | USESF1 | USESF2 },          /* fmul fm,fn */
01968   { 0xf003, SETSF1 | USESF1 | USESF2 },          /* fdiv fm,fn */
01969   { 0xf004, SETSSP | USESF1 | USESF2 },          /* fcmp/eq fm,fn */
01970   { 0xf005, SETSSP | USESF1 | USESF2 },          /* fcmp/gt fm,fn */
01971   { 0xf006, LOAD | SETSF1 | USES2 | USESR0 },    /* fmov.s @(r0,rm),fn */
01972   { 0xf007, STORE | USES1 | USESF2 | USESR0 },   /* fmov.s fm,@(r0,rn) */
01973   { 0xf008, LOAD | SETSF1 | USES2 },             /* fmov.s @rm,fn */
01974   { 0xf009, LOAD | SETS2 | SETSF1 | USES2 },     /* fmov.s @rm+,fn */
01975   { 0xf00a, STORE | USES1 | USESF2 },            /* fmov.s fm,@rn */
01976   { 0xf00b, STORE | SETS1 | USES1 | USESF2 },    /* fmov.s fm,@-rn */
01977   { 0xf00c, SETSF1 | USESF2 },                   /* fmov fm,fn */
01978   { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 }  /* fmac f0,fm,fn */
01979 };
01980 
01981 static const struct sh_opcode sh_opcodef1[] =
01982 {
01983   { 0xf00d, SETSF1 | USESSP },     /* fsts fpul,fn */
01984   { 0xf01d, SETSSP | USESF1 },     /* flds fn,fpul */
01985   { 0xf02d, SETSF1 | USESSP },     /* float fpul,fn */
01986   { 0xf03d, SETSSP | USESF1 },     /* ftrc fn,fpul */
01987   { 0xf04d, SETSF1 | USESF1 },     /* fneg fn */
01988   { 0xf05d, SETSF1 | USESF1 },     /* fabs fn */
01989   { 0xf06d, SETSF1 | USESF1 },     /* fsqrt fn */
01990   { 0xf07d, SETSSP | USESF1 },     /* ftst/nan fn */
01991   { 0xf08d, SETSF1 },              /* fldi0 fn */
01992   { 0xf09d, SETSF1 }        /* fldi1 fn */
01993 };
01994 
01995 static const struct sh_minor_opcode sh_opcodef[] =
01996 {
01997   { MAP (sh_opcodef0), 0xf00f },
01998   { MAP (sh_opcodef1), 0xf0ff }
01999 };
02000 
02001 static struct sh_major_opcode sh_opcodes[] =
02002 {
02003   { MAP (sh_opcode0) },
02004   { MAP (sh_opcode1) },
02005   { MAP (sh_opcode2) },
02006   { MAP (sh_opcode3) },
02007   { MAP (sh_opcode4) },
02008   { MAP (sh_opcode5) },
02009   { MAP (sh_opcode6) },
02010   { MAP (sh_opcode7) },
02011   { MAP (sh_opcode8) },
02012   { MAP (sh_opcode9) },
02013   { MAP (sh_opcodea) },
02014   { MAP (sh_opcodeb) },
02015   { MAP (sh_opcodec) },
02016   { MAP (sh_opcoded) },
02017   { MAP (sh_opcodee) },
02018   { MAP (sh_opcodef) }
02019 };
02020 
02021 /* The double data transfer / parallel processing insns are not
02022    described here.  This will cause sh_align_load_span to leave them alone.  */
02023 
02024 static const struct sh_opcode sh_dsp_opcodef0[] =
02025 {
02026   { 0xf400, USESAS | SETSAS | LOAD | SETSSP },   /* movs.x @-as,ds */
02027   { 0xf401, USESAS | SETSAS | STORE | USESSP },  /* movs.x ds,@-as */
02028   { 0xf404, USESAS | LOAD | SETSSP },            /* movs.x @as,ds */
02029   { 0xf405, USESAS | STORE | USESSP },           /* movs.x ds,@as */
02030   { 0xf408, USESAS | SETSAS | LOAD | SETSSP },   /* movs.x @as+,ds */
02031   { 0xf409, USESAS | SETSAS | STORE | USESSP },  /* movs.x ds,@as+ */
02032   { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
02033   { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
02034 };
02035 
02036 static const struct sh_minor_opcode sh_dsp_opcodef[] =
02037 {
02038   { MAP (sh_dsp_opcodef0), 0xfc0d }
02039 };
02040 
02041 /* Given an instruction, return a pointer to the corresponding
02042    sh_opcode structure.  Return NULL if the instruction is not
02043    recognized.  */
02044 
02045 static const struct sh_opcode *
02046 sh_insn_info (insn)
02047      unsigned int insn;
02048 {
02049   const struct sh_major_opcode *maj;
02050   const struct sh_minor_opcode *min, *minend;
02051 
02052   maj = &sh_opcodes[(insn & 0xf000) >> 12];
02053   min = maj->minor_opcodes;
02054   minend = min + maj->count;
02055   for (; min < minend; min++)
02056     {
02057       unsigned int l;
02058       const struct sh_opcode *op, *opend;
02059 
02060       l = insn & min->mask;
02061       op = min->opcodes;
02062       opend = op + min->count;
02063 
02064       /* Since the opcodes tables are sorted, we could use a binary
02065          search here if the count were above some cutoff value.  */
02066       for (; op < opend; op++)
02067        if (op->opcode == l)
02068          return op;
02069     }
02070 
02071   return NULL;
02072 }
02073 
02074 /* See whether an instruction uses or sets a general purpose register */
02075 
02076 static bfd_boolean
02077 sh_insn_uses_or_sets_reg (insn, op, reg)
02078      unsigned int insn;
02079      const struct sh_opcode *op;
02080      unsigned int reg;
02081 {
02082   if (sh_insn_uses_reg (insn, op, reg))
02083     return TRUE;
02084 
02085   return sh_insn_sets_reg (insn, op, reg);
02086 }
02087 
02088 /* See whether an instruction uses a general purpose register.  */
02089 
02090 static bfd_boolean
02091 sh_insn_uses_reg (insn, op, reg)
02092      unsigned int insn;
02093      const struct sh_opcode *op;
02094      unsigned int reg;
02095 {
02096   unsigned int f;
02097 
02098   f = op->flags;
02099 
02100   if ((f & USES1) != 0
02101       && USES1_REG (insn) == reg)
02102     return TRUE;
02103   if ((f & USES2) != 0
02104       && USES2_REG (insn) == reg)
02105     return TRUE;
02106   if ((f & USESR0) != 0
02107       && reg == 0)
02108     return TRUE;
02109   if ((f & USESAS) && reg == USESAS_REG (insn))
02110     return TRUE;
02111   if ((f & USESR8) && reg == 8)
02112     return TRUE;
02113 
02114   return FALSE;
02115 }
02116 
02117 /* See whether an instruction sets a general purpose register.  */
02118 
02119 static bfd_boolean
02120 sh_insn_sets_reg (insn, op, reg)
02121      unsigned int insn;
02122      const struct sh_opcode *op;
02123      unsigned int reg;
02124 {
02125   unsigned int f;
02126 
02127   f = op->flags;
02128 
02129   if ((f & SETS1) != 0
02130       && SETS1_REG (insn) == reg)
02131     return TRUE;
02132   if ((f & SETS2) != 0
02133       && SETS2_REG (insn) == reg)
02134     return TRUE;
02135   if ((f & SETSR0) != 0
02136       && reg == 0)
02137     return TRUE;
02138   if ((f & SETSAS) && reg == SETSAS_REG (insn))
02139     return TRUE;
02140 
02141   return FALSE;
02142 }
02143 
02144 /* See whether an instruction uses or sets a floating point register */
02145 
02146 static bfd_boolean
02147 sh_insn_uses_or_sets_freg (insn, op, reg)
02148      unsigned int insn;
02149      const struct sh_opcode *op;
02150      unsigned int reg;
02151 {
02152   if (sh_insn_uses_freg (insn, op, reg))
02153     return TRUE;
02154 
02155   return sh_insn_sets_freg (insn, op, reg);
02156 }
02157 
02158 /* See whether an instruction uses a floating point register.  */
02159 
02160 static bfd_boolean
02161 sh_insn_uses_freg (insn, op, freg)
02162      unsigned int insn;
02163      const struct sh_opcode *op;
02164      unsigned int freg;
02165 {
02166   unsigned int f;
02167 
02168   f = op->flags;
02169 
02170   /* We can't tell if this is a double-precision insn, so just play safe
02171      and assume that it might be.  So not only have we test FREG against
02172      itself, but also even FREG against FREG+1 - if the using insn uses
02173      just the low part of a double precision value - but also an odd
02174      FREG against FREG-1 -  if the setting insn sets just the low part
02175      of a double precision value.
02176      So what this all boils down to is that we have to ignore the lowest
02177      bit of the register number.  */
02178 
02179   if ((f & USESF1) != 0
02180       && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
02181     return TRUE;
02182   if ((f & USESF2) != 0
02183       && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
02184     return TRUE;
02185   if ((f & USESF0) != 0
02186       && freg == 0)
02187     return TRUE;
02188 
02189   return FALSE;
02190 }
02191 
02192 /* See whether an instruction sets a floating point register.  */
02193 
02194 static bfd_boolean
02195 sh_insn_sets_freg (insn, op, freg)
02196      unsigned int insn;
02197      const struct sh_opcode *op;
02198      unsigned int freg;
02199 {
02200   unsigned int f;
02201 
02202   f = op->flags;
02203 
02204   /* We can't tell if this is a double-precision insn, so just play safe
02205      and assume that it might be.  So not only have we test FREG against
02206      itself, but also even FREG against FREG+1 - if the using insn uses
02207      just the low part of a double precision value - but also an odd
02208      FREG against FREG-1 -  if the setting insn sets just the low part
02209      of a double precision value.
02210      So what this all boils down to is that we have to ignore the lowest
02211      bit of the register number.  */
02212 
02213   if ((f & SETSF1) != 0
02214       && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
02215     return TRUE;
02216 
02217   return FALSE;
02218 }
02219 
02220 /* See whether instructions I1 and I2 conflict, assuming I1 comes
02221    before I2.  OP1 and OP2 are the corresponding sh_opcode structures.
02222    This should return TRUE if there is a conflict, or FALSE if the
02223    instructions can be swapped safely.  */
02224 
02225 static bfd_boolean
02226 sh_insns_conflict (i1, op1, i2, op2)
02227      unsigned int i1;
02228      const struct sh_opcode *op1;
02229      unsigned int i2;
02230      const struct sh_opcode *op2;
02231 {
02232   unsigned int f1, f2;
02233 
02234   f1 = op1->flags;
02235   f2 = op2->flags;
02236 
02237   /* Load of fpscr conflicts with floating point operations.
02238      FIXME: shouldn't test raw opcodes here.  */
02239   if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
02240       || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
02241     return TRUE;
02242 
02243   if ((f1 & (BRANCH | DELAY)) != 0
02244       || (f2 & (BRANCH | DELAY)) != 0)
02245     return TRUE;
02246 
02247   if (((f1 | f2) & SETSSP)
02248       && (f1 & (SETSSP | USESSP))
02249       && (f2 & (SETSSP | USESSP)))
02250     return TRUE;
02251 
02252   if ((f1 & SETS1) != 0
02253       && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
02254     return TRUE;
02255   if ((f1 & SETS2) != 0
02256       && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
02257     return TRUE;
02258   if ((f1 & SETSR0) != 0
02259       && sh_insn_uses_or_sets_reg (i2, op2, 0))
02260     return TRUE;
02261   if ((f1 & SETSAS)
02262       && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
02263     return TRUE;
02264   if ((f1 & SETSF1) != 0
02265       && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
02266     return TRUE;
02267 
02268   if ((f2 & SETS1) != 0
02269       && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
02270     return TRUE;
02271   if ((f2 & SETS2) != 0
02272       && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
02273     return TRUE;
02274   if ((f2 & SETSR0) != 0
02275       && sh_insn_uses_or_sets_reg (i1, op1, 0))
02276     return TRUE;
02277   if ((f2 & SETSAS)
02278       && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
02279     return TRUE;
02280   if ((f2 & SETSF1) != 0
02281       && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
02282     return TRUE;
02283 
02284   /* The instructions do not conflict.  */
02285   return FALSE;
02286 }
02287 
02288 /* I1 is a load instruction, and I2 is some other instruction.  Return
02289    TRUE if I1 loads a register which I2 uses.  */
02290 
02291 static bfd_boolean
02292 sh_load_use (i1, op1, i2, op2)
02293      unsigned int i1;
02294      const struct sh_opcode *op1;
02295      unsigned int i2;
02296      const struct sh_opcode *op2;
02297 {
02298   unsigned int f1;
02299 
02300   f1 = op1->flags;
02301 
02302   if ((f1 & LOAD) == 0)
02303     return FALSE;
02304 
02305   /* If both SETS1 and SETSSP are set, that means a load to a special
02306      register using postincrement addressing mode, which we don't care
02307      about here.  */
02308   if ((f1 & SETS1) != 0
02309       && (f1 & SETSSP) == 0
02310       && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
02311     return TRUE;
02312 
02313   if ((f1 & SETSR0) != 0
02314       && sh_insn_uses_reg (i2, op2, 0))
02315     return TRUE;
02316 
02317   if ((f1 & SETSF1) != 0
02318       && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
02319     return TRUE;
02320 
02321   return FALSE;
02322 }
02323 
02324 /* Try to align loads and stores within a span of memory.  This is
02325    called by both the ELF and the COFF sh targets.  ABFD and SEC are
02326    the BFD and section we are examining.  CONTENTS is the contents of
02327    the section.  SWAP is the routine to call to swap two instructions.
02328    RELOCS is a pointer to the internal relocation information, to be
02329    passed to SWAP.  PLABEL is a pointer to the current label in a
02330    sorted list of labels; LABEL_END is the end of the list.  START and
02331    STOP are the range of memory to examine.  If a swap is made,
02332    *PSWAPPED is set to TRUE.  */
02333 
02334 #ifdef COFF_WITH_PE
02335 static
02336 #endif
02337 bfd_boolean
02338 _bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
02339                       plabel, label_end, start, stop, pswapped)
02340      bfd *abfd;
02341      asection *sec;
02342      bfd_byte *contents;
02343      bfd_boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
02344      PTR relocs;
02345      bfd_vma **plabel;
02346      bfd_vma *label_end;
02347      bfd_vma start;
02348      bfd_vma stop;
02349      bfd_boolean *pswapped;
02350 {
02351   int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
02352             || abfd->arch_info->mach == bfd_mach_sh3_dsp);
02353   bfd_vma i;
02354 
02355   /* The SH4 has a Harvard architecture, hence aligning loads is not
02356      desirable.  In fact, it is counter-productive, since it interferes
02357      with the schedules generated by the compiler.  */
02358   if (abfd->arch_info->mach == bfd_mach_sh4)
02359     return TRUE;
02360 
02361   /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
02362      instructions.  */
02363   if (dsp)
02364     {
02365       sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
02366       sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
02367     }
02368 
02369   /* Instructions should be aligned on 2 byte boundaries.  */
02370   if ((start & 1) == 1)
02371     ++start;
02372 
02373   /* Now look through the unaligned addresses.  */
02374   i = start;
02375   if ((i & 2) == 0)
02376     i += 2;
02377   for (; i < stop; i += 4)
02378     {
02379       unsigned int insn;
02380       const struct sh_opcode *op;
02381       unsigned int prev_insn = 0;
02382       const struct sh_opcode *prev_op = NULL;
02383 
02384       insn = bfd_get_16 (abfd, contents + i);
02385       op = sh_insn_info (insn);
02386       if (op == NULL
02387          || (op->flags & (LOAD | STORE)) == 0)
02388        continue;
02389 
02390       /* This is a load or store which is not on a four byte boundary.  */
02391 
02392       while (*plabel < label_end && **plabel < i)
02393        ++*plabel;
02394 
02395       if (i > start)
02396        {
02397          prev_insn = bfd_get_16 (abfd, contents + i - 2);
02398          /* If INSN is the field b of a parallel processing insn, it is not
02399             a load / store after all.  Note that the test here might mistake
02400             the field_b of a pcopy insn for the starting code of a parallel
02401             processing insn; this might miss a swapping opportunity, but at
02402             least we're on the safe side.  */
02403          if (dsp && (prev_insn & 0xfc00) == 0xf800)
02404            continue;
02405 
02406          /* Check if prev_insn is actually the field b of a parallel
02407             processing insn.  Again, this can give a spurious match
02408             after a pcopy.  */
02409          if (dsp && i - 2 > start)
02410            {
02411              unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
02412 
02413              if ((pprev_insn & 0xfc00) == 0xf800)
02414               prev_op = NULL;
02415              else
02416               prev_op = sh_insn_info (prev_insn);
02417            }
02418          else
02419            prev_op = sh_insn_info (prev_insn);
02420 
02421          /* If the load/store instruction is in a delay slot, we
02422             can't swap.  */
02423          if (prev_op == NULL
02424              || (prev_op->flags & DELAY) != 0)
02425            continue;
02426        }
02427       if (i > start
02428          && (*plabel >= label_end || **plabel != i)
02429          && prev_op != NULL
02430          && (prev_op->flags & (LOAD | STORE)) == 0
02431          && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
02432        {
02433          bfd_boolean ok;
02434 
02435          /* The load/store instruction does not have a label, and
02436             there is a previous instruction; PREV_INSN is not
02437             itself a load/store instruction, and PREV_INSN and
02438             INSN do not conflict.  */
02439 
02440          ok = TRUE;
02441 
02442          if (i >= start + 4)
02443            {
02444              unsigned int prev2_insn;
02445              const struct sh_opcode *prev2_op;
02446 
02447              prev2_insn = bfd_get_16 (abfd, contents + i - 4);
02448              prev2_op = sh_insn_info (prev2_insn);
02449 
02450              /* If the instruction before PREV_INSN has a delay
02451                slot--that is, PREV_INSN is in a delay slot--we
02452                can not swap.  */
02453              if (prev2_op == NULL
02454                 || (prev2_op->flags & DELAY) != 0)
02455               ok = FALSE;
02456 
02457              /* If the instruction before PREV_INSN is a load,
02458                and it sets a register which INSN uses, then
02459                putting INSN immediately after PREV_INSN will
02460                cause a pipeline bubble, so there is no point to
02461                making the swap.  */
02462              if (ok
02463                 && (prev2_op->flags & LOAD) != 0
02464                 && sh_load_use (prev2_insn, prev2_op, insn, op))
02465               ok = FALSE;
02466            }
02467 
02468          if (ok)
02469            {
02470              if (! (*swap) (abfd, sec, relocs, contents, i - 2))
02471               return FALSE;
02472              *pswapped = TRUE;
02473              continue;
02474            }
02475        }
02476 
02477       while (*plabel < label_end && **plabel < i + 2)
02478        ++*plabel;
02479 
02480       if (i + 2 < stop
02481          && (*plabel >= label_end || **plabel != i + 2))
02482        {
02483          unsigned int next_insn;
02484          const struct sh_opcode *next_op;
02485 
02486          /* There is an instruction after the load/store
02487             instruction, and it does not have a label.  */
02488          next_insn = bfd_get_16 (abfd, contents + i + 2);
02489          next_op = sh_insn_info (next_insn);
02490          if (next_op != NULL
02491              && (next_op->flags & (LOAD | STORE)) == 0
02492              && ! sh_insns_conflict (insn, op, next_insn, next_op))
02493            {
02494              bfd_boolean ok;
02495 
02496              /* NEXT_INSN is not itself a load/store instruction,
02497                and it does not conflict with INSN.  */
02498 
02499              ok = TRUE;
02500 
02501              /* If PREV_INSN is a load, and it sets a register
02502                which NEXT_INSN uses, then putting NEXT_INSN
02503                immediately after PREV_INSN will cause a pipeline
02504                bubble, so there is no reason to make this swap.  */
02505              if (prev_op != NULL
02506                 && (prev_op->flags & LOAD) != 0
02507                 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
02508               ok = FALSE;
02509 
02510              /* If INSN is a load, and it sets a register which
02511                the insn after NEXT_INSN uses, then doing the
02512                swap will cause a pipeline bubble, so there is no
02513                reason to make the swap.  However, if the insn
02514                after NEXT_INSN is itself a load or store
02515                instruction, then it is misaligned, so
02516                optimistically hope that it will be swapped
02517                itself, and just live with the pipeline bubble if
02518                it isn't.  */
02519              if (ok
02520                 && i + 4 < stop
02521                 && (op->flags & LOAD) != 0)
02522               {
02523                 unsigned int next2_insn;
02524                 const struct sh_opcode *next2_op;
02525 
02526                 next2_insn = bfd_get_16 (abfd, contents + i + 4);
02527                 next2_op = sh_insn_info (next2_insn);
02528                 if (next2_op == NULL
02529                     || ((next2_op->flags & (LOAD | STORE)) == 0
02530                        && sh_load_use (insn, op, next2_insn, next2_op)))
02531                   ok = FALSE;
02532               }
02533 
02534              if (ok)
02535               {
02536                 if (! (*swap) (abfd, sec, relocs, contents, i))
02537                   return FALSE;
02538                 *pswapped = TRUE;
02539                 continue;
02540               }
02541            }
02542        }
02543     }
02544 
02545   return TRUE;
02546 }
02547 #endif /* not COFF_IMAGE_WITH_PE */
02548 
02549 /* Look for loads and stores which we can align to four byte
02550    boundaries.  See the longer comment above sh_relax_section for why
02551    this is desirable.  This sets *PSWAPPED if some instruction was
02552    swapped.  */
02553 
02554 static bfd_boolean
02555 sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
02556      bfd *abfd;
02557      asection *sec;
02558      struct internal_reloc *internal_relocs;
02559      bfd_byte *contents;
02560      bfd_boolean *pswapped;
02561 {
02562   struct internal_reloc *irel, *irelend;
02563   bfd_vma *labels = NULL;
02564   bfd_vma *label, *label_end;
02565   bfd_size_type amt;
02566 
02567   *pswapped = FALSE;
02568 
02569   irelend = internal_relocs + sec->reloc_count;
02570 
02571   /* Get all the addresses with labels on them.  */
02572   amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
02573   labels = (bfd_vma *) bfd_malloc (amt);
02574   if (labels == NULL)
02575     goto error_return;
02576   label_end = labels;
02577   for (irel = internal_relocs; irel < irelend; irel++)
02578     {
02579       if (irel->r_type == R_SH_LABEL)
02580        {
02581          *label_end = irel->r_vaddr - sec->vma;
02582          ++label_end;
02583        }
02584     }
02585 
02586   /* Note that the assembler currently always outputs relocs in
02587      address order.  If that ever changes, this code will need to sort
02588      the label values and the relocs.  */
02589 
02590   label = labels;
02591 
02592   for (irel = internal_relocs; irel < irelend; irel++)
02593     {
02594       bfd_vma start, stop;
02595 
02596       if (irel->r_type != R_SH_CODE)
02597        continue;
02598 
02599       start = irel->r_vaddr - sec->vma;
02600 
02601       for (irel++; irel < irelend; irel++)
02602        if (irel->r_type == R_SH_DATA)
02603          break;
02604       if (irel < irelend)
02605        stop = irel->r_vaddr - sec->vma;
02606       else
02607        stop = sec->size;
02608 
02609       if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
02610                                  (PTR) internal_relocs, &label,
02611                                  label_end, start, stop, pswapped))
02612        goto error_return;
02613     }
02614 
02615   free (labels);
02616 
02617   return TRUE;
02618 
02619  error_return:
02620   if (labels != NULL)
02621     free (labels);
02622   return FALSE;
02623 }
02624 
02625 /* Swap two SH instructions.  */
02626 
02627 static bfd_boolean
02628 sh_swap_insns (abfd, sec, relocs, contents, addr)
02629      bfd *abfd;
02630      asection *sec;
02631      PTR relocs;
02632      bfd_byte *contents;
02633      bfd_vma addr;
02634 {
02635   struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
02636   unsigned short i1, i2;
02637   struct internal_reloc *irel, *irelend;
02638 
02639   /* Swap the instructions themselves.  */
02640   i1 = bfd_get_16 (abfd, contents + addr);
02641   i2 = bfd_get_16 (abfd, contents + addr + 2);
02642   bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
02643   bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
02644 
02645   /* Adjust all reloc addresses.  */
02646   irelend = internal_relocs + sec->reloc_count;
02647   for (irel = internal_relocs; irel < irelend; irel++)
02648     {
02649       int type, add;
02650 
02651       /* There are a few special types of relocs that we don't want to
02652          adjust.  These relocs do not apply to the instruction itself,
02653          but are only associated with the address.  */
02654       type = irel->r_type;
02655       if (type == R_SH_ALIGN
02656          || type == R_SH_CODE
02657          || type == R_SH_DATA
02658          || type == R_SH_LABEL)
02659        continue;
02660 
02661       /* If an R_SH_USES reloc points to one of the addresses being
02662          swapped, we must adjust it.  It would be incorrect to do this
02663          for a jump, though, since we want to execute both
02664          instructions after the jump.  (We have avoided swapping
02665          around a label, so the jump will not wind up executing an
02666          instruction it shouldn't).  */
02667       if (type == R_SH_USES)
02668        {
02669          bfd_vma off;
02670 
02671          off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
02672          if (off == addr)
02673            irel->r_offset += 2;
02674          else if (off == addr + 2)
02675            irel->r_offset -= 2;
02676        }
02677 
02678       if (irel->r_vaddr - sec->vma == addr)
02679        {
02680          irel->r_vaddr += 2;
02681          add = -2;
02682        }
02683       else if (irel->r_vaddr - sec->vma == addr + 2)
02684        {
02685          irel->r_vaddr -= 2;
02686          add = 2;
02687        }
02688       else
02689        add = 0;
02690 
02691       if (add != 0)
02692        {
02693          bfd_byte *loc;
02694          unsigned short insn, oinsn;
02695          bfd_boolean overflow;
02696 
02697          loc = contents + irel->r_vaddr - sec->vma;
02698          overflow = FALSE;
02699          switch (type)
02700            {
02701            default:
02702              break;
02703 
02704            case R_SH_PCDISP8BY2:
02705            case R_SH_PCRELIMM8BY2:
02706              insn = bfd_get_16 (abfd, loc);
02707              oinsn = insn;
02708              insn += add / 2;
02709              if ((oinsn & 0xff00) != (insn & 0xff00))
02710               overflow = TRUE;
02711              bfd_put_16 (abfd, (bfd_vma) insn, loc);
02712              break;
02713 
02714            case R_SH_PCDISP:
02715              insn = bfd_get_16 (abfd, loc);
02716              oinsn = insn;
02717              insn += add / 2;
02718              if ((oinsn & 0xf000) != (insn & 0xf000))
02719               overflow = TRUE;
02720              bfd_put_16 (abfd, (bfd_vma) insn, loc);
02721              break;
02722 
02723            case R_SH_PCRELIMM8BY4:
02724              /* This reloc ignores the least significant 3 bits of
02725                  the program counter before adding in the offset.
02726                  This means that if ADDR is at an even address, the
02727                  swap will not affect the offset.  If ADDR is an at an
02728                  odd address, then the instruction will be crossing a
02729                  four byte boundary, and must be adjusted.  */
02730              if ((addr & 3) != 0)
02731               {
02732                 insn = bfd_get_16 (abfd, loc);
02733                 oinsn = insn;
02734                 insn += add / 2;
02735                 if ((oinsn & 0xff00) != (insn & 0xff00))
02736                   overflow = TRUE;
02737                 bfd_put_16 (abfd, (bfd_vma) insn, loc);
02738               }
02739 
02740              break;
02741            }
02742 
02743          if (overflow)
02744            {
02745              ((*_bfd_error_handler)
02746               ("%B: 0x%lx: fatal: reloc overflow while relaxing",
02747               abfd, (unsigned long) irel->r_vaddr));
02748              bfd_set_error (bfd_error_bad_value);
02749              return FALSE;
02750            }
02751        }
02752     }
02753 
02754   return TRUE;
02755 }
02756 
02757 /* This is a modification of _bfd_coff_generic_relocate_section, which
02758    will handle SH relaxing.  */
02759 
02760 static bfd_boolean
02761 sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
02762                    relocs, syms, sections)
02763      bfd *output_bfd ATTRIBUTE_UNUSED;
02764      struct bfd_link_info *info;
02765      bfd *input_bfd;
02766      asection *input_section;
02767      bfd_byte *contents;
02768      struct internal_reloc *relocs;
02769      struct internal_syment *syms;
02770      asection **sections;
02771 {
02772   struct internal_reloc *rel;
02773   struct internal_reloc *relend;
02774 
02775   rel = relocs;
02776   relend = rel + input_section->reloc_count;
02777   for (; rel < relend; rel++)
02778     {
02779       long symndx;
02780       struct coff_link_hash_entry *h;
02781       struct internal_syment *sym;
02782       bfd_vma addend;
02783       bfd_vma val;
02784       reloc_howto_type *howto;
02785       bfd_reloc_status_type rstat;
02786 
02787       /* Almost all relocs have to do with relaxing.  If any work must
02788          be done for them, it has been done in sh_relax_section.  */
02789       if (rel->r_type != R_SH_IMM32
02790 #ifdef COFF_WITH_PE
02791          && rel->r_type != R_SH_IMM32CE
02792          && rel->r_type != R_SH_IMAGEBASE
02793 #endif
02794          && rel->r_type != R_SH_PCDISP)
02795        continue;
02796 
02797       symndx = rel->r_symndx;
02798 
02799       if (symndx == -1)
02800        {
02801          h = NULL;
02802          sym = NULL;
02803        }
02804       else
02805        {
02806          if (symndx < 0
02807              || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
02808            {
02809              (*_bfd_error_handler)
02810               ("%B: illegal symbol index %ld in relocs",
02811                input_bfd, symndx);
02812              bfd_set_error (bfd_error_bad_value);
02813              return FALSE;
02814            }
02815          h = obj_coff_sym_hashes (input_bfd)[symndx];
02816          sym = syms + symndx;
02817        }
02818 
02819       if (sym != NULL && sym->n_scnum != 0)
02820        addend = - sym->n_value;
02821       else
02822        addend = 0;
02823 
02824       if (rel->r_type == R_SH_PCDISP)
02825        addend -= 4;
02826 
02827       if (rel->r_type >= SH_COFF_HOWTO_COUNT)
02828        howto = NULL;
02829       else
02830        howto = &sh_coff_howtos[rel->r_type];
02831 
02832       if (howto == NULL)
02833        {
02834          bfd_set_error (bfd_error_bad_value);
02835          return FALSE;
02836        }
02837 
02838 #ifdef COFF_WITH_PE
02839       if (rel->r_type == R_SH_IMAGEBASE)
02840        addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
02841 #endif
02842 
02843       val = 0;
02844 
02845       if (h == NULL)
02846        {
02847          asection *sec;
02848 
02849          /* There is nothing to do for an internal PCDISP reloc.  */
02850          if (rel->r_type == R_SH_PCDISP)
02851            continue;
02852 
02853          if (symndx == -1)
02854            {
02855              sec = bfd_abs_section_ptr;
02856              val = 0;
02857            }
02858          else
02859            {
02860              sec = sections[symndx];
02861               val = (sec->output_section->vma
02862                    + sec->output_offset
02863                    + sym->n_value
02864                    - sec->vma);
02865            }
02866        }
02867       else
02868        {
02869          if (h->root.type == bfd_link_hash_defined
02870              || h->root.type == bfd_link_hash_defweak)
02871            {
02872              asection *sec;
02873 
02874              sec = h->root.u.def.section;
02875              val = (h->root.u.def.value
02876                    + sec->output_section->vma
02877                    + sec->output_offset);
02878            }
02879          else if (! info->relocatable)
02880            {
02881              if (! ((*info->callbacks->undefined_symbol)
02882                    (info, h->root.root.string, input_bfd, input_section,
02883                     rel->r_vaddr - input_section->vma, TRUE)))
02884               return FALSE;
02885            }
02886        }
02887 
02888       rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
02889                                    contents,
02890                                    rel->r_vaddr - input_section->vma,
02891                                    val, addend);
02892 
02893       switch (rstat)
02894        {
02895        default:
02896          abort ();
02897        case bfd_reloc_ok:
02898          break;
02899        case bfd_reloc_overflow:
02900          {
02901            const char *name;
02902            char buf[SYMNMLEN + 1];
02903 
02904            if (symndx == -1)
02905              name = "*ABS*";
02906            else if (h != NULL)
02907              name = NULL;
02908            else if (sym->_n._n_n._n_zeroes == 0
02909                    && sym->_n._n_n._n_offset != 0)
02910              name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
02911            else
02912              {
02913               strncpy (buf, sym->_n._n_name, SYMNMLEN);
02914               buf[SYMNMLEN] = '\0';
02915               name = buf;
02916              }
02917 
02918            if (! ((*info->callbacks->reloc_overflow)
02919                  (info, (h ? &h->root : NULL), name, howto->name,
02920                   (bfd_vma) 0, input_bfd, input_section,
02921                   rel->r_vaddr - input_section->vma)))
02922              return FALSE;
02923          }
02924        }
02925     }
02926 
02927   return TRUE;
02928 }
02929 
02930 /* This is a version of bfd_generic_get_relocated_section_contents
02931    which uses sh_relocate_section.  */
02932 
02933 static bfd_byte *
02934 sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
02935                                    data, relocatable, symbols)
02936      bfd *output_bfd;
02937      struct bfd_link_info *link_info;
02938      struct bfd_link_order *link_order;
02939      bfd_byte *data;
02940      bfd_boolean relocatable;
02941      asymbol **symbols;
02942 {
02943   asection *input_section = link_order->u.indirect.section;
02944   bfd *input_bfd = input_section->owner;
02945   asection **sections = NULL;
02946   struct internal_reloc *internal_relocs = NULL;
02947   struct internal_syment *internal_syms = NULL;
02948 
02949   /* We only need to handle the case of relaxing, or of having a
02950      particular set of section contents, specially.  */
02951   if (relocatable
02952       || coff_section_data (input_bfd, input_section) == NULL
02953       || coff_section_data (input_bfd, input_section)->contents == NULL)
02954     return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
02955                                                  link_order, data,
02956                                                  relocatable,
02957                                                  symbols);
02958 
02959   memcpy (data, coff_section_data (input_bfd, input_section)->contents,
02960          (size_t) input_section->size);
02961 
02962   if ((input_section->flags & SEC_RELOC) != 0
02963       && input_section->reloc_count > 0)
02964     {
02965       bfd_size_type symesz = bfd_coff_symesz (input_bfd);
02966       bfd_byte *esym, *esymend;
02967       struct internal_syment *isymp;
02968       asection **secpp;
02969       bfd_size_type amt;
02970 
02971       if (! _bfd_coff_get_external_symbols (input_bfd))
02972        goto error_return;
02973 
02974       internal_relocs = (_bfd_coff_read_internal_relocs
02975                       (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
02976                        FALSE, (struct internal_reloc *) NULL));
02977       if (internal_relocs == NULL)
02978        goto error_return;
02979 
02980       amt = obj_raw_syment_count (input_bfd);
02981       amt *= sizeof (struct internal_syment);
02982       internal_syms = (struct internal_syment *) bfd_malloc (amt);
02983       if (internal_syms == NULL)
02984        goto error_return;
02985 
02986       amt = obj_raw_syment_count (input_bfd);
02987       amt *= sizeof (asection *);
02988       sections = (asection **) bfd_malloc (amt);
02989       if (sections == NULL)
02990        goto error_return;
02991 
02992       isymp = internal_syms;
02993       secpp = sections;
02994       esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
02995       esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
02996       while (esym < esymend)
02997        {
02998          bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
02999 
03000          if (isymp->n_scnum != 0)
03001            *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
03002          else
03003            {
03004              if (isymp->n_value == 0)
03005               *secpp = bfd_und_section_ptr;
03006              else
03007               *secpp = bfd_com_section_ptr;
03008            }
03009 
03010          esym += (isymp->n_numaux + 1) * symesz;
03011          secpp += isymp->n_numaux + 1;
03012          isymp += isymp->n_numaux + 1;
03013        }
03014 
03015       if (! sh_relocate_section (output_bfd, link_info, input_bfd,
03016                              input_section, data, internal_relocs,
03017                              internal_syms, sections))
03018        goto error_return;
03019 
03020       free (sections);
03021       sections = NULL;
03022       free (internal_syms);
03023       internal_syms = NULL;
03024       free (internal_relocs);
03025       internal_relocs = NULL;
03026     }
03027 
03028   return data;
03029 
03030  error_return:
03031   if (internal_relocs != NULL)
03032     free (internal_relocs);
03033   if (internal_syms != NULL)
03034     free (internal_syms);
03035   if (sections != NULL)
03036     free (sections);
03037   return NULL;
03038 }
03039 
03040 /* The target vectors.  */
03041 
03042 #ifndef TARGET_SHL_SYM
03043 CREATE_BIG_COFF_TARGET_VEC (shcoff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
03044 #endif
03045 
03046 #ifdef TARGET_SHL_SYM
03047 #define TARGET_SYM TARGET_SHL_SYM
03048 #else
03049 #define TARGET_SYM shlcoff_vec
03050 #endif
03051 
03052 #ifndef TARGET_SHL_NAME
03053 #define TARGET_SHL_NAME "coff-shl"
03054 #endif
03055 
03056 #ifdef COFF_WITH_PE
03057 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
03058                             SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
03059 #else
03060 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
03061                             0, '_', NULL, COFF_SWAP_TABLE)
03062 #endif
03063 
03064 #ifndef TARGET_SHL_SYM
03065 static const bfd_target * coff_small_object_p PARAMS ((bfd *));
03066 static bfd_boolean coff_small_new_section_hook PARAMS ((bfd *, asection *));
03067 /* Some people want versions of the SH COFF target which do not align
03068    to 16 byte boundaries.  We implement that by adding a couple of new
03069    target vectors.  These are just like the ones above, but they
03070    change the default section alignment.  To generate them in the
03071    assembler, use -small.  To use them in the linker, use -b
03072    coff-sh{l}-small and -oformat coff-sh{l}-small.
03073 
03074    Yes, this is a horrible hack.  A general solution for setting
03075    section alignment in COFF is rather complex.  ELF handles this
03076    correctly.  */
03077 
03078 /* Only recognize the small versions if the target was not defaulted.
03079    Otherwise we won't recognize the non default endianness.  */
03080 
03081 static const bfd_target *
03082 coff_small_object_p (abfd)
03083      bfd *abfd;
03084 {
03085   if (abfd->target_defaulted)
03086     {
03087       bfd_set_error (bfd_error_wrong_format);
03088       return NULL;
03089     }
03090   return coff_object_p (abfd);
03091 }
03092 
03093 /* Set the section alignment for the small versions.  */
03094 
03095 static bfd_boolean
03096 coff_small_new_section_hook (abfd, section)
03097      bfd *abfd;
03098      asection *section;
03099 {
03100   if (! coff_new_section_hook (abfd, section))
03101     return FALSE;
03102 
03103   /* We must align to at least a four byte boundary, because longword
03104      accesses must be on a four byte boundary.  */
03105   if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
03106     section->alignment_power = 2;
03107 
03108   return TRUE;
03109 }
03110 
03111 /* This is copied from bfd_coff_std_swap_table so that we can change
03112    the default section alignment power.  */
03113 
03114 static const bfd_coff_backend_data bfd_coff_small_swap_table =
03115 {
03116   coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
03117   coff_swap_aux_out, coff_swap_sym_out,
03118   coff_swap_lineno_out, coff_swap_reloc_out,
03119   coff_swap_filehdr_out, coff_swap_aouthdr_out,
03120   coff_swap_scnhdr_out,
03121   FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
03122 #ifdef COFF_LONG_FILENAMES
03123   TRUE,
03124 #else
03125   FALSE,
03126 #endif
03127 #ifdef COFF_LONG_SECTION_NAMES
03128   TRUE,
03129 #else
03130   FALSE,
03131 #endif
03132   2,
03133 #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
03134   TRUE,
03135 #else
03136   FALSE,
03137 #endif
03138 #ifdef COFF_DEBUG_STRING_WIDE_PREFIX
03139   4,
03140 #else
03141   2,
03142 #endif
03143   coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
03144   coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
03145   coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
03146   coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
03147   coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
03148   coff_classify_symbol, coff_compute_section_file_positions,
03149   coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
03150   coff_adjust_symndx, coff_link_add_one_symbol,
03151   coff_link_output_has_begun, coff_final_link_postscript
03152 };
03153 
03154 #define coff_small_close_and_cleanup \
03155   coff_close_and_cleanup
03156 #define coff_small_bfd_free_cached_info \
03157   coff_bfd_free_cached_info
03158 #define coff_small_get_section_contents \
03159   coff_get_section_contents
03160 #define coff_small_get_section_contents_in_window \
03161   coff_get_section_contents_in_window
03162 
03163 extern const bfd_target shlcoff_small_vec;
03164 
03165 const bfd_target shcoff_small_vec =
03166 {
03167   "coff-sh-small",          /* name */
03168   bfd_target_coff_flavour,
03169   BFD_ENDIAN_BIG,           /* data byte order is big */
03170   BFD_ENDIAN_BIG,           /* header byte order is big */
03171 
03172   (HAS_RELOC | EXEC_P |            /* object flags */
03173    HAS_LINENO | HAS_DEBUG |
03174    HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
03175 
03176   (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
03177   '_',                      /* leading symbol underscore */
03178   '/',                      /* ar_pad_char */
03179   15,                       /* ar_max_namelen */
03180   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
03181   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
03182   bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
03183   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
03184   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
03185   bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
03186 
03187   {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
03188      bfd_generic_archive_p, _bfd_dummy_target},
03189   {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
03190      bfd_false},
03191   {bfd_false, coff_write_object_contents, /* bfd_write_contents */
03192      _bfd_write_archive_contents, bfd_false},
03193 
03194   BFD_JUMP_TABLE_GENERIC (coff_small),
03195   BFD_JUMP_TABLE_COPY (coff),
03196   BFD_JUMP_TABLE_CORE (_bfd_nocore),
03197   BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
03198   BFD_JUMP_TABLE_SYMBOLS (coff),
03199   BFD_JUMP_TABLE_RELOCS (coff),
03200   BFD_JUMP_TABLE_WRITE (coff),
03201   BFD_JUMP_TABLE_LINK (coff),
03202   BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
03203 
03204   & shlcoff_small_vec,
03205 
03206   (PTR) &bfd_coff_small_swap_table
03207 };
03208 
03209 const bfd_target shlcoff_small_vec =
03210 {
03211   "coff-shl-small",         /* name */
03212   bfd_target_coff_flavour,
03213   BFD_ENDIAN_LITTLE,        /* data byte order is little */
03214   BFD_ENDIAN_LITTLE,        /* header byte order is little endian too*/
03215 
03216   (HAS_RELOC | EXEC_P |            /* object flags */
03217    HAS_LINENO | HAS_DEBUG |
03218    HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
03219 
03220   (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
03221   '_',                      /* leading symbol underscore */
03222   '/',                      /* ar_pad_char */
03223   15,                       /* ar_max_namelen */
03224   bfd_getl64, bfd_getl_signed_64, bfd_putl64,
03225   bfd_getl32, bfd_getl_signed_32, bfd_putl32,
03226   bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
03227   bfd_getl64, bfd_getl_signed_64, bfd_putl64,
03228   bfd_getl32, bfd_getl_signed_32, bfd_putl32,
03229   bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
03230 
03231   {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
03232      bfd_generic_archive_p, _bfd_dummy_target},
03233   {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
03234      bfd_false},
03235   {bfd_false, coff_write_object_contents, /* bfd_write_contents */
03236      _bfd_write_archive_contents, bfd_false},
03237 
03238   BFD_JUMP_TABLE_GENERIC (coff_small),
03239   BFD_JUMP_TABLE_COPY (coff),
03240   BFD_JUMP_TABLE_CORE (_bfd_nocore),
03241   BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
03242   BFD_JUMP_TABLE_SYMBOLS (coff),
03243   BFD_JUMP_TABLE_RELOCS (coff),
03244   BFD_JUMP_TABLE_WRITE (coff),
03245   BFD_JUMP_TABLE_LINK (coff),
03246   BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
03247 
03248   & shcoff_small_vec,
03249 
03250   (PTR) &bfd_coff_small_swap_table
03251 };
03252 #endif