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cell-binutils  2.17cvs20070401
Classes | Defines | Functions | Variables
coff-sh.c File Reference
#include "bfd.h"
#include "sysdep.h"
#include "libiberty.h"
#include "libbfd.h"
#include "bfdlink.h"
#include "coff/sh.h"
#include "coff/internal.h"
#include "libcoff.h"
#include "coffcode.h"
#include "coff/pe.h"
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Classes

struct  shcoff_reloc_map
struct  sh_major_opcode
struct  sh_minor_opcode
struct  sh_opcode

Defines

#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER   4
#define COFF_LONG_FILENAMES
#define SH_COFF_HOWTO_COUNT   (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
#define BADMAG(x)   SHBADMAG(x)
#define SH   1
#define __A_MAGIC_SET__
#define SWAP_IN_RELOC_OFFSET   H_GET_32
#define SWAP_OUT_RELOC_OFFSET   H_PUT_32
#define SWAP_OUT_RELOC_EXTRA(abfd, src, dst)
#define coff_bfd_reloc_type_lookup   sh_coff_reloc_type_lookup
#define coff_bfd_reloc_name_lookup   sh_coff_reloc_name_lookup
#define RTYPE2HOWTO(relent, internal)
#define CALC_ADDEND(abfd, ptr, reloc, cache_ptr)
#define coff_bfd_merge_private_bfd_data   _bfd_generic_verify_endian_match
#define coff_bfd_relax_section   sh_relax_section
#define coff_relocate_section   sh_relocate_section
#define coff_bfd_get_relocated_section_contents   sh_coff_get_relocated_section_contents
#define NOP_OPCODE   (0x0009)
#define LOAD   (0x1)
#define STORE   (0x2)
#define BRANCH   (0x4)
#define DELAY   (0x8)
#define USES1   (0x10)
#define USES1_REG(x)   ((x & 0x0f00) >> 8)
#define USES2   (0x20)
#define USES2_REG(x)   ((x & 0x00f0) >> 4)
#define USESR0   (0x40)
#define SETS1   (0x80)
#define SETS1_REG(x)   ((x & 0x0f00) >> 8)
#define SETS2   (0x100)
#define SETS2_REG(x)   ((x & 0x00f0) >> 4)
#define SETSR0   (0x200)
#define SETSSP   (0x400)
#define USESSP   (0x800)
#define USESF1   (0x1000)
#define USESF1_REG(x)   ((x & 0x0f00) >> 8)
#define USESF2   (0x2000)
#define USESF2_REG(x)   ((x & 0x00f0) >> 4)
#define USESF0   (0x4000)
#define SETSF1   (0x8000)
#define SETSF1_REG(x)   ((x & 0x0f00) >> 8)
#define USESAS   (0x10000)
#define USESAS_REG(x)   (((((x) >> 8) - 2) & 3) + 2)
#define USESR8   (0x20000)
#define SETSAS   (0x40000)
#define SETSAS_REG(x)   USESAS_REG (x)
#define MAP(a)   a, sizeof a / sizeof a[0]
#define TARGET_SYM   shlcoff_vec
#define TARGET_SHL_NAME   "coff-shl"
#define coff_small_close_and_cleanup   coff_close_and_cleanup
#define coff_small_bfd_free_cached_info   coff_bfd_free_cached_info
#define coff_small_get_section_contents   coff_get_section_contents
#define coff_small_get_section_contents_in_window   coff_get_section_contents_in_window

Functions

static bfd_reloc_status_type
sh_reloc 
PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **))
static long get_symbol_value PARAMS ((asymbol *))
static bfd_boolean sh_relax_section PARAMS ((bfd *, asection *, struct bfd_link_info *, bfd_boolean *))
static bfd_boolean
sh_relax_delete_bytes 
PARAMS ((bfd *, asection *, bfd_vma, int))
static struct sh_opcode
*sh_insn_info 
PARAMS ((unsigned int))
static bfd_boolean sh_align_loads PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, bfd_boolean *))
static bfd_boolean sh_swap_insns PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma))
static bfd_boolean
sh_relocate_section 
PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *, struct internal_reloc *, struct internal_syment *, asection **))
static bfd_byte
*sh_coff_get_relocated_section_contents 
PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *, bfd_byte *, bfd_boolean, asymbol **))
static reloc_howto_type
*sh_coff_reloc_type_lookup 
PARAMS ((bfd *, bfd_reloc_code_real_type))
static long get_symbol_value (asymbol *symbol)
static reloc_howto_type * sh_coff_reloc_type_lookup (abfd, bfd_reloc_code_real_type code)
static reloc_howto_type * sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED, const char *r_name)
static bfd_reloc_status_type sh_reloc (bfd *abfd, arelent *reloc_entry, asymbol *symbol_in, PTR data, asection *input_section, bfd *output_bfd, error_message)
static bfd_boolean sh_relax_section (bfd *abfd, asection *sec, struct bfd_link_info *link_info, bfd_boolean *again)
static bfd_boolean sh_relax_delete_bytes (bfd *abfd, asection *sec, bfd_vma addr, int count)
static bfd_boolean sh_insn_uses_reg PARAMS ((unsigned int, const struct sh_opcode *, unsigned int))
static bfd_boolean
sh_insns_conflict 
PARAMS ((unsigned int, const struct sh_opcode *, unsigned int, const struct sh_opcode *))
static struct sh_opcodesh_insn_info (unsigned int insn)
static bfd_boolean sh_insn_uses_or_sets_reg (unsigned int insn, const struct sh_opcode *op, unsigned int reg)
static bfd_boolean sh_insn_uses_reg (unsigned int insn, const struct sh_opcode *op, unsigned int reg)
static bfd_boolean sh_insn_sets_reg (unsigned int insn, const struct sh_opcode *op, unsigned int reg)
static bfd_boolean sh_insn_uses_or_sets_freg (unsigned int insn, const struct sh_opcode *op, unsigned int reg)
static bfd_boolean sh_insn_uses_freg (unsigned int insn, const struct sh_opcode *op, unsigned int freg)
static bfd_boolean sh_insn_sets_freg (unsigned int insn, const struct sh_opcode *op, unsigned int freg)
static bfd_boolean sh_insns_conflict (unsigned int i1, const struct sh_opcode *op1, unsigned int i2, const struct sh_opcode *op2)
static bfd_boolean sh_load_use (unsigned int i1, const struct sh_opcode *op1, unsigned int i2, const struct sh_opcode *op2)
bfd_boolean _bfd_sh_align_load_span (bfd *abfd, bfd_boolean *asection *, bfd_boolean *bfd_byte *, bfd_boolean *swap, PTR relocs, bfd_vma **plabel, bfd_vma *label_end, bfd_vma start, bfd_vma stop, bfd_boolean *pswapped)
static bfd_boolean sh_align_loads (bfd *abfd, asection *sec, struct internal_reloc *internal_relocs, bfd_byte *contents, bfd_boolean *pswapped)
static bfd_boolean sh_swap_insns (bfd *abfd, asection *sec, PTR relocs, bfd_byte *contents, bfd_vma addr)
static bfd_boolean sh_relocate_section (output_bfd, struct bfd_link_info *info, bfd *input_bfd, asection *input_section, bfd_byte *contents, struct internal_reloc *relocs, struct internal_syment *syms, asection **sections)
static bfd_bytesh_coff_get_relocated_section_contents (bfd *output_bfd, struct bfd_link_info *link_info, struct bfd_link_order *link_order, bfd_byte *data, bfd_boolean relocatable, asymbol **symbols)
 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
static bfd_boolean coff_small_new_section_hook (bfd *abfd, asection *section)

Variables

static reloc_howto_type sh_coff_howtos []
static struct shcoff_reloc_map []
static struct sh_opcode []
static struct sh_minor_opcode []
static struct sh_major_opcode []
static const bfd_coff_backend_data bfd_coff_small_swap_table
const bfd_target shlcoff_small_vec
const bfd_target shcoff_small_vec

Class Documentation

struct shcoff_reloc_map

Definition at line 471 of file coff-sh.c.

Class Members
bfd_reloc_code_real_type bfd_reloc_val
unsigned char shcoff_reloc_val
struct sh_major_opcode

Definition at line 1512 of file coff-sh.c.

Collaboration diagram for sh_major_opcode:
Class Members
unsigned short count
struct sh_minor_opcode * minor_opcodes
struct sh_minor_opcode

Definition at line 1525 of file coff-sh.c.

Collaboration diagram for sh_minor_opcode:
Class Members
unsigned short count
unsigned short mask
struct sh_opcode * opcodes
struct sh_opcode

Definition at line 1538 of file coff-sh.c.

Class Members
unsigned long flags
unsigned short opcode

Define Documentation

#define __A_MAGIC_SET__

Definition at line 379 of file coff-sh.c.

#define BADMAG (   x)    SHBADMAG(x)

Definition at line 373 of file coff-sh.c.

#define BRANCH   (0x4)

Definition at line 1556 of file coff-sh.c.

#define CALC_ADDEND (   abfd,
  ptr,
  reloc,
  cache_ptr 
)
Value:
{                                                             \
    coff_symbol_type *coffsym = (coff_symbol_type *) NULL;      \
    if (ptr && bfd_asymbol_bfd (ptr) != abfd)                   \
      coffsym = (obj_symbols (abfd)                             \
                 + (cache_ptr->sym_ptr_ptr - symbols));         \
    else if (ptr)                                               \
      coffsym = coff_symbol_from (abfd, ptr);                   \
    if (coffsym != (coff_symbol_type *) NULL                    \
        && coffsym->native->u.syment.n_scnum == 0)              \
      cache_ptr->addend = 0;                                    \
    else if (ptr && bfd_asymbol_bfd (ptr) == abfd               \
             && ptr->section != (asection *) NULL)              \
      cache_ptr->addend = - (ptr->section->vma + ptr->value);   \
    else                                                        \
      cache_ptr->addend = 0;                                    \
    if ((reloc).r_type == R_SH_SWITCH8                         \
       || (reloc).r_type == R_SH_SWITCH16               \
       || (reloc).r_type == R_SH_SWITCH32               \
       || (reloc).r_type == R_SH_USES                          \
       || (reloc).r_type == R_SH_COUNT                         \
       || (reloc).r_type == R_SH_ALIGN)                 \
      cache_ptr->addend = (reloc).r_offset;                    \
  }

Definition at line 539 of file coff-sh.c.

Definition at line 660 of file coff-sh.c.

Definition at line 650 of file coff-sh.c.

Definition at line 653 of file coff-sh.c.

Definition at line 497 of file coff-sh.c.

Definition at line 496 of file coff-sh.c.

Definition at line 76 of file coff-sh.c.

Definition at line 85 of file coff-sh.c.

Definition at line 656 of file coff-sh.c.

Definition at line 3156 of file coff-sh.c.

Definition at line 3154 of file coff-sh.c.

Definition at line 3158 of file coff-sh.c.

Definition at line 3160 of file coff-sh.c.

#define DELAY   (0x8)

Definition at line 1559 of file coff-sh.c.

CODE data LOAD other c LOAD   (0x1)

Definition at line 1550 of file coff-sh.c.

#define MAP (   a)    a, sizeof a / sizeof a[0]

Definition at line 1617 of file coff-sh.c.

#define NOP_OPCODE   (0x0009)
#define RTYPE2HOWTO (   relent,
  internal 
)
Value:
((relent)->howto =                        \
   ((internal)->r_type < SH_COFF_HOWTO_COUNT     \
    ? &sh_coff_howtos[(internal)->r_type] \
    : (reloc_howto_type *) NULL))

Definition at line 531 of file coff-sh.c.

#define SETS1   (0x80)

Definition at line 1576 of file coff-sh.c.

#define SETS1_REG (   x)    ((x & 0x0f00) >> 8)

Definition at line 1577 of file coff-sh.c.

#define SETS2   (0x100)

Definition at line 1581 of file coff-sh.c.

#define SETS2_REG (   x)    ((x & 0x00f0) >> 4)

Definition at line 1582 of file coff-sh.c.

#define SETSAS   (0x40000)

Definition at line 1614 of file coff-sh.c.

#define SETSAS_REG (   x)    USESAS_REG (x)

Definition at line 1615 of file coff-sh.c.

#define SETSF1   (0x8000)

Definition at line 1608 of file coff-sh.c.

#define SETSF1_REG (   x)    ((x & 0x0f00) >> 8)

Definition at line 1609 of file coff-sh.c.

#define SETSR0   (0x200)

Definition at line 1585 of file coff-sh.c.

#define SETSSP   (0x400)

Definition at line 1588 of file coff-sh.c.

#define SH   1

Definition at line 376 of file coff-sh.c.

#define SH_COFF_HOWTO_COUNT   (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])

Definition at line 370 of file coff-sh.c.

#define STORE   (0x2)

Definition at line 1553 of file coff-sh.c.

Definition at line 383 of file coff-sh.c.

#define SWAP_OUT_RELOC_EXTRA (   abfd,
  src,
  dst 
)
Value:
do                                        \
    {                                     \
      dst->r_stuff[0] = 'S';                     \
      dst->r_stuff[1] = 'C';                     \
    }                                     \
  while (0)

Definition at line 387 of file coff-sh.c.

Definition at line 384 of file coff-sh.c.

#define TARGET_SHL_NAME   "coff-shl"

Definition at line 3053 of file coff-sh.c.

#define TARGET_SYM   shlcoff_vec

Definition at line 3049 of file coff-sh.c.

#define USES1   (0x10)

Definition at line 1563 of file coff-sh.c.

#define USES1_REG (   x)    ((x & 0x0f00) >> 8)

Definition at line 1564 of file coff-sh.c.

#define USES2   (0x20)

Definition at line 1568 of file coff-sh.c.

#define USES2_REG (   x)    ((x & 0x00f0) >> 4)

Definition at line 1569 of file coff-sh.c.

#define USESAS   (0x10000)

Definition at line 1611 of file coff-sh.c.

#define USESAS_REG (   x)    (((((x) >> 8) - 2) & 3) + 2)

Definition at line 1612 of file coff-sh.c.

#define USESF0   (0x4000)

Definition at line 1604 of file coff-sh.c.

#define USESF1   (0x1000)

Definition at line 1595 of file coff-sh.c.

#define USESF1_REG (   x)    ((x & 0x0f00) >> 8)

Definition at line 1596 of file coff-sh.c.

#define USESF2   (0x2000)

Definition at line 1600 of file coff-sh.c.

#define USESF2_REG (   x)    ((x & 0x00f0) >> 4)

Definition at line 1601 of file coff-sh.c.

#define USESR0   (0x40)

Definition at line 1572 of file coff-sh.c.

#define USESR8   (0x20000)

Definition at line 1613 of file coff-sh.c.

#define USESSP   (0x800)

Definition at line 1591 of file coff-sh.c.


Function Documentation

bfd_boolean _bfd_sh_align_load_span ( bfd abfd,
bfd_boolean asection *,
bfd_boolean bfd_byte *,
bfd_boolean swap,
PTR  relocs,
bfd_vma **  plabel,
bfd_vma label_end,
bfd_vma  start,
bfd_vma  stop,
bfd_boolean pswapped 
)

Definition at line 2338 of file coff-sh.c.

{
  int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
            || abfd->arch_info->mach == bfd_mach_sh3_dsp);
  bfd_vma i;

  /* The SH4 has a Harvard architecture, hence aligning loads is not
     desirable.  In fact, it is counter-productive, since it interferes
     with the schedules generated by the compiler.  */
  if (abfd->arch_info->mach == bfd_mach_sh4)
    return TRUE;

  /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
     instructions.  */
  if (dsp)
    {
      sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
      sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef;
    }

  /* Instructions should be aligned on 2 byte boundaries.  */
  if ((start & 1) == 1)
    ++start;

  /* Now look through the unaligned addresses.  */
  i = start;
  if ((i & 2) == 0)
    i += 2;
  for (; i < stop; i += 4)
    {
      unsigned int insn;
      const struct sh_opcode *op;
      unsigned int prev_insn = 0;
      const struct sh_opcode *prev_op = NULL;

      insn = bfd_get_16 (abfd, contents + i);
      op = sh_insn_info (insn);
      if (op == NULL
         || (op->flags & (LOAD | STORE)) == 0)
       continue;

      /* This is a load or store which is not on a four byte boundary.  */

      while (*plabel < label_end && **plabel < i)
       ++*plabel;

      if (i > start)
       {
         prev_insn = bfd_get_16 (abfd, contents + i - 2);
         /* If INSN is the field b of a parallel processing insn, it is not
            a load / store after all.  Note that the test here might mistake
            the field_b of a pcopy insn for the starting code of a parallel
            processing insn; this might miss a swapping opportunity, but at
            least we're on the safe side.  */
         if (dsp && (prev_insn & 0xfc00) == 0xf800)
           continue;

         /* Check if prev_insn is actually the field b of a parallel
            processing insn.  Again, this can give a spurious match
            after a pcopy.  */
         if (dsp && i - 2 > start)
           {
             unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);

             if ((pprev_insn & 0xfc00) == 0xf800)
              prev_op = NULL;
             else
              prev_op = sh_insn_info (prev_insn);
           }
         else
           prev_op = sh_insn_info (prev_insn);

         /* If the load/store instruction is in a delay slot, we
            can't swap.  */
         if (prev_op == NULL
             || (prev_op->flags & DELAY) != 0)
           continue;
       }
      if (i > start
         && (*plabel >= label_end || **plabel != i)
         && prev_op != NULL
         && (prev_op->flags & (LOAD | STORE)) == 0
         && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
       {
         bfd_boolean ok;

         /* The load/store instruction does not have a label, and
            there is a previous instruction; PREV_INSN is not
            itself a load/store instruction, and PREV_INSN and
            INSN do not conflict.  */

         ok = TRUE;

         if (i >= start + 4)
           {
             unsigned int prev2_insn;
             const struct sh_opcode *prev2_op;

             prev2_insn = bfd_get_16 (abfd, contents + i - 4);
             prev2_op = sh_insn_info (prev2_insn);

             /* If the instruction before PREV_INSN has a delay
               slot--that is, PREV_INSN is in a delay slot--we
               can not swap.  */
             if (prev2_op == NULL
                || (prev2_op->flags & DELAY) != 0)
              ok = FALSE;

             /* If the instruction before PREV_INSN is a load,
               and it sets a register which INSN uses, then
               putting INSN immediately after PREV_INSN will
               cause a pipeline bubble, so there is no point to
               making the swap.  */
             if (ok
                && (prev2_op->flags & LOAD) != 0
                && sh_load_use (prev2_insn, prev2_op, insn, op))
              ok = FALSE;
           }

         if (ok)
           {
             if (! (*swap) (abfd, sec, relocs, contents, i - 2))
              return FALSE;
             *pswapped = TRUE;
             continue;
           }
       }

      while (*plabel < label_end && **plabel < i + 2)
       ++*plabel;

      if (i + 2 < stop
         && (*plabel >= label_end || **plabel != i + 2))
       {
         unsigned int next_insn;
         const struct sh_opcode *next_op;

         /* There is an instruction after the load/store
            instruction, and it does not have a label.  */
         next_insn = bfd_get_16 (abfd, contents + i + 2);
         next_op = sh_insn_info (next_insn);
         if (next_op != NULL
             && (next_op->flags & (LOAD | STORE)) == 0
             && ! sh_insns_conflict (insn, op, next_insn, next_op))
           {
             bfd_boolean ok;

             /* NEXT_INSN is not itself a load/store instruction,
               and it does not conflict with INSN.  */

             ok = TRUE;

             /* If PREV_INSN is a load, and it sets a register
               which NEXT_INSN uses, then putting NEXT_INSN
               immediately after PREV_INSN will cause a pipeline
               bubble, so there is no reason to make this swap.  */
             if (prev_op != NULL
                && (prev_op->flags & LOAD) != 0
                && sh_load_use (prev_insn, prev_op, next_insn, next_op))
              ok = FALSE;

             /* If INSN is a load, and it sets a register which
               the insn after NEXT_INSN uses, then doing the
               swap will cause a pipeline bubble, so there is no
               reason to make the swap.  However, if the insn
               after NEXT_INSN is itself a load or store
               instruction, then it is misaligned, so
               optimistically hope that it will be swapped
               itself, and just live with the pipeline bubble if
               it isn't.  */
             if (ok
                && i + 4 < stop
                && (op->flags & LOAD) != 0)
              {
                unsigned int next2_insn;
                const struct sh_opcode *next2_op;

                next2_insn = bfd_get_16 (abfd, contents + i + 4);
                next2_op = sh_insn_info (next2_insn);
                if (next2_op == NULL
                    || ((next2_op->flags & (LOAD | STORE)) == 0
                       && sh_load_use (insn, op, next2_insn, next2_op)))
                  ok = FALSE;
              }

             if (ok)
              {
                if (! (*swap) (abfd, sec, relocs, contents, i))
                  return FALSE;
                *pswapped = TRUE;
                continue;
              }
           }
       }
    }

  return TRUE;
}

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static bfd_boolean coff_small_new_section_hook ( bfd abfd,
asection section 
) [static]

Definition at line 3096 of file coff-sh.c.

{
  if (! coff_new_section_hook (abfd, section))
    return FALSE;

  /* We must align to at least a four byte boundary, because longword
     accesses must be on a four byte boundary.  */
  if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
    section->alignment_power = 2;

  return TRUE;
}

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Definition at line 3060 of file coff-sh.c.

static long get_symbol_value ( asymbol symbol) [static]

Definition at line 399 of file coff-sh.c.

{
  bfd_vma relocation;

  if (bfd_is_com_section (symbol->section))
    relocation = 0;
  else
    relocation = (symbol->value +
                symbol->section->output_section->vma +
                symbol->section->output_offset);

  return relocation;
}

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static bfd_reloc_status_type sh_reloc PARAMS ( (bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **)  ) [static]
static long get_symbol_value PARAMS ( (asymbol *)  ) [static]
static struct sh_opcode* sh_insn_info PARAMS ( (unsigned int ) [static, read]
static bfd_boolean sh_swap_insns PARAMS ( (bfd *, asection *, PTR, bfd_byte *, bfd_vma ) [static]
static reloc_howto_type* sh_coff_reloc_type_lookup PARAMS ( (bfd *, bfd_reloc_code_real_type ) [static]
static bfd_boolean sh_align_loads ( bfd abfd,
asection sec,
struct internal_reloc internal_relocs,
bfd_byte contents,
bfd_boolean pswapped 
) [static]

Definition at line 2555 of file coff-sh.c.

{
  struct internal_reloc *irel, *irelend;
  bfd_vma *labels = NULL;
  bfd_vma *label, *label_end;
  bfd_size_type amt;

  *pswapped = FALSE;

  irelend = internal_relocs + sec->reloc_count;

  /* Get all the addresses with labels on them.  */
  amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
  labels = (bfd_vma *) bfd_malloc (amt);
  if (labels == NULL)
    goto error_return;
  label_end = labels;
  for (irel = internal_relocs; irel < irelend; irel++)
    {
      if (irel->r_type == R_SH_LABEL)
       {
         *label_end = irel->r_vaddr - sec->vma;
         ++label_end;
       }
    }

  /* Note that the assembler currently always outputs relocs in
     address order.  If that ever changes, this code will need to sort
     the label values and the relocs.  */

  label = labels;

  for (irel = internal_relocs; irel < irelend; irel++)
    {
      bfd_vma start, stop;

      if (irel->r_type != R_SH_CODE)
       continue;

      start = irel->r_vaddr - sec->vma;

      for (irel++; irel < irelend; irel++)
       if (irel->r_type == R_SH_DATA)
         break;
      if (irel < irelend)
       stop = irel->r_vaddr - sec->vma;
      else
       stop = sec->size;

      if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
                                 (PTR) internal_relocs, &label,
                                 label_end, start, stop, pswapped))
       goto error_return;
    }

  free (labels);

  return TRUE;

 error_return:
  if (labels != NULL)
    free (labels);
  return FALSE;
}

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static bfd_byte* sh_coff_get_relocated_section_contents ( bfd output_bfd,
struct bfd_link_info link_info,
struct bfd_link_order link_order,
bfd_byte data,
bfd_boolean  relocatable,
asymbol **  symbols 
) [static]

Definition at line 2934 of file coff-sh.c.

{
  asection *input_section = link_order->u.indirect.section;
  bfd *input_bfd = input_section->owner;
  asection **sections = NULL;
  struct internal_reloc *internal_relocs = NULL;
  struct internal_syment *internal_syms = NULL;

  /* We only need to handle the case of relaxing, or of having a
     particular set of section contents, specially.  */
  if (relocatable
      || coff_section_data (input_bfd, input_section) == NULL
      || coff_section_data (input_bfd, input_section)->contents == NULL)
    return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
                                                 link_order, data,
                                                 relocatable,
                                                 symbols);

  memcpy (data, coff_section_data (input_bfd, input_section)->contents,
         (size_t) input_section->size);

  if ((input_section->flags & SEC_RELOC) != 0
      && input_section->reloc_count > 0)
    {
      bfd_size_type symesz = bfd_coff_symesz (input_bfd);
      bfd_byte *esym, *esymend;
      struct internal_syment *isymp;
      asection **secpp;
      bfd_size_type amt;

      if (! _bfd_coff_get_external_symbols (input_bfd))
       goto error_return;

      internal_relocs = (_bfd_coff_read_internal_relocs
                      (input_bfd, input_section, FALSE, (bfd_byte *) NULL,
                       FALSE, (struct internal_reloc *) NULL));
      if (internal_relocs == NULL)
       goto error_return;

      amt = obj_raw_syment_count (input_bfd);
      amt *= sizeof (struct internal_syment);
      internal_syms = (struct internal_syment *) bfd_malloc (amt);
      if (internal_syms == NULL)
       goto error_return;

      amt = obj_raw_syment_count (input_bfd);
      amt *= sizeof (asection *);
      sections = (asection **) bfd_malloc (amt);
      if (sections == NULL)
       goto error_return;

      isymp = internal_syms;
      secpp = sections;
      esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
      esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
      while (esym < esymend)
       {
         bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);

         if (isymp->n_scnum != 0)
           *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
         else
           {
             if (isymp->n_value == 0)
              *secpp = bfd_und_section_ptr;
             else
              *secpp = bfd_com_section_ptr;
           }

         esym += (isymp->n_numaux + 1) * symesz;
         secpp += isymp->n_numaux + 1;
         isymp += isymp->n_numaux + 1;
       }

      if (! sh_relocate_section (output_bfd, link_info, input_bfd,
                             input_section, data, internal_relocs,
                             internal_syms, sections))
       goto error_return;

      free (sections);
      sections = NULL;
      free (internal_syms);
      internal_syms = NULL;
      free (internal_relocs);
      internal_relocs = NULL;
    }

  return data;

 error_return:
  if (internal_relocs != NULL)
    free (internal_relocs);
  if (internal_syms != NULL)
    free (internal_syms);
  if (sections != NULL)
    free (sections);
  return NULL;
}

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static reloc_howto_type* sh_coff_reloc_name_lookup ( bfd *abfd  ATTRIBUTE_UNUSED,
const char *  r_name 
) [static]

Definition at line 515 of file coff-sh.c.

{
  unsigned int i;

  for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
    if (sh_coff_howtos[i].name != NULL
       && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
      return &sh_coff_howtos[i];

  return NULL;
}

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static reloc_howto_type* sh_coff_reloc_type_lookup ( abfd  ,
bfd_reloc_code_real_type  code 
) [static]

Definition at line 500 of file coff-sh.c.

{
  unsigned int i;

  for (i = ARRAY_SIZE (sh_reloc_map); i--;)
    if (sh_reloc_map[i].bfd_reloc_val == code)
      return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];

  fprintf (stderr, "SH Error: unknown reloc type %d\n", code);
  return NULL;
}

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static struct sh_opcode* sh_insn_info ( unsigned int  insn) [static, read]

Definition at line 2046 of file coff-sh.c.

{
  const struct sh_major_opcode *maj;
  const struct sh_minor_opcode *min, *minend;

  maj = &sh_opcodes[(insn & 0xf000) >> 12];
  min = maj->minor_opcodes;
  minend = min + maj->count;
  for (; min < minend; min++)
    {
      unsigned int l;
      const struct sh_opcode *op, *opend;

      l = insn & min->mask;
      op = min->opcodes;
      opend = op + min->count;

      /* Since the opcodes tables are sorted, we could use a binary
         search here if the count were above some cutoff value.  */
      for (; op < opend; op++)
       if (op->opcode == l)
         return op;
    }

  return NULL;
}

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static bfd_boolean sh_insn_sets_freg ( unsigned int  insn,
const struct sh_opcode op,
unsigned int  freg 
) [static]

Definition at line 2195 of file coff-sh.c.

{
  unsigned int f;

  f = op->flags;

  /* We can't tell if this is a double-precision insn, so just play safe
     and assume that it might be.  So not only have we test FREG against
     itself, but also even FREG against FREG+1 - if the using insn uses
     just the low part of a double precision value - but also an odd
     FREG against FREG-1 -  if the setting insn sets just the low part
     of a double precision value.
     So what this all boils down to is that we have to ignore the lowest
     bit of the register number.  */

  if ((f & SETSF1) != 0
      && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
    return TRUE;

  return FALSE;
}

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static bfd_boolean sh_insn_sets_reg ( unsigned int  insn,
const struct sh_opcode op,
unsigned int  reg 
) [static]

Definition at line 2120 of file coff-sh.c.

{
  unsigned int f;

  f = op->flags;

  if ((f & SETS1) != 0
      && SETS1_REG (insn) == reg)
    return TRUE;
  if ((f & SETS2) != 0
      && SETS2_REG (insn) == reg)
    return TRUE;
  if ((f & SETSR0) != 0
      && reg == 0)
    return TRUE;
  if ((f & SETSAS) && reg == SETSAS_REG (insn))
    return TRUE;

  return FALSE;
}

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static bfd_boolean sh_insn_uses_freg ( unsigned int  insn,
const struct sh_opcode op,
unsigned int  freg 
) [static]

Definition at line 2161 of file coff-sh.c.

{
  unsigned int f;

  f = op->flags;

  /* We can't tell if this is a double-precision insn, so just play safe
     and assume that it might be.  So not only have we test FREG against
     itself, but also even FREG against FREG+1 - if the using insn uses
     just the low part of a double precision value - but also an odd
     FREG against FREG-1 -  if the setting insn sets just the low part
     of a double precision value.
     So what this all boils down to is that we have to ignore the lowest
     bit of the register number.  */

  if ((f & USESF1) != 0
      && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
    return TRUE;
  if ((f & USESF2) != 0
      && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
    return TRUE;
  if ((f & USESF0) != 0
      && freg == 0)
    return TRUE;

  return FALSE;
}

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static bfd_boolean sh_insn_uses_or_sets_freg ( unsigned int  insn,
const struct sh_opcode op,
unsigned int  reg 
) [static]

Definition at line 2147 of file coff-sh.c.

{
  if (sh_insn_uses_freg (insn, op, reg))
    return TRUE;

  return sh_insn_sets_freg (insn, op, reg);
}

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static bfd_boolean sh_insn_uses_or_sets_reg ( unsigned int  insn,
const struct sh_opcode op,
unsigned int  reg 
) [static]

Definition at line 2077 of file coff-sh.c.

{
  if (sh_insn_uses_reg (insn, op, reg))
    return TRUE;

  return sh_insn_sets_reg (insn, op, reg);
}

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static bfd_boolean sh_insn_uses_reg ( unsigned int  insn,
const struct sh_opcode op,
unsigned int  reg 
) [static]

Definition at line 2091 of file coff-sh.c.

{
  unsigned int f;

  f = op->flags;

  if ((f & USES1) != 0
      && USES1_REG (insn) == reg)
    return TRUE;
  if ((f & USES2) != 0
      && USES2_REG (insn) == reg)
    return TRUE;
  if ((f & USESR0) != 0
      && reg == 0)
    return TRUE;
  if ((f & USESAS) && reg == USESAS_REG (insn))
    return TRUE;
  if ((f & USESR8) && reg == 8)
    return TRUE;

  return FALSE;
}

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static bfd_boolean sh_insns_conflict ( unsigned int  i1,
const struct sh_opcode op1,
unsigned int  i2,
const struct sh_opcode op2 
) [static]

Definition at line 2226 of file coff-sh.c.

{
  unsigned int f1, f2;

  f1 = op1->flags;
  f2 = op2->flags;

  /* Load of fpscr conflicts with floating point operations.
     FIXME: shouldn't test raw opcodes here.  */
  if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
      || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
    return TRUE;

  if ((f1 & (BRANCH | DELAY)) != 0
      || (f2 & (BRANCH | DELAY)) != 0)
    return TRUE;

  if (((f1 | f2) & SETSSP)
      && (f1 & (SETSSP | USESSP))
      && (f2 & (SETSSP | USESSP)))
    return TRUE;

  if ((f1 & SETS1) != 0
      && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
    return TRUE;
  if ((f1 & SETS2) != 0
      && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
    return TRUE;
  if ((f1 & SETSR0) != 0
      && sh_insn_uses_or_sets_reg (i2, op2, 0))
    return TRUE;
  if ((f1 & SETSAS)
      && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
    return TRUE;
  if ((f1 & SETSF1) != 0
      && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
    return TRUE;

  if ((f2 & SETS1) != 0
      && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
    return TRUE;
  if ((f2 & SETS2) != 0
      && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
    return TRUE;
  if ((f2 & SETSR0) != 0
      && sh_insn_uses_or_sets_reg (i1, op1, 0))
    return TRUE;
  if ((f2 & SETSAS)
      && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
    return TRUE;
  if ((f2 & SETSF1) != 0
      && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
    return TRUE;

  /* The instructions do not conflict.  */
  return FALSE;
}

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static bfd_boolean sh_load_use ( unsigned int  i1,
const struct sh_opcode op1,
unsigned int  i2,
const struct sh_opcode op2 
) [static]

Definition at line 2292 of file coff-sh.c.

{
  unsigned int f1;

  f1 = op1->flags;

  if ((f1 & LOAD) == 0)
    return FALSE;

  /* If both SETS1 and SETSSP are set, that means a load to a special
     register using postincrement addressing mode, which we don't care
     about here.  */
  if ((f1 & SETS1) != 0
      && (f1 & SETSSP) == 0
      && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
    return TRUE;

  if ((f1 & SETSR0) != 0
      && sh_insn_uses_reg (i2, op2, 0))
    return TRUE;

  if ((f1 & SETSF1) != 0
      && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
    return TRUE;

  return FALSE;
}

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static bfd_boolean sh_relax_delete_bytes ( bfd abfd,
asection sec,
bfd_vma  addr,
int  count 
) [static]

Definition at line 1066 of file coff-sh.c.

{
  bfd_byte *contents;
  struct internal_reloc *irel, *irelend;
  struct internal_reloc *irelalign;
  bfd_vma toaddr;
  bfd_byte *esym, *esymend;
  bfd_size_type symesz;
  struct coff_link_hash_entry **sym_hash;
  asection *o;

  contents = coff_section_data (abfd, sec)->contents;

  /* The deletion must stop at the next ALIGN reloc for an aligment
     power larger than the number of bytes we are deleting.  */

  irelalign = NULL;
  toaddr = sec->size;

  irel = coff_section_data (abfd, sec)->relocs;
  irelend = irel + sec->reloc_count;
  for (; irel < irelend; irel++)
    {
      if (irel->r_type == R_SH_ALIGN
         && irel->r_vaddr - sec->vma > addr
         && count < (1 << irel->r_offset))
       {
         irelalign = irel;
         toaddr = irel->r_vaddr - sec->vma;
         break;
       }
    }

  /* Actually delete the bytes.  */
  memmove (contents + addr, contents + addr + count,
          (size_t) (toaddr - addr - count));
  if (irelalign == NULL)
    sec->size -= count;
  else
    {
      int i;

#define NOP_OPCODE (0x0009)

      BFD_ASSERT ((count & 1) == 0);
      for (i = 0; i < count; i += 2)
       bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
    }

  /* Adjust all the relocs.  */
  for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
    {
      bfd_vma nraddr, stop;
      bfd_vma start = 0;
      int insn = 0;
      struct internal_syment sym;
      int off, adjust, oinsn;
      bfd_signed_vma voff = 0;
      bfd_boolean overflow;

      /* Get the new reloc address.  */
      nraddr = irel->r_vaddr - sec->vma;
      if ((irel->r_vaddr - sec->vma > addr
          && irel->r_vaddr - sec->vma < toaddr)
         || (irel->r_type == R_SH_ALIGN
             && irel->r_vaddr - sec->vma == toaddr))
       nraddr -= count;

      /* See if this reloc was for the bytes we have deleted, in which
        case we no longer care about it.  Don't delete relocs which
        represent addresses, though.  */
      if (irel->r_vaddr - sec->vma >= addr
         && irel->r_vaddr - sec->vma < addr + count
         && irel->r_type != R_SH_ALIGN
         && irel->r_type != R_SH_CODE
         && irel->r_type != R_SH_DATA
         && irel->r_type != R_SH_LABEL)
       irel->r_type = R_SH_UNUSED;

      /* If this is a PC relative reloc, see if the range it covers
         includes the bytes we have deleted.  */
      switch (irel->r_type)
       {
       default:
         break;

       case R_SH_PCDISP8BY2:
       case R_SH_PCDISP:
       case R_SH_PCRELIMM8BY2:
       case R_SH_PCRELIMM8BY4:
         start = irel->r_vaddr - sec->vma;
         insn = bfd_get_16 (abfd, contents + nraddr);
         break;
       }

      switch (irel->r_type)
       {
       default:
         start = stop = addr;
         break;

       case R_SH_IMM32:
#ifdef COFF_WITH_PE
       case R_SH_IMM32CE:
       case R_SH_IMAGEBASE:
#endif
         /* If this reloc is against a symbol defined in this
             section, and the symbol will not be adjusted below, we
             must check the addend to see it will put the value in
             range to be adjusted, and hence must be changed.  */
         bfd_coff_swap_sym_in (abfd,
                            ((bfd_byte *) obj_coff_external_syms (abfd)
                             + (irel->r_symndx
                                * bfd_coff_symesz (abfd))),
                            &sym);
         if (sym.n_sclass != C_EXT
             && sym.n_scnum == sec->target_index
             && ((bfd_vma) sym.n_value <= addr
                || (bfd_vma) sym.n_value >= toaddr))
           {
             bfd_vma val;

             val = bfd_get_32 (abfd, contents + nraddr);
             val += sym.n_value;
             if (val > addr && val < toaddr)
              bfd_put_32 (abfd, val - count, contents + nraddr);
           }
         start = stop = addr;
         break;

       case R_SH_PCDISP8BY2:
         off = insn & 0xff;
         if (off & 0x80)
           off -= 0x100;
         stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
         break;

       case R_SH_PCDISP:
         bfd_coff_swap_sym_in (abfd,
                            ((bfd_byte *) obj_coff_external_syms (abfd)
                             + (irel->r_symndx
                                * bfd_coff_symesz (abfd))),
                            &sym);
         if (sym.n_sclass == C_EXT)
           start = stop = addr;
         else
           {
             off = insn & 0xfff;
             if (off & 0x800)
              off -= 0x1000;
             stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
           }
         break;

       case R_SH_PCRELIMM8BY2:
         off = insn & 0xff;
         stop = start + 4 + off * 2;
         break;

       case R_SH_PCRELIMM8BY4:
         off = insn & 0xff;
         stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
         break;

       case R_SH_SWITCH8:
       case R_SH_SWITCH16:
       case R_SH_SWITCH32:
         /* These relocs types represent
              .word L2-L1
            The r_offset field holds the difference between the reloc
            address and L1.  That is the start of the reloc, and
            adding in the contents gives us the top.  We must adjust
            both the r_offset field and the section contents.  */

         start = irel->r_vaddr - sec->vma;
         stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);

         if (start > addr
             && start < toaddr
             && (stop <= addr || stop >= toaddr))
           irel->r_offset += count;
         else if (stop > addr
                 && stop < toaddr
                 && (start <= addr || start >= toaddr))
           irel->r_offset -= count;

         start = stop;

         if (irel->r_type == R_SH_SWITCH16)
           voff = bfd_get_signed_16 (abfd, contents + nraddr);
         else if (irel->r_type == R_SH_SWITCH8)
           voff = bfd_get_8 (abfd, contents + nraddr);
         else
           voff = bfd_get_signed_32 (abfd, contents + nraddr);
         stop = (bfd_vma) ((bfd_signed_vma) start + voff);

         break;

       case R_SH_USES:
         start = irel->r_vaddr - sec->vma;
         stop = (bfd_vma) ((bfd_signed_vma) start
                         + (long) irel->r_offset
                         + 4);
         break;
       }

      if (start > addr
         && start < toaddr
         && (stop <= addr || stop >= toaddr))
       adjust = count;
      else if (stop > addr
              && stop < toaddr
              && (start <= addr || start >= toaddr))
       adjust = - count;
      else
       adjust = 0;

      if (adjust != 0)
       {
         oinsn = insn;
         overflow = FALSE;
         switch (irel->r_type)
           {
           default:
             abort ();
             break;

           case R_SH_PCDISP8BY2:
           case R_SH_PCRELIMM8BY2:
             insn += adjust / 2;
             if ((oinsn & 0xff00) != (insn & 0xff00))
              overflow = TRUE;
             bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
             break;

           case R_SH_PCDISP:
             insn += adjust / 2;
             if ((oinsn & 0xf000) != (insn & 0xf000))
              overflow = TRUE;
             bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
             break;

           case R_SH_PCRELIMM8BY4:
             BFD_ASSERT (adjust == count || count >= 4);
             if (count >= 4)
              insn += adjust / 4;
             else
              {
                if ((irel->r_vaddr & 3) == 0)
                  ++insn;
              }
             if ((oinsn & 0xff00) != (insn & 0xff00))
              overflow = TRUE;
             bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
             break;

           case R_SH_SWITCH8:
             voff += adjust;
             if (voff < 0 || voff >= 0xff)
              overflow = TRUE;
             bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
             break;

           case R_SH_SWITCH16:
             voff += adjust;
             if (voff < - 0x8000 || voff >= 0x8000)
              overflow = TRUE;
             bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
             break;

           case R_SH_SWITCH32:
             voff += adjust;
             bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
             break;

           case R_SH_USES:
             irel->r_offset += adjust;
             break;
           }

         if (overflow)
           {
             ((*_bfd_error_handler)
              ("%B: 0x%lx: fatal: reloc overflow while relaxing",
              abfd, (unsigned long) irel->r_vaddr));
             bfd_set_error (bfd_error_bad_value);
             return FALSE;
           }
       }

      irel->r_vaddr = nraddr + sec->vma;
    }

  /* Look through all the other sections.  If there contain any IMM32
     relocs against internal symbols which we are not going to adjust
     below, we may need to adjust the addends.  */
  for (o = abfd->sections; o != NULL; o = o->next)
    {
      struct internal_reloc *internal_relocs;
      struct internal_reloc *irelscan, *irelscanend;
      bfd_byte *ocontents;

      if (o == sec
         || (o->flags & SEC_RELOC) == 0
         || o->reloc_count == 0)
       continue;

      /* We always cache the relocs.  Perhaps, if info->keep_memory is
         FALSE, we should free them, if we are permitted to, when we
         leave sh_coff_relax_section.  */
      internal_relocs = (_bfd_coff_read_internal_relocs
                      (abfd, o, TRUE, (bfd_byte *) NULL, FALSE,
                       (struct internal_reloc *) NULL));
      if (internal_relocs == NULL)
       return FALSE;

      ocontents = NULL;
      irelscanend = internal_relocs + o->reloc_count;
      for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
       {
         struct internal_syment sym;

#ifdef COFF_WITH_PE
         if (irelscan->r_type != R_SH_IMM32
             && irelscan->r_type != R_SH_IMAGEBASE
             && irelscan->r_type != R_SH_IMM32CE)
#else
         if (irelscan->r_type != R_SH_IMM32)
#endif
           continue;

         bfd_coff_swap_sym_in (abfd,
                            ((bfd_byte *) obj_coff_external_syms (abfd)
                             + (irelscan->r_symndx
                                * bfd_coff_symesz (abfd))),
                            &sym);
         if (sym.n_sclass != C_EXT
             && sym.n_scnum == sec->target_index
             && ((bfd_vma) sym.n_value <= addr
                || (bfd_vma) sym.n_value >= toaddr))
           {
             bfd_vma val;

             if (ocontents == NULL)
              {
                if (coff_section_data (abfd, o)->contents != NULL)
                  ocontents = coff_section_data (abfd, o)->contents;
                else
                  {
                    if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
                     return FALSE;
                    /* We always cache the section contents.
                         Perhaps, if info->keep_memory is FALSE, we
                         should free them, if we are permitted to,
                         when we leave sh_coff_relax_section.  */
                    coff_section_data (abfd, o)->contents = ocontents;
                  }
              }

             val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
             val += sym.n_value;
             if (val > addr && val < toaddr)
              bfd_put_32 (abfd, val - count,
                         ocontents + irelscan->r_vaddr - o->vma);

             coff_section_data (abfd, o)->keep_contents = TRUE;
           }
       }
    }

  /* Adjusting the internal symbols will not work if something has
     already retrieved the generic symbols.  It would be possible to
     make this work by adjusting the generic symbols at the same time.
     However, this case should not arise in normal usage.  */
  if (obj_symbols (abfd) != NULL
      || obj_raw_syments (abfd) != NULL)
    {
      ((*_bfd_error_handler)
       ("%B: fatal: generic symbols retrieved before relaxing", abfd));
      bfd_set_error (bfd_error_invalid_operation);
      return FALSE;
    }

  /* Adjust all the symbols.  */
  sym_hash = obj_coff_sym_hashes (abfd);
  symesz = bfd_coff_symesz (abfd);
  esym = (bfd_byte *) obj_coff_external_syms (abfd);
  esymend = esym + obj_raw_syment_count (abfd) * symesz;
  while (esym < esymend)
    {
      struct internal_syment isym;

      bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);

      if (isym.n_scnum == sec->target_index
         && (bfd_vma) isym.n_value > addr
         && (bfd_vma) isym.n_value < toaddr)
       {
         isym.n_value -= count;

         bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);

         if (*sym_hash != NULL)
           {
             BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
                       || (*sym_hash)->root.type == bfd_link_hash_defweak);
             BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
                       && (*sym_hash)->root.u.def.value < toaddr);
             (*sym_hash)->root.u.def.value -= count;
           }
       }

      esym += (isym.n_numaux + 1) * symesz;
      sym_hash += isym.n_numaux + 1;
    }

  /* See if we can move the ALIGN reloc forward.  We have adjusted
     r_vaddr for it already.  */
  if (irelalign != NULL)
    {
      bfd_vma alignto, alignaddr;

      alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
      alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
                          1 << irelalign->r_offset);
      if (alignto != alignaddr)
       {
         /* Tail recursion.  */
         return sh_relax_delete_bytes (abfd, sec, alignaddr,
                                   (int) (alignto - alignaddr));
       }
    }

  return TRUE;
}

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static bfd_boolean sh_relax_section ( bfd abfd,
asection sec,
struct bfd_link_info link_info,
bfd_boolean again 
) [static]

Definition at line 709 of file coff-sh.c.

{
  struct internal_reloc *internal_relocs;
  bfd_boolean have_code;
  struct internal_reloc *irel, *irelend;
  bfd_byte *contents = NULL;

  *again = FALSE;

  if (link_info->relocatable
      || (sec->flags & SEC_RELOC) == 0
      || sec->reloc_count == 0)
    return TRUE;

  if (coff_section_data (abfd, sec) == NULL)
    {
      bfd_size_type amt = sizeof (struct coff_section_tdata);
      sec->used_by_bfd = (PTR) bfd_zalloc (abfd, amt);
      if (sec->used_by_bfd == NULL)
       return FALSE;
    }

  internal_relocs = (_bfd_coff_read_internal_relocs
                   (abfd, sec, link_info->keep_memory,
                    (bfd_byte *) NULL, FALSE,
                    (struct internal_reloc *) NULL));
  if (internal_relocs == NULL)
    goto error_return;

  have_code = FALSE;

  irelend = internal_relocs + sec->reloc_count;
  for (irel = internal_relocs; irel < irelend; irel++)
    {
      bfd_vma laddr, paddr, symval;
      unsigned short insn;
      struct internal_reloc *irelfn, *irelscan, *irelcount;
      struct internal_syment sym;
      bfd_signed_vma foff;

      if (irel->r_type == R_SH_CODE)
       have_code = TRUE;

      if (irel->r_type != R_SH_USES)
       continue;

      /* Get the section contents.  */
      if (contents == NULL)
       {
         if (coff_section_data (abfd, sec)->contents != NULL)
           contents = coff_section_data (abfd, sec)->contents;
         else
           {
             if (!bfd_malloc_and_get_section (abfd, sec, &contents))
              goto error_return;
           }
       }

      /* The r_offset field of the R_SH_USES reloc will point us to
         the register load.  The 4 is because the r_offset field is
         computed as though it were a jump offset, which are based
         from 4 bytes after the jump instruction.  */
      laddr = irel->r_vaddr - sec->vma + 4;
      /* Careful to sign extend the 32-bit offset.  */
      laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
      if (laddr >= sec->size)
       {
         (*_bfd_error_handler) ("%B: 0x%lx: warning: bad R_SH_USES offset",
                             abfd, (unsigned long) irel->r_vaddr);
         continue;
       }
      insn = bfd_get_16 (abfd, contents + laddr);

      /* If the instruction is not mov.l NN,rN, we don't know what to do.  */
      if ((insn & 0xf000) != 0xd000)
       {
         ((*_bfd_error_handler)
          ("%B: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
           abfd, (unsigned long) irel->r_vaddr, insn));
         continue;
       }

      /* Get the address from which the register is being loaded.  The
        displacement in the mov.l instruction is quadrupled.  It is a
        displacement from four bytes after the movl instruction, but,
        before adding in the PC address, two least significant bits
        of the PC are cleared.  We assume that the section is aligned
        on a four byte boundary.  */
      paddr = insn & 0xff;
      paddr *= 4;
      paddr += (laddr + 4) &~ (bfd_vma) 3;
      if (paddr >= sec->size)
       {
         ((*_bfd_error_handler)
          ("%B: 0x%lx: warning: bad R_SH_USES load offset",
           abfd, (unsigned long) irel->r_vaddr));
         continue;
       }

      /* Get the reloc for the address from which the register is
         being loaded.  This reloc will tell us which function is
         actually being called.  */
      paddr += sec->vma;
      for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
       if (irelfn->r_vaddr == paddr
#ifdef COFF_WITH_PE
           && (irelfn->r_type == R_SH_IMM32
              || irelfn->r_type == R_SH_IMM32CE
              || irelfn->r_type == R_SH_IMAGEBASE)

#else
           && irelfn->r_type == R_SH_IMM32
#endif
           )
         break;
      if (irelfn >= irelend)
       {
         ((*_bfd_error_handler)
          ("%B: 0x%lx: warning: could not find expected reloc",
           abfd, (unsigned long) paddr));
         continue;
       }

      /* Get the value of the symbol referred to by the reloc.  */
      if (! _bfd_coff_get_external_symbols (abfd))
       goto error_return;
      bfd_coff_swap_sym_in (abfd,
                         ((bfd_byte *) obj_coff_external_syms (abfd)
                          + (irelfn->r_symndx
                            * bfd_coff_symesz (abfd))),
                         &sym);
      if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
       {
         ((*_bfd_error_handler)
          ("%B: 0x%lx: warning: symbol in unexpected section",
           abfd, (unsigned long) paddr));
         continue;
       }

      if (sym.n_sclass != C_EXT)
       {
         symval = (sym.n_value
                  - sec->vma
                  + sec->output_section->vma
                  + sec->output_offset);
       }
      else
       {
         struct coff_link_hash_entry *h;

         h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
         BFD_ASSERT (h != NULL);
         if (h->root.type != bfd_link_hash_defined
             && h->root.type != bfd_link_hash_defweak)
           {
             /* This appears to be a reference to an undefined
                 symbol.  Just ignore it--it will be caught by the
                 regular reloc processing.  */
             continue;
           }

         symval = (h->root.u.def.value
                  + h->root.u.def.section->output_section->vma
                  + h->root.u.def.section->output_offset);
       }

      symval += bfd_get_32 (abfd, contents + paddr - sec->vma);

      /* See if this function call can be shortened.  */
      foff = (symval
             - (irel->r_vaddr
               - sec->vma
               + sec->output_section->vma
               + sec->output_offset
               + 4));
      if (foff < -0x1000 || foff >= 0x1000)
       {
         /* After all that work, we can't shorten this function call.  */
         continue;
       }

      /* Shorten the function call.  */

      /* For simplicity of coding, we are going to modify the section
        contents, the section relocs, and the BFD symbol table.  We
        must tell the rest of the code not to free up this
        information.  It would be possible to instead create a table
        of changes which have to be made, as is done in coff-mips.c;
        that would be more work, but would require less memory when
        the linker is run.  */

      coff_section_data (abfd, sec)->relocs = internal_relocs;
      coff_section_data (abfd, sec)->keep_relocs = TRUE;

      coff_section_data (abfd, sec)->contents = contents;
      coff_section_data (abfd, sec)->keep_contents = TRUE;

      obj_coff_keep_syms (abfd) = TRUE;

      /* Replace the jsr with a bsr.  */

      /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
         replace the jsr with a bsr.  */
      irel->r_type = R_SH_PCDISP;
      irel->r_symndx = irelfn->r_symndx;
      if (sym.n_sclass != C_EXT)
       {
         /* If this needs to be changed because of future relaxing,
             it will be handled here like other internal PCDISP
             relocs.  */
         bfd_put_16 (abfd,
                    (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
                    contents + irel->r_vaddr - sec->vma);
       }
      else
       {
         /* We can't fully resolve this yet, because the external
             symbol value may be changed by future relaxing.  We let
             the final link phase handle it.  */
         bfd_put_16 (abfd, (bfd_vma) 0xb000,
                    contents + irel->r_vaddr - sec->vma);
       }

      /* See if there is another R_SH_USES reloc referring to the same
         register load.  */
      for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
       if (irelscan->r_type == R_SH_USES
           && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
         break;
      if (irelscan < irelend)
       {
         /* Some other function call depends upon this register load,
            and we have not yet converted that function call.
            Indeed, we may never be able to convert it.  There is
            nothing else we can do at this point.  */
         continue;
       }

      /* Look for a R_SH_COUNT reloc on the location where the
         function address is stored.  Do this before deleting any
         bytes, to avoid confusion about the address.  */
      for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
       if (irelcount->r_vaddr == paddr
           && irelcount->r_type == R_SH_COUNT)
         break;

      /* Delete the register load.  */
      if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
       goto error_return;

      /* That will change things, so, just in case it permits some
         other function call to come within range, we should relax
         again.  Note that this is not required, and it may be slow.  */
      *again = TRUE;

      /* Now check whether we got a COUNT reloc.  */
      if (irelcount >= irelend)
       {
         ((*_bfd_error_handler)
          ("%B: 0x%lx: warning: could not find expected COUNT reloc",
           abfd, (unsigned long) paddr));
         continue;
       }

      /* The number of uses is stored in the r_offset field.  We've
         just deleted one.  */
      if (irelcount->r_offset == 0)
       {
         ((*_bfd_error_handler) ("%B: 0x%lx: warning: bad count",
                              abfd, (unsigned long) paddr));
         continue;
       }

      --irelcount->r_offset;

      /* If there are no more uses, we can delete the address.  Reload
         the address from irelfn, in case it was changed by the
         previous call to sh_relax_delete_bytes.  */
      if (irelcount->r_offset == 0)
       {
         if (! sh_relax_delete_bytes (abfd, sec,
                                   irelfn->r_vaddr - sec->vma, 4))
           goto error_return;
       }

      /* We've done all we can with that function call.  */
    }

  /* Look for load and store instructions that we can align on four
     byte boundaries.  */
  if (have_code)
    {
      bfd_boolean swapped;

      /* Get the section contents.  */
      if (contents == NULL)
       {
         if (coff_section_data (abfd, sec)->contents != NULL)
           contents = coff_section_data (abfd, sec)->contents;
         else
           {
             if (!bfd_malloc_and_get_section (abfd, sec, &contents))
              goto error_return;
           }
       }

      if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
       goto error_return;

      if (swapped)
       {
         coff_section_data (abfd, sec)->relocs = internal_relocs;
         coff_section_data (abfd, sec)->keep_relocs = TRUE;

         coff_section_data (abfd, sec)->contents = contents;
         coff_section_data (abfd, sec)->keep_contents = TRUE;

         obj_coff_keep_syms (abfd) = TRUE;
       }
    }

  if (internal_relocs != NULL
      && internal_relocs != coff_section_data (abfd, sec)->relocs)
    {
      if (! link_info->keep_memory)
       free (internal_relocs);
      else
       coff_section_data (abfd, sec)->relocs = internal_relocs;
    }

  if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
    {
      if (! link_info->keep_memory)
       free (contents);
      else
       /* Cache the section contents for coff_link_input_bfd.  */
       coff_section_data (abfd, sec)->contents = contents;
    }

  return TRUE;

 error_return:
  if (internal_relocs != NULL
      && internal_relocs != coff_section_data (abfd, sec)->relocs)
    free (internal_relocs);
  if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
    free (contents);
  return FALSE;
}

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static bfd_reloc_status_type sh_reloc ( bfd abfd,
arelent reloc_entry,
asymbol symbol_in,
PTR  data,
asection input_section,
bfd output_bfd,
error_message   
) [static]

Definition at line 567 of file coff-sh.c.

{
  unsigned long insn;
  bfd_vma sym_value;
  unsigned short r_type;
  bfd_vma addr = reloc_entry->address;
  bfd_byte *hit_data = addr + (bfd_byte *) data;

  r_type = reloc_entry->howto->type;

  if (output_bfd != NULL)
    {
      /* Partial linking--do nothing.  */
      reloc_entry->address += input_section->output_offset;
      return bfd_reloc_ok;
    }

  /* Almost all relocs have to do with relaxing.  If any work must be
     done for them, it has been done in sh_relax_section.  */
  if (r_type != R_SH_IMM32
#ifdef COFF_WITH_PE
      && r_type != R_SH_IMM32CE
      && r_type != R_SH_IMAGEBASE
#endif
      && (r_type != R_SH_PCDISP
         || (symbol_in->flags & BSF_LOCAL) != 0))
    return bfd_reloc_ok;

  if (symbol_in != NULL
      && bfd_is_und_section (symbol_in->section))
    return bfd_reloc_undefined;

  sym_value = get_symbol_value (symbol_in);

  switch (r_type)
    {
    case R_SH_IMM32:
#ifdef COFF_WITH_PE
    case R_SH_IMM32CE:
#endif
      insn = bfd_get_32 (abfd, hit_data);
      insn += sym_value + reloc_entry->addend;
      bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
      break;
#ifdef COFF_WITH_PE
    case R_SH_IMAGEBASE:
      insn = bfd_get_32 (abfd, hit_data);
      insn += sym_value + reloc_entry->addend;
      insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
      bfd_put_32 (abfd, (bfd_vma) insn, hit_data);
      break;
#endif
    case R_SH_PCDISP:
      insn = bfd_get_16 (abfd, hit_data);
      sym_value += reloc_entry->addend;
      sym_value -= (input_section->output_section->vma
                  + input_section->output_offset
                  + addr
                  + 4);
      sym_value += (insn & 0xfff) << 1;
      if (insn & 0x800)
       sym_value -= 0x1000;
      insn = (insn & 0xf000) | (sym_value & 0xfff);
      bfd_put_16 (abfd, (bfd_vma) insn, hit_data);
      if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
       return bfd_reloc_overflow;
      break;
    default:
      abort ();
      break;
    }

  return bfd_reloc_ok;
}

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static bfd_boolean sh_relocate_section ( output_bfd  ,
struct bfd_link_info info,
bfd input_bfd,
asection input_section,
bfd_byte contents,
struct internal_reloc relocs,
struct internal_syment syms,
asection **  sections 
) [static]

Definition at line 2761 of file coff-sh.c.

{
  struct internal_reloc *rel;
  struct internal_reloc *relend;

  rel = relocs;
  relend = rel + input_section->reloc_count;
  for (; rel < relend; rel++)
    {
      long symndx;
      struct coff_link_hash_entry *h;
      struct internal_syment *sym;
      bfd_vma addend;
      bfd_vma val;
      reloc_howto_type *howto;
      bfd_reloc_status_type rstat;

      /* Almost all relocs have to do with relaxing.  If any work must
         be done for them, it has been done in sh_relax_section.  */
      if (rel->r_type != R_SH_IMM32
#ifdef COFF_WITH_PE
         && rel->r_type != R_SH_IMM32CE
         && rel->r_type != R_SH_IMAGEBASE
#endif
         && rel->r_type != R_SH_PCDISP)
       continue;

      symndx = rel->r_symndx;

      if (symndx == -1)
       {
         h = NULL;
         sym = NULL;
       }
      else
       {
         if (symndx < 0
             || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
           {
             (*_bfd_error_handler)
              ("%B: illegal symbol index %ld in relocs",
               input_bfd, symndx);
             bfd_set_error (bfd_error_bad_value);
             return FALSE;
           }
         h = obj_coff_sym_hashes (input_bfd)[symndx];
         sym = syms + symndx;
       }

      if (sym != NULL && sym->n_scnum != 0)
       addend = - sym->n_value;
      else
       addend = 0;

      if (rel->r_type == R_SH_PCDISP)
       addend -= 4;

      if (rel->r_type >= SH_COFF_HOWTO_COUNT)
       howto = NULL;
      else
       howto = &sh_coff_howtos[rel->r_type];

      if (howto == NULL)
       {
         bfd_set_error (bfd_error_bad_value);
         return FALSE;
       }

#ifdef COFF_WITH_PE
      if (rel->r_type == R_SH_IMAGEBASE)
       addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
#endif

      val = 0;

      if (h == NULL)
       {
         asection *sec;

         /* There is nothing to do for an internal PCDISP reloc.  */
         if (rel->r_type == R_SH_PCDISP)
           continue;

         if (symndx == -1)
           {
             sec = bfd_abs_section_ptr;
             val = 0;
           }
         else
           {
             sec = sections[symndx];
              val = (sec->output_section->vma
                   + sec->output_offset
                   + sym->n_value
                   - sec->vma);
           }
       }
      else
       {
         if (h->root.type == bfd_link_hash_defined
             || h->root.type == bfd_link_hash_defweak)
           {
             asection *sec;

             sec = h->root.u.def.section;
             val = (h->root.u.def.value
                   + sec->output_section->vma
                   + sec->output_offset);
           }
         else if (! info->relocatable)
           {
             if (! ((*info->callbacks->undefined_symbol)
                   (info, h->root.root.string, input_bfd, input_section,
                    rel->r_vaddr - input_section->vma, TRUE)))
              return FALSE;
           }
       }

      rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
                                   contents,
                                   rel->r_vaddr - input_section->vma,
                                   val, addend);

      switch (rstat)
       {
       default:
         abort ();
       case bfd_reloc_ok:
         break;
       case bfd_reloc_overflow:
         {
           const char *name;
           char buf[SYMNMLEN + 1];

           if (symndx == -1)
             name = "*ABS*";
           else if (h != NULL)
             name = NULL;
           else if (sym->_n._n_n._n_zeroes == 0
                   && sym->_n._n_n._n_offset != 0)
             name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
           else
             {
              strncpy (buf, sym->_n._n_name, SYMNMLEN);
              buf[SYMNMLEN] = '\0';
              name = buf;
             }

           if (! ((*info->callbacks->reloc_overflow)
                 (info, (h ? &h->root : NULL), name, howto->name,
                  (bfd_vma) 0, input_bfd, input_section,
                  rel->r_vaddr - input_section->vma)))
             return FALSE;
         }
       }
    }

  return TRUE;
}

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static bfd_boolean sh_swap_insns ( bfd abfd,
asection sec,
PTR  relocs,
bfd_byte contents,
bfd_vma  addr 
) [static]

Definition at line 2628 of file coff-sh.c.

{
  struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
  unsigned short i1, i2;
  struct internal_reloc *irel, *irelend;

  /* Swap the instructions themselves.  */
  i1 = bfd_get_16 (abfd, contents + addr);
  i2 = bfd_get_16 (abfd, contents + addr + 2);
  bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
  bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);

  /* Adjust all reloc addresses.  */
  irelend = internal_relocs + sec->reloc_count;
  for (irel = internal_relocs; irel < irelend; irel++)
    {
      int type, add;

      /* There are a few special types of relocs that we don't want to
         adjust.  These relocs do not apply to the instruction itself,
         but are only associated with the address.  */
      type = irel->r_type;
      if (type == R_SH_ALIGN
         || type == R_SH_CODE
         || type == R_SH_DATA
         || type == R_SH_LABEL)
       continue;

      /* If an R_SH_USES reloc points to one of the addresses being
         swapped, we must adjust it.  It would be incorrect to do this
         for a jump, though, since we want to execute both
         instructions after the jump.  (We have avoided swapping
         around a label, so the jump will not wind up executing an
         instruction it shouldn't).  */
      if (type == R_SH_USES)
       {
         bfd_vma off;

         off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
         if (off == addr)
           irel->r_offset += 2;
         else if (off == addr + 2)
           irel->r_offset -= 2;
       }

      if (irel->r_vaddr - sec->vma == addr)
       {
         irel->r_vaddr += 2;
         add = -2;
       }
      else if (irel->r_vaddr - sec->vma == addr + 2)
       {
         irel->r_vaddr -= 2;
         add = 2;
       }
      else
       add = 0;

      if (add != 0)
       {
         bfd_byte *loc;
         unsigned short insn, oinsn;
         bfd_boolean overflow;

         loc = contents + irel->r_vaddr - sec->vma;
         overflow = FALSE;
         switch (type)
           {
           default:
             break;

           case R_SH_PCDISP8BY2:
           case R_SH_PCRELIMM8BY2:
             insn = bfd_get_16 (abfd, loc);
             oinsn = insn;
             insn += add / 2;
             if ((oinsn & 0xff00) != (insn & 0xff00))
              overflow = TRUE;
             bfd_put_16 (abfd, (bfd_vma) insn, loc);
             break;

           case R_SH_PCDISP:
             insn = bfd_get_16 (abfd, loc);
             oinsn = insn;
             insn += add / 2;
             if ((oinsn & 0xf000) != (insn & 0xf000))
              overflow = TRUE;
             bfd_put_16 (abfd, (bfd_vma) insn, loc);
             break;

           case R_SH_PCRELIMM8BY4:
             /* This reloc ignores the least significant 3 bits of
                 the program counter before adding in the offset.
                 This means that if ADDR is at an even address, the
                 swap will not affect the offset.  If ADDR is an at an
                 odd address, then the instruction will be crossing a
                 four byte boundary, and must be adjusted.  */
             if ((addr & 3) != 0)
              {
                insn = bfd_get_16 (abfd, loc);
                oinsn = insn;
                insn += add / 2;
                if ((oinsn & 0xff00) != (insn & 0xff00))
                  overflow = TRUE;
                bfd_put_16 (abfd, (bfd_vma) insn, loc);
              }

             break;
           }

         if (overflow)
           {
             ((*_bfd_error_handler)
              ("%B: 0x%lx: fatal: reloc overflow while relaxing",
              abfd, (unsigned long) irel->r_vaddr));
             bfd_set_error (bfd_error_bad_value);
             return FALSE;
           }
       }
    }

  return TRUE;
}

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Variable Documentation

Definition at line 3114 of file coff-sh.c.

reloc_howto_type sh_coff_howtos[] [static]

Definition at line 101 of file coff-sh.c.

struct sh_major_opcode[] [static]
Initial value:
{
  { MAP (sh_opcode0) },
  { MAP (sh_opcode1) },
  { MAP (sh_opcode2) },
  { MAP (sh_opcode3) },
  { MAP (sh_opcode4) },
  { MAP (sh_opcode5) },
  { MAP (sh_opcode6) },
  { MAP (sh_opcode7) },
  { MAP (sh_opcode8) },
  { MAP (sh_opcode9) },
  { MAP (sh_opcodea) },
  { MAP (sh_opcodeb) },
  { MAP (sh_opcodec) },
  { MAP (sh_opcoded) },
  { MAP (sh_opcodee) },
  { MAP (sh_opcodef) }
}

Definition at line 2001 of file coff-sh.c.

static struct sh_minor_opcode [static]
Initial value:
{
  { MAP (sh_opcode00), 0xffff },
  { MAP (sh_opcode01), 0xf0ff },
  { MAP (sh_opcode02), 0xf00f }
}

Definition at line 1687 of file coff-sh.c.

static struct sh_opcode [static]
Initial value:
{
  { 0x0008, SETSSP },                     
  { 0x0009, 0 },                   
  { 0x000b, BRANCH | DELAY | USESSP },    
  { 0x0018, SETSSP },                     
  { 0x0019, SETSSP },                     
  { 0x001b, 0 },                   
  { 0x0028, SETSSP },                     
  { 0x002b, BRANCH | DELAY | SETSSP },    
  { 0x0038, USESSP | SETSSP },            
  { 0x0048, SETSSP },                     
  { 0x0058, SETSSP }               
}

Definition at line 1641 of file coff-sh.c.

Initial value:

Definition at line 487 of file coff-sh.c.

Definition at line 3165 of file coff-sh.c.

Definition at line 3209 of file coff-sh.c.