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cell-binutils  2.17cvs20070401
bfin-dis.c
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00001 /* Disassemble ADI Blackfin Instructions.
00002    Copyright 2005 Free Software Foundation, Inc.
00003 
00004    This program is free software; you can redistribute it and/or modify
00005    it under the terms of the GNU General Public License as published by
00006    the Free Software Foundation; either version 2 of the License, or
00007    (at your option) any later version.
00008 
00009    This program is distributed in the hope that it will be useful,
00010    but WITHOUT ANY WARRANTY; without even the implied warranty of
00011    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
00012    GNU General Public License for more details.
00013 
00014    You should have received a copy of the GNU General Public License
00015    along with this program; if not, write to the Free Software
00016    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
00017    MA 02110-1301, USA.  */
00018 
00019 #include <stdio.h>
00020 #include <stdlib.h>
00021 #include <string.h>
00022 
00023 #include "opcode/bfin.h"
00024 
00025 #define M_S2RND 1
00026 #define M_T     2
00027 #define M_W32   3
00028 #define M_FU    4
00029 #define M_TFU   6
00030 #define M_IS    8
00031 #define M_ISS2  9
00032 #define M_IH    11
00033 #define M_IU    12
00034 
00035 #ifndef PRINTF
00036 #define PRINTF printf
00037 #endif
00038 
00039 #ifndef EXIT
00040 #define EXIT exit
00041 #endif
00042 
00043 typedef long TIword;
00044 
00045 #define HOST_LONG_WORD_SIZE (sizeof (long) * 8)
00046 #define XFIELD(w,p,s)       (((w) & ((1 << (s)) - 1) << (p)) >> (p))
00047 #define SIGNEXTEND(v, n)    ((v << (HOST_LONG_WORD_SIZE - (n))) >> (HOST_LONG_WORD_SIZE - (n)))
00048 #define MASKBITS(val, bits) (val & ((1 << bits) - 1))
00049 
00050 #include "dis-asm.h"
00051 
00052 typedef enum
00053 {
00054   c_0, c_1, c_4, c_2, c_uimm2, c_uimm3, c_imm3, c_pcrel4,
00055   c_imm4, c_uimm4s4, c_uimm4, c_uimm4s2, c_negimm5s4, c_imm5, c_uimm5, c_imm6,
00056   c_imm7, c_imm8, c_uimm8, c_pcrel8, c_uimm8s4, c_pcrel8s4, c_lppcrel10, c_pcrel10,
00057   c_pcrel12, c_imm16s4, c_luimm16, c_imm16, c_huimm16, c_rimm16, c_imm16s2, c_uimm16s4,
00058   c_uimm16, c_pcrel24,
00059 } const_forms_t;
00060 
00061 static struct
00062 {
00063   char *name;
00064   int nbits;
00065   char reloc;
00066   char issigned;
00067   char pcrel;
00068   char scale;
00069   char offset;
00070   char negative;
00071   char positive;
00072 } constant_formats[] =
00073 {
00074   { "0", 0, 0, 1, 0, 0, 0, 0, 0},
00075   { "1", 0, 0, 1, 0, 0, 0, 0, 0},
00076   { "4", 0, 0, 1, 0, 0, 0, 0, 0},
00077   { "2", 0, 0, 1, 0, 0, 0, 0, 0},
00078   { "uimm2", 2, 0, 0, 0, 0, 0, 0, 0},
00079   { "uimm3", 3, 0, 0, 0, 0, 0, 0, 0},
00080   { "imm3", 3, 0, 1, 0, 0, 0, 0, 0},
00081   { "pcrel4", 4, 1, 0, 1, 1, 0, 0, 0},
00082   { "imm4", 4, 0, 1, 0, 0, 0, 0, 0},
00083   { "uimm4s4", 4, 0, 0, 0, 2, 0, 0, 1},
00084   { "uimm4", 4, 0, 0, 0, 0, 0, 0, 0},
00085   { "uimm4s2", 4, 0, 0, 0, 1, 0, 0, 1},
00086   { "negimm5s4", 5, 0, 1, 0, 2, 0, 1, 0},
00087   { "imm5", 5, 0, 1, 0, 0, 0, 0, 0},
00088   { "uimm5", 5, 0, 0, 0, 0, 0, 0, 0},
00089   { "imm6", 6, 0, 1, 0, 0, 0, 0, 0},
00090   { "imm7", 7, 0, 1, 0, 0, 0, 0, 0},
00091   { "imm8", 8, 0, 1, 0, 0, 0, 0, 0},
00092   { "uimm8", 8, 0, 0, 0, 0, 0, 0, 0},
00093   { "pcrel8", 8, 1, 0, 1, 1, 0, 0, 0},
00094   { "uimm8s4", 8, 0, 0, 0, 2, 0, 0, 0},
00095   { "pcrel8s4", 8, 1, 1, 1, 2, 0, 0, 0},
00096   { "lppcrel10", 10, 1, 0, 1, 1, 0, 0, 0},
00097   { "pcrel10", 10, 1, 1, 1, 1, 0, 0, 0},
00098   { "pcrel12", 12, 1, 1, 1, 1, 0, 0, 0},
00099   { "imm16s4", 16, 0, 1, 0, 2, 0, 0, 0},
00100   { "luimm16", 16, 1, 0, 0, 0, 0, 0, 0},
00101   { "imm16", 16, 0, 1, 0, 0, 0, 0, 0},
00102   { "huimm16", 16, 1, 0, 0, 0, 0, 0, 0},
00103   { "rimm16", 16, 1, 1, 0, 0, 0, 0, 0},
00104   { "imm16s2", 16, 0, 1, 0, 1, 0, 0, 0},
00105   { "uimm16s4", 16, 0, 0, 0, 2, 0, 0, 0},
00106   { "uimm16", 16, 0, 0, 0, 0, 0, 0, 0},
00107   { "pcrel24", 24, 1, 1, 1, 1, 0, 0, 0}
00108 };
00109 
00110 int _print_insn_bfin (bfd_vma pc, disassemble_info * outf);
00111 int print_insn_bfin (bfd_vma pc, disassemble_info * outf);
00112 
00113 static char *
00114 fmtconst (const_forms_t cf, TIword x, bfd_vma pc, disassemble_info * outf)
00115 {
00116   static char buf[60];
00117 
00118   if (constant_formats[cf].reloc)
00119     {
00120       bfd_vma ea = (((constant_formats[cf].pcrel ? SIGNEXTEND (x, constant_formats[cf].nbits)
00121                     : x) + constant_formats[cf].offset) << constant_formats[cf].scale);
00122       if (constant_formats[cf].pcrel)
00123        ea += pc;
00124 
00125       outf->print_address_func (ea, outf);
00126       return "";
00127     }
00128 
00129   /* Negative constants have an implied sign bit.  */
00130   if (constant_formats[cf].negative)
00131     {
00132       int nb = constant_formats[cf].nbits + 1;
00133 
00134       x = x | (1 << constant_formats[cf].nbits);
00135       x = SIGNEXTEND (x, nb);
00136     }
00137   else
00138     x = constant_formats[cf].issigned ? SIGNEXTEND (x, constant_formats[cf].nbits) : x;
00139 
00140   if (constant_formats[cf].offset)
00141     x += constant_formats[cf].offset;
00142 
00143   if (constant_formats[cf].scale)
00144     x <<= constant_formats[cf].scale;
00145 
00146   if (constant_formats[cf].issigned && x < 0)
00147     sprintf (buf, "%ld", x);
00148   else
00149     sprintf (buf, "0x%lx", x);
00150 
00151   return buf;
00152 }
00153 
00154 enum machine_registers
00155 {
00156   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
00157   REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
00158   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
00159   REG_R1_0, REG_R3_2, REG_R5_4, REG_R7_6, REG_P0, REG_P1, REG_P2, REG_P3,
00160   REG_P4, REG_P5, REG_SP, REG_FP, REG_A0x, REG_A1x, REG_A0w, REG_A1w,
00161   REG_A0, REG_A1, REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1,
00162   REG_M2, REG_M3, REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1,
00163   REG_L2, REG_L3,
00164   REG_AZ, REG_AN, REG_AC0, REG_AC1, REG_AV0, REG_AV1, REG_AV0S, REG_AV1S,
00165   REG_AQ, REG_V, REG_VS,
00166   REG_sftreset, REG_omode, REG_excause, REG_emucause, REG_idle_req, REG_hwerrcause, REG_CC, REG_LC0,
00167   REG_LC1, REG_GP, REG_ASTAT, REG_RETS, REG_LT0, REG_LB0, REG_LT1, REG_LB1,
00168   REG_CYCLES, REG_CYCLES2, REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN,
00169   REG_RETE, REG_EMUDAT, REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6,
00170   REG_BR7, REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
00171   REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
00172   REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
00173   REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
00174   REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_MH2, REG_MH3,
00175   REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
00176   REG_LASTREG,
00177 };
00178 
00179 enum reg_class
00180 {
00181   rc_dregs_lo, rc_dregs_hi, rc_dregs, rc_dregs_pair, rc_pregs, rc_spfp, rc_dregs_hilo, rc_accum_ext,
00182   rc_accum_word, rc_accum, rc_iregs, rc_mregs, rc_bregs, rc_lregs, rc_dpregs, rc_gregs,
00183   rc_regs, rc_statbits, rc_ignore_bits, rc_ccstat, rc_counters, rc_dregs2_sysregs1, rc_open, rc_sysregs2,
00184   rc_sysregs3, rc_allregs,
00185   LIM_REG_CLASSES
00186 };
00187 
00188 static char *reg_names[] =
00189 {
00190   "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L",
00191   "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H",
00192   "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
00193   "R1:0", "R3:2", "R5:4", "R7:6", "P0", "P1", "P2", "P3",
00194   "P4", "P5", "SP", "FP", "A0.x", "A1.x", "A0.w", "A1.w",
00195   "A0", "A1", "I0", "I1", "I2", "I3", "M0", "M1",
00196   "M2", "M3", "B0", "B1", "B2", "B3", "L0", "L1",
00197   "L2", "L3",
00198   "AZ", "AN", "AC0", "AC1", "AV0", "AV1", "AV0S", "AV1S",
00199   "AQ", "V", "VS",
00200   "sftreset", "omode", "excause", "emucause", "idle_req", "hwerrcause", "CC", "LC0",
00201   "LC1", "GP", "ASTAT", "RETS", "LT0", "LB0", "LT1", "LB1",
00202   "CYCLES", "CYCLES2", "USP", "SEQSTAT", "SYSCFG", "RETI", "RETX", "RETN",
00203   "RETE", "EMUDAT",
00204   "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B",
00205   "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L",
00206   "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H",
00207   "I0.L", "I1.L", "I2.L", "I3.L", "M0.L", "M1.L", "M2.L", "M3.L",
00208   "B0.L", "B1.L", "B2.L", "B3.L", "L0.L", "L1.L", "L2.L", "L3.L",
00209   "I0.H", "I1.H", "I2.H", "I3.H", "M0.H", "M1.H", "M2.H", "M3.H",
00210   "B0.H", "B1.H", "B2.H", "B3.H", "L0.H", "L1.H", "L2.H", "L3.H",
00211   "LASTREG",
00212   0
00213 };
00214 
00215 #define REGNAME(x) ((x) < REG_LASTREG ? (reg_names[x]) : "...... Illegal register .......")
00216 
00217 /* RL(0..7).  */
00218 static enum machine_registers decode_dregs_lo[] =
00219 {
00220   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
00221 };
00222 
00223 #define dregs_lo(x) REGNAME (decode_dregs_lo[(x) & 7])
00224 
00225 /* RH(0..7).  */
00226 static enum machine_registers decode_dregs_hi[] =
00227 {
00228   REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
00229 };
00230 
00231 #define dregs_hi(x) REGNAME (decode_dregs_hi[(x) & 7])
00232 
00233 /* R(0..7).  */
00234 static enum machine_registers decode_dregs[] =
00235 {
00236   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
00237 };
00238 
00239 #define dregs(x) REGNAME (decode_dregs[(x) & 7])
00240 
00241 /* R BYTE(0..7).  */
00242 static enum machine_registers decode_dregs_byte[] =
00243 {
00244   REG_BR0, REG_BR1, REG_BR2, REG_BR3, REG_BR4, REG_BR5, REG_BR6, REG_BR7,
00245 };
00246 
00247 #define dregs_byte(x) REGNAME (decode_dregs_byte[(x) & 7])
00248 #define dregs_pair(x) REGNAME (decode_dregs_pair[(x) & 7])
00249 
00250 /* P(0..5) SP FP.  */
00251 static enum machine_registers decode_pregs[] =
00252 {
00253   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
00254 };
00255 
00256 #define pregs(x)     REGNAME (decode_pregs[(x) & 7])
00257 #define spfp(x)             REGNAME (decode_spfp[(x) & 1])
00258 #define dregs_hilo(x,i)     REGNAME (decode_dregs_hilo[((i) << 3)|x])
00259 #define accum_ext(x) REGNAME (decode_accum_ext[(x) & 1])
00260 #define accum_word(x)       REGNAME (decode_accum_word[(x) & 1])
00261 #define accum(x)     REGNAME (decode_accum[(x) & 1])
00262 
00263 /* I(0..3).  */
00264 static enum machine_registers decode_iregs[] =
00265 {
00266   REG_I0, REG_I1, REG_I2, REG_I3,
00267 };
00268 
00269 #define iregs(x) REGNAME (decode_iregs[(x) & 3])
00270 
00271 /* M(0..3).  */
00272 static enum machine_registers decode_mregs[] =
00273 {
00274   REG_M0, REG_M1, REG_M2, REG_M3,
00275 };
00276 
00277 #define mregs(x) REGNAME (decode_mregs[(x) & 3])
00278 #define bregs(x) REGNAME (decode_bregs[(x) & 3])
00279 #define lregs(x) REGNAME (decode_lregs[(x) & 3])
00280 
00281 /* dregs pregs.  */
00282 static enum machine_registers decode_dpregs[] =
00283 {
00284   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
00285   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
00286 };
00287 
00288 #define dpregs(x) REGNAME (decode_dpregs[(x) & 15])
00289 
00290 /* [dregs pregs].  */
00291 static enum machine_registers decode_gregs[] =
00292 {
00293   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
00294   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
00295 };
00296 
00297 #define gregs(x,i) REGNAME (decode_gregs[((i) << 3)|x])
00298 
00299 /* [dregs pregs (iregs mregs) (bregs lregs)].  */
00300 static enum machine_registers decode_regs[] =
00301 {
00302   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
00303   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
00304   REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
00305   REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
00306 };
00307 
00308 #define regs(x,i) REGNAME (decode_regs[((i) << 3)|x])
00309 
00310 /* [dregs pregs (iregs mregs) (bregs lregs) Low Half].  */
00311 static enum machine_registers decode_regs_lo[] =
00312 {
00313   REG_RL0, REG_RL1, REG_RL2, REG_RL3, REG_RL4, REG_RL5, REG_RL6, REG_RL7,
00314   REG_PL0, REG_PL1, REG_PL2, REG_PL3, REG_PL4, REG_PL5, REG_SLP, REG_FLP,
00315   REG_IL0, REG_IL1, REG_IL2, REG_IL3, REG_ML0, REG_ML1, REG_ML2, REG_ML3,
00316   REG_BL0, REG_BL1, REG_BL2, REG_BL3, REG_LL0, REG_LL1, REG_LL2, REG_LL3,
00317 };
00318 
00319 #define regs_lo(x,i) REGNAME (decode_regs_lo[((i) << 3)|x])
00320 /* [dregs pregs (iregs mregs) (bregs lregs) High Half].  */
00321 static enum machine_registers decode_regs_hi[] =
00322 {
00323   REG_RH0, REG_RH1, REG_RH2, REG_RH3, REG_RH4, REG_RH5, REG_RH6, REG_RH7,
00324   REG_PH0, REG_PH1, REG_PH2, REG_PH3, REG_PH4, REG_PH5, REG_SHP, REG_FHP,
00325   REG_IH0, REG_IH1, REG_IH2, REG_IH3, REG_MH0, REG_MH1, REG_LH2, REG_MH3,
00326   REG_BH0, REG_BH1, REG_BH2, REG_BH3, REG_LH0, REG_LH1, REG_LH2, REG_LH3,
00327 };
00328 
00329 #define regs_hi(x,i) REGNAME (decode_regs_hi[((i) << 3)|x])
00330 
00331 static enum machine_registers decode_statbits[] =
00332 {
00333   REG_AZ, REG_AN, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AQ, REG_LASTREG,
00334   REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_AC0, REG_AC1, REG_LASTREG, REG_LASTREG,
00335   REG_AV0, REG_AV0S, REG_AV1, REG_AV1S, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
00336   REG_V, REG_VS, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
00337 };
00338 
00339 #define statbits(x)  REGNAME (decode_statbits[(x) & 31])
00340 #define ignore_bits(x)      REGNAME (decode_ignore_bits[(x) & 7])
00341 #define ccstat(x)    REGNAME (decode_ccstat[(x) & 0])
00342 
00343 /* LC0 LC1.  */
00344 static enum machine_registers decode_counters[] =
00345 {
00346   REG_LC0, REG_LC1,
00347 };
00348 
00349 #define counters(x)        REGNAME (decode_counters[(x) & 1])
00350 #define dregs2_sysregs1(x) REGNAME (decode_dregs2_sysregs1[(x) & 7])
00351 
00352 /* [dregs pregs (iregs mregs) (bregs lregs)
00353    dregs2_sysregs1 open sysregs2 sysregs3].  */
00354 static enum machine_registers decode_allregs[] =
00355 {
00356   REG_R0, REG_R1, REG_R2, REG_R3, REG_R4, REG_R5, REG_R6, REG_R7,
00357   REG_P0, REG_P1, REG_P2, REG_P3, REG_P4, REG_P5, REG_SP, REG_FP,
00358   REG_I0, REG_I1, REG_I2, REG_I3, REG_M0, REG_M1, REG_M2, REG_M3,
00359   REG_B0, REG_B1, REG_B2, REG_B3, REG_L0, REG_L1, REG_L2, REG_L3,
00360   REG_A0x, REG_A0w, REG_A1x, REG_A1w, REG_GP, REG_LASTREG, REG_ASTAT, REG_RETS,
00361   REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG, REG_LASTREG,
00362   REG_LC0, REG_LT0, REG_LB0, REG_LC1, REG_LT1, REG_LB1, REG_CYCLES, REG_CYCLES2,
00363   REG_USP, REG_SEQSTAT, REG_SYSCFG, REG_RETI, REG_RETX, REG_RETN, REG_RETE, REG_EMUDAT, REG_LASTREG,
00364 };
00365 
00366 #define allregs(x,i) REGNAME (decode_allregs[((i) << 3) | x])
00367 #define uimm16s4(x)  fmtconst (c_uimm16s4, x, 0, outf)
00368 #define pcrel4(x)    fmtconst (c_pcrel4, x, pc, outf)
00369 #define pcrel8(x)    fmtconst (c_pcrel8, x, pc, outf)
00370 #define pcrel8s4(x)  fmtconst (c_pcrel8s4, x, pc, outf)
00371 #define pcrel10(x)   fmtconst (c_pcrel10, x, pc, outf)
00372 #define pcrel12(x)   fmtconst (c_pcrel12, x, pc, outf)
00373 #define negimm5s4(x) fmtconst (c_negimm5s4, x, 0, outf)
00374 #define rimm16(x)    fmtconst (c_rimm16, x, 0, outf)
00375 #define huimm16(x)   fmtconst (c_huimm16, x, 0, outf)
00376 #define imm16(x)     fmtconst (c_imm16, x, 0, outf)
00377 #define uimm2(x)     fmtconst (c_uimm2, x, 0, outf)
00378 #define uimm3(x)     fmtconst (c_uimm3, x, 0, outf)
00379 #define luimm16(x)   fmtconst (c_luimm16, x, 0, outf)
00380 #define uimm4(x)     fmtconst (c_uimm4, x, 0, outf)
00381 #define uimm5(x)     fmtconst (c_uimm5, x, 0, outf)
00382 #define imm16s2(x)   fmtconst (c_imm16s2, x, 0, outf)
00383 #define uimm8(x)     fmtconst (c_uimm8, x, 0, outf)
00384 #define imm16s4(x)   fmtconst (c_imm16s4, x, 0, outf)
00385 #define uimm4s2(x)   fmtconst (c_uimm4s2, x, 0, outf)
00386 #define uimm4s4(x)   fmtconst (c_uimm4s4, x, 0, outf)
00387 #define lppcrel10(x) fmtconst (c_lppcrel10, x, pc, outf)
00388 #define imm3(x)             fmtconst (c_imm3, x, 0, outf)
00389 #define imm4(x)             fmtconst (c_imm4, x, 0, outf)
00390 #define uimm8s4(x)   fmtconst (c_uimm8s4, x, 0, outf)
00391 #define imm5(x)             fmtconst (c_imm5, x, 0, outf)
00392 #define imm6(x)             fmtconst (c_imm6, x, 0, outf)
00393 #define imm7(x)             fmtconst (c_imm7, x, 0, outf)
00394 #define imm8(x)             fmtconst (c_imm8, x, 0, outf)
00395 #define pcrel24(x)   fmtconst (c_pcrel24, x, pc, outf)
00396 #define uimm16(x)    fmtconst (c_uimm16, x, 0, outf)
00397 
00398 /* (arch.pm)arch_disassembler_functions.  */
00399 #ifndef OUTS
00400 #define OUTS(p, txt) ((p) ? (((txt)[0]) ? (p->fprintf_func)(p->stream, txt) :0) :0)
00401 #endif
00402 
00403 static void
00404 amod0 (int s0, int x0, disassemble_info *outf)
00405 {
00406   if (s0 == 1 && x0 == 0)
00407     OUTS (outf, "(S)");
00408   else if (s0 == 0 && x0 == 1)
00409     OUTS (outf, "(CO)");
00410   else if (s0 == 1 && x0 == 1)
00411     OUTS (outf, "(SCO)");
00412 }
00413 
00414 static void
00415 amod1 (int s0, int x0, disassemble_info *outf)
00416 {
00417   if (s0 == 0 && x0 == 0)
00418     OUTS (outf, "(NS)");
00419   else if (s0 == 1 && x0 == 0)
00420     OUTS (outf, "(S)");
00421 }
00422 
00423 static void
00424 amod0amod2 (int s0, int x0, int aop0, disassemble_info *outf)
00425 {
00426   if (s0 == 1 && x0 == 0 && aop0 == 0)
00427     OUTS (outf, "(S)");
00428   else if (s0 == 0 && x0 == 1 && aop0 == 0)
00429     OUTS (outf, "(CO)");
00430   else if (s0 == 1 && x0 == 1 && aop0 == 0)
00431     OUTS (outf, "(SCO)");
00432   else if (s0 == 0 && x0 == 0 && aop0 == 2)
00433     OUTS (outf, "(ASR)");
00434   else if (s0 == 1 && x0 == 0 && aop0 == 2)
00435     OUTS (outf, "(S,ASR)");
00436   else if (s0 == 0 && x0 == 1 && aop0 == 2)
00437     OUTS (outf, "(CO,ASR)");
00438   else if (s0 == 1 && x0 == 1 && aop0 == 2)
00439     OUTS (outf, "(SCO,ASR)");
00440   else if (s0 == 0 && x0 == 0 && aop0 == 3)
00441     OUTS (outf, "(ASL)");
00442   else if (s0 == 1 && x0 == 0 && aop0 == 3)
00443     OUTS (outf, "(S,ASL)");
00444   else if (s0 == 0 && x0 == 1 && aop0 == 3)
00445     OUTS (outf, "(CO,ASL)");
00446   else if (s0 == 1 && x0 == 1 && aop0 == 3)
00447     OUTS (outf, "(SCO,ASL)");
00448 }
00449 
00450 static void
00451 searchmod (int r0, disassemble_info *outf)
00452 {
00453   if (r0 == 0)
00454     OUTS (outf, "GT");
00455   else if (r0 == 1)
00456     OUTS (outf, "GE");
00457   else if (r0 == 2)
00458     OUTS (outf, "LT");
00459   else if (r0 == 3)
00460     OUTS (outf, "LE");
00461 }
00462 
00463 static void
00464 aligndir (int r0, disassemble_info *outf)
00465 {
00466   if (r0 == 1)
00467     OUTS (outf, "(R)");
00468 }
00469 
00470 static int
00471 decode_multfunc (int h0, int h1, int src0, int src1, disassemble_info * outf)
00472 {
00473   char *s0, *s1;
00474 
00475   if (h0)
00476     s0 = dregs_hi (src0);
00477   else
00478     s0 = dregs_lo (src0);
00479 
00480   if (h1)
00481     s1 = dregs_hi (src1);
00482   else
00483     s1 = dregs_lo (src1);
00484 
00485   OUTS (outf, s0);
00486   OUTS (outf, " * ");
00487   OUTS (outf, s1);
00488   return 0;
00489 }
00490 
00491 static int
00492 decode_macfunc (int which, int op, int h0, int h1, int src0, int src1, disassemble_info * outf)
00493 {
00494   char *a;
00495   char *sop = "<unknown op>";
00496 
00497   if (which)
00498     a = "a1";
00499   else
00500     a = "a0";
00501 
00502   if (op == 3)
00503     {
00504       OUTS (outf, a);
00505       return 0;
00506     }
00507 
00508   switch (op)
00509     {
00510     case 0: sop = "=";   break;
00511     case 1: sop = "+=";  break;
00512     case 2: sop = "-=";  break;
00513     default: break;
00514     }
00515 
00516   OUTS (outf, a);
00517   OUTS (outf, " ");
00518   OUTS (outf, sop);
00519   OUTS (outf, " ");
00520   decode_multfunc (h0, h1, src0, src1, outf);
00521 
00522   return 0;
00523 }
00524 
00525 static void
00526 decode_optmode (int mod, int MM, disassemble_info *outf)
00527 {
00528   if (mod == 0 && MM == 0)
00529     return;
00530 
00531   OUTS (outf, " (");
00532 
00533   if (MM && !mod)
00534     {
00535       OUTS (outf, "M)");
00536       return;
00537     }
00538 
00539   if (MM)
00540     OUTS (outf, "M, ");
00541 
00542   if (mod == M_S2RND)
00543     OUTS (outf, "S2RND");
00544   else if (mod == M_T)
00545     OUTS (outf, "T");
00546   else if (mod == M_W32)
00547     OUTS (outf, "W32");
00548   else if (mod == M_FU)
00549     OUTS (outf, "FU");
00550   else if (mod == M_TFU)
00551     OUTS (outf, "TFU");
00552   else if (mod == M_IS)
00553     OUTS (outf, "IS");
00554   else if (mod == M_ISS2)
00555     OUTS (outf, "ISS2");
00556   else if (mod == M_IH)
00557     OUTS (outf, "IH");
00558   else if (mod == M_IU)
00559     OUTS (outf, "IU");
00560   else
00561     abort ();
00562 
00563   OUTS (outf, ")");
00564 }
00565 
00566 static int
00567 decode_ProgCtrl_0 (TIword iw0, disassemble_info *outf)
00568 {
00569   /* ProgCtrl
00570      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
00571      | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.prgfunc.......|.poprnd........|
00572      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
00573   int poprnd  = ((iw0 >> ProgCtrl_poprnd_bits) & ProgCtrl_poprnd_mask);
00574   int prgfunc = ((iw0 >> ProgCtrl_prgfunc_bits) & ProgCtrl_prgfunc_mask);
00575 
00576   if (prgfunc == 0 && poprnd == 0)
00577     OUTS (outf, "NOP");
00578   else if (prgfunc == 1 && poprnd == 0)
00579     OUTS (outf, "RTS");
00580   else if (prgfunc == 1 && poprnd == 1)
00581     OUTS (outf, "RTI");
00582   else if (prgfunc == 1 && poprnd == 2)
00583     OUTS (outf, "RTX");
00584   else if (prgfunc == 1 && poprnd == 3)
00585     OUTS (outf, "RTN");
00586   else if (prgfunc == 1 && poprnd == 4)
00587     OUTS (outf, "RTE");
00588   else if (prgfunc == 2 && poprnd == 0)
00589     OUTS (outf, "IDLE");
00590   else if (prgfunc == 2 && poprnd == 3)
00591     OUTS (outf, "CSYNC");
00592   else if (prgfunc == 2 && poprnd == 4)
00593     OUTS (outf, "SSYNC");
00594   else if (prgfunc == 2 && poprnd == 5)
00595     OUTS (outf, "EMUEXCPT");
00596   else if (prgfunc == 3)
00597     {
00598       OUTS (outf, "CLI  ");
00599       OUTS (outf, dregs (poprnd));
00600     }
00601   else if (prgfunc == 4)
00602     {
00603       OUTS (outf, "STI  ");
00604       OUTS (outf, dregs (poprnd));
00605     }
00606   else if (prgfunc == 5)
00607     {
00608       OUTS (outf, "JUMP  (");
00609       OUTS (outf, pregs (poprnd));
00610       OUTS (outf, ")");
00611     }
00612   else if (prgfunc == 6)
00613     {
00614       OUTS (outf, "CALL  (");
00615       OUTS (outf, pregs (poprnd));
00616       OUTS (outf, ")");
00617     }
00618   else if (prgfunc == 7)
00619     {
00620       OUTS (outf, "CALL  (PC+");
00621       OUTS (outf, pregs (poprnd));
00622       OUTS (outf, ")");
00623     }
00624   else if (prgfunc == 8)
00625     {
00626       OUTS (outf, "JUMP  (PC+");
00627       OUTS (outf, pregs (poprnd));
00628       OUTS (outf, ")");
00629     }
00630   else if (prgfunc == 9)
00631     {
00632       OUTS (outf, "RAISE  ");
00633       OUTS (outf, uimm4 (poprnd));
00634     }
00635   else if (prgfunc == 10)
00636     {
00637       OUTS (outf, "EXCPT  ");
00638       OUTS (outf, uimm4 (poprnd));
00639     }
00640   else if (prgfunc == 11)
00641     {
00642       OUTS (outf, "TESTSET  (");
00643       OUTS (outf, pregs (poprnd));
00644       OUTS (outf, ")");
00645     }
00646   else
00647     return 0;
00648   return 2;
00649 }
00650 
00651 static int
00652 decode_CaCTRL_0 (TIword iw0, disassemble_info *outf)
00653 {
00654   /* CaCTRL
00655      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
00656      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |.a.|.op....|.reg.......|
00657      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
00658   int a   = ((iw0 >> CaCTRL_a_bits) & CaCTRL_a_mask);
00659   int op  = ((iw0 >> CaCTRL_op_bits) & CaCTRL_op_mask);
00660   int reg = ((iw0 >> CaCTRL_reg_bits) & CaCTRL_reg_mask);
00661 
00662   if (a == 0 && op == 0)
00663     {
00664       OUTS (outf, "PREFETCH[");
00665       OUTS (outf, pregs (reg));
00666       OUTS (outf, "]");
00667     }
00668   else if (a == 0 && op == 1)
00669     {
00670       OUTS (outf, "FLUSHINV[");
00671       OUTS (outf, pregs (reg));
00672       OUTS (outf, "]");
00673     }
00674   else if (a == 0 && op == 2)
00675     {
00676       OUTS (outf, "FLUSH[");
00677       OUTS (outf, pregs (reg));
00678       OUTS (outf, "]");
00679     }
00680   else if (a == 0 && op == 3)
00681     {
00682       OUTS (outf, "IFLUSH[");
00683       OUTS (outf, pregs (reg));
00684       OUTS (outf, "]");
00685     }
00686   else if (a == 1 && op == 0)
00687     {
00688       OUTS (outf, "PREFETCH[");
00689       OUTS (outf, pregs (reg));
00690       OUTS (outf, "++]");
00691     }
00692   else if (a == 1 && op == 1)
00693     {
00694       OUTS (outf, "FLUSHINV[");
00695       OUTS (outf, pregs (reg));
00696       OUTS (outf, "++]");
00697     }
00698   else if (a == 1 && op == 2)
00699     {
00700       OUTS (outf, "FLUSH[");
00701       OUTS (outf, pregs (reg));
00702       OUTS (outf, "++]");
00703     }
00704   else if (a == 1 && op == 3)
00705     {
00706       OUTS (outf, "IFLUSH[");
00707       OUTS (outf, pregs (reg));
00708       OUTS (outf, "++]");
00709     }
00710   else
00711     return 0;
00712   return 2;
00713 }
00714 
00715 static int
00716 decode_PushPopReg_0 (TIword iw0, disassemble_info *outf)
00717 {
00718   /* PushPopReg
00719      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
00720      | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.W.|.grp.......|.reg.......|
00721      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
00722   int W   = ((iw0 >> PushPopReg_W_bits) & PushPopReg_W_mask);
00723   int grp = ((iw0 >> PushPopReg_grp_bits) & PushPopReg_grp_mask);
00724   int reg = ((iw0 >> PushPopReg_reg_bits) & PushPopReg_reg_mask);
00725 
00726   if (W == 0)
00727     {
00728       OUTS (outf, allregs (reg, grp));
00729       OUTS (outf, " = [SP++]");
00730     }
00731   else if (W == 1)
00732     {
00733       OUTS (outf, "[--SP] = ");
00734       OUTS (outf, allregs (reg, grp));
00735     }
00736   else
00737     return 0;
00738   return 2;
00739 }
00740 
00741 static int
00742 decode_PushPopMultiple_0 (TIword iw0, disassemble_info *outf)
00743 {
00744   /* PushPopMultiple
00745      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
00746      | 0 | 0 | 0 | 0 | 0 | 1 | 0 |.d.|.p.|.W.|.dr........|.pr........|
00747      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
00748   int p  = ((iw0 >> PushPopMultiple_p_bits) & PushPopMultiple_p_mask);
00749   int d  = ((iw0 >> PushPopMultiple_d_bits) & PushPopMultiple_d_mask);
00750   int W  = ((iw0 >> PushPopMultiple_W_bits) & PushPopMultiple_W_mask);
00751   int dr = ((iw0 >> PushPopMultiple_dr_bits) & PushPopMultiple_dr_mask);
00752   int pr = ((iw0 >> PushPopMultiple_pr_bits) & PushPopMultiple_pr_mask);
00753   char ps[5], ds[5];
00754 
00755   sprintf (ps, "%d", pr);
00756   sprintf (ds, "%d", dr);
00757 
00758   if (W == 1 && d == 1 && p == 1)
00759     {
00760       OUTS (outf, "[--SP] = (R7:");
00761       OUTS (outf, ds);
00762       OUTS (outf, ", P5:");
00763       OUTS (outf, ps);
00764       OUTS (outf, ")");
00765     }
00766   else if (W == 1 && d == 1 && p == 0)
00767     {
00768       OUTS (outf, "[--SP] = (R7:");
00769       OUTS (outf, ds);
00770       OUTS (outf, ")");
00771     }
00772   else if (W == 1 && d == 0 && p == 1)
00773     {
00774       OUTS (outf, "[--SP] = (P5:");
00775       OUTS (outf, ps);
00776       OUTS (outf, ")");
00777     }
00778   else if (W == 0 && d == 1 && p == 1)
00779     {
00780       OUTS (outf, "(R7:");
00781       OUTS (outf, ds);
00782       OUTS (outf, ", P5:");
00783       OUTS (outf, ps);
00784       OUTS (outf, ") = [SP++]");
00785     }
00786   else if (W == 0 && d == 1 && p == 0)
00787     {
00788       OUTS (outf, "(R7:");
00789       OUTS (outf, ds);
00790       OUTS (outf, ") = [SP++]");
00791     }
00792   else if (W == 0 && d == 0 && p == 1)
00793     {
00794       OUTS (outf, "(P5:");
00795       OUTS (outf, ps);
00796       OUTS (outf, ") = [SP++]");
00797     }
00798   else
00799     return 0;
00800   return 2;
00801 }
00802 
00803 static int
00804 decode_ccMV_0 (TIword iw0, disassemble_info *outf)
00805 {
00806   /* ccMV
00807      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
00808      | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.T.|.d.|.s.|.dst.......|.src.......|
00809      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
00810   int s  = ((iw0 >> CCmv_s_bits) & CCmv_s_mask);
00811   int d  = ((iw0 >> CCmv_d_bits) & CCmv_d_mask);
00812   int T  = ((iw0 >> CCmv_T_bits) & CCmv_T_mask);
00813   int src = ((iw0 >> CCmv_src_bits) & CCmv_src_mask);
00814   int dst = ((iw0 >> CCmv_dst_bits) & CCmv_dst_mask);
00815 
00816   if (T == 1)
00817     {
00818       OUTS (outf, "IF CC ");
00819       OUTS (outf, gregs (dst, d));
00820       OUTS (outf, " = ");
00821       OUTS (outf, gregs (src, s));
00822     }
00823   else if (T == 0)
00824     {
00825       OUTS (outf, "IF ! CC ");
00826       OUTS (outf, gregs (dst, d));
00827       OUTS (outf, " = ");
00828       OUTS (outf, gregs (src, s));
00829     }
00830   else
00831     return 0;
00832   return 2;
00833 }
00834 
00835 static int
00836 decode_CCflag_0 (TIword iw0, disassemble_info *outf)
00837 {
00838   /* CCflag
00839      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
00840      | 0 | 0 | 0 | 0 | 1 |.I.|.opc.......|.G.|.y.........|.x.........|
00841      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
00842   int x = ((iw0 >> CCflag_x_bits) & CCflag_x_mask);
00843   int y = ((iw0 >> CCflag_y_bits) & CCflag_y_mask);
00844   int I = ((iw0 >> CCflag_I_bits) & CCflag_I_mask);
00845   int G = ((iw0 >> CCflag_G_bits) & CCflag_G_mask);
00846   int opc = ((iw0 >> CCflag_opc_bits) & CCflag_opc_mask);
00847 
00848   if (opc == 0 && I == 0 && G == 0)
00849     {
00850       OUTS (outf, "CC=");
00851       OUTS (outf, dregs (x));
00852       OUTS (outf, "==");
00853       OUTS (outf, dregs (y));
00854     }
00855   else if (opc == 1 && I == 0 && G == 0)
00856     {
00857       OUTS (outf, "CC=");
00858       OUTS (outf, dregs (x));
00859       OUTS (outf, "<");
00860       OUTS (outf, dregs (y));
00861     }
00862   else if (opc == 2 && I == 0 && G == 0)
00863     {
00864       OUTS (outf, "CC=");
00865       OUTS (outf, dregs (x));
00866       OUTS (outf, "<=");
00867       OUTS (outf, dregs (y));
00868     }
00869   else if (opc == 3 && I == 0 && G == 0)
00870     {
00871       OUTS (outf, "CC=");
00872       OUTS (outf, dregs (x));
00873       OUTS (outf, "<");
00874       OUTS (outf, dregs (y));
00875       OUTS (outf, "(IU)");
00876     }
00877   else if (opc == 4 && I == 0 && G == 0)
00878     {
00879       OUTS (outf, "CC=");
00880       OUTS (outf, dregs (x));
00881       OUTS (outf, "<=");
00882       OUTS (outf, dregs (y));
00883       OUTS (outf, "(IU)");
00884     }
00885   else if (opc == 0 && I == 1 && G == 0)
00886     {
00887       OUTS (outf, "CC=");
00888       OUTS (outf, dregs (x));
00889       OUTS (outf, "==");
00890       OUTS (outf, imm3 (y));
00891     }
00892   else if (opc == 1 && I == 1 && G == 0)
00893     {
00894       OUTS (outf, "CC=");
00895       OUTS (outf, dregs (x));
00896       OUTS (outf, "<");
00897       OUTS (outf, imm3 (y));
00898     }
00899   else if (opc == 2 && I == 1 && G == 0)
00900     {
00901       OUTS (outf, "CC=");
00902       OUTS (outf, dregs (x));
00903       OUTS (outf, "<=");
00904       OUTS (outf, imm3 (y));
00905     }
00906   else if (opc == 3 && I == 1 && G == 0)
00907     {
00908       OUTS (outf, "CC=");
00909       OUTS (outf, dregs (x));
00910       OUTS (outf, "<");
00911       OUTS (outf, uimm3 (y));
00912       OUTS (outf, "(IU)");
00913     }
00914   else if (opc == 4 && I == 1 && G == 0)
00915     {
00916       OUTS (outf, "CC=");
00917       OUTS (outf, dregs (x));
00918       OUTS (outf, "<=");
00919       OUTS (outf, uimm3 (y));
00920       OUTS (outf, "(IU)");
00921     }
00922   else if (opc == 0 && I == 0 && G == 1)
00923     {
00924       OUTS (outf, "CC=");
00925       OUTS (outf, pregs (x));
00926       OUTS (outf, "==");
00927       OUTS (outf, pregs (y));
00928     }
00929   else if (opc == 1 && I == 0 && G == 1)
00930     {
00931       OUTS (outf, "CC=");
00932       OUTS (outf, pregs (x));
00933       OUTS (outf, "<");
00934       OUTS (outf, pregs (y));
00935     }
00936   else if (opc == 2 && I == 0 && G == 1)
00937     {
00938       OUTS (outf, "CC=");
00939       OUTS (outf, pregs (x));
00940       OUTS (outf, "<=");
00941       OUTS (outf, pregs (y));
00942     }
00943   else if (opc == 3 && I == 0 && G == 1)
00944     {
00945       OUTS (outf, "CC=");
00946       OUTS (outf, pregs (x));
00947       OUTS (outf, "<");
00948       OUTS (outf, pregs (y));
00949       OUTS (outf, "(IU)");
00950     }
00951   else if (opc == 4 && I == 0 && G == 1)
00952     {
00953       OUTS (outf, "CC=");
00954       OUTS (outf, pregs (x));
00955       OUTS (outf, "<=");
00956       OUTS (outf, pregs (y));
00957       OUTS (outf, "(IU)");
00958     }
00959   else if (opc == 0 && I == 1 && G == 1)
00960     {
00961       OUTS (outf, "CC=");
00962       OUTS (outf, pregs (x));
00963       OUTS (outf, "==");
00964       OUTS (outf, imm3 (y));
00965     }
00966   else if (opc == 1 && I == 1 && G == 1)
00967     {
00968       OUTS (outf, "CC=");
00969       OUTS (outf, pregs (x));
00970       OUTS (outf, "<");
00971       OUTS (outf, imm3 (y));
00972     }
00973   else if (opc == 2 && I == 1 && G == 1)
00974     {
00975       OUTS (outf, "CC=");
00976       OUTS (outf, pregs (x));
00977       OUTS (outf, "<=");
00978       OUTS (outf, imm3 (y));
00979     }
00980   else if (opc == 3 && I == 1 && G == 1)
00981     {
00982       OUTS (outf, "CC=");
00983       OUTS (outf, pregs (x));
00984       OUTS (outf, "<");
00985       OUTS (outf, uimm3 (y));
00986       OUTS (outf, "(IU)");
00987     }
00988   else if (opc == 4 && I == 1 && G == 1)
00989     {
00990       OUTS (outf, "CC=");
00991       OUTS (outf, pregs (x));
00992       OUTS (outf, "<=");
00993       OUTS (outf, uimm3 (y));
00994       OUTS (outf, "(IU)");
00995     }
00996   else if (opc == 5 && I == 0 && G == 0)
00997     OUTS (outf, "CC=A0==A1");
00998 
00999   else if (opc == 6 && I == 0 && G == 0)
01000     OUTS (outf, "CC=A0<A1");
01001 
01002   else if (opc == 7 && I == 0 && G == 0)
01003     OUTS (outf, "CC=A0<=A1");
01004 
01005   else
01006     return 0;
01007   return 2;
01008 }
01009 
01010 static int
01011 decode_CC2dreg_0 (TIword iw0, disassemble_info *outf)
01012 {
01013   /* CC2dreg
01014      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01015      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 |.op....|.reg.......|
01016      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01017   int op  = ((iw0 >> CC2dreg_op_bits) & CC2dreg_op_mask);
01018   int reg = ((iw0 >> CC2dreg_reg_bits) & CC2dreg_reg_mask);
01019 
01020   if (op == 0)
01021     {
01022       OUTS (outf, dregs (reg));
01023       OUTS (outf, "=CC");
01024     }
01025   else if (op == 1)
01026     {
01027       OUTS (outf, "CC=");
01028       OUTS (outf, dregs (reg));
01029     }
01030   else if (op == 3)
01031     OUTS (outf, "CC=!CC");
01032   else
01033     return 0;
01034 
01035   return 2;
01036 }
01037 
01038 static int
01039 decode_CC2stat_0 (TIword iw0, disassemble_info *outf)
01040 {
01041   /* CC2stat
01042      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01043      | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |.D.|.op....|.cbit..............|
01044      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01045   int D    = ((iw0 >> CC2stat_D_bits) & CC2stat_D_mask);
01046   int op   = ((iw0 >> CC2stat_op_bits) & CC2stat_op_mask);
01047   int cbit = ((iw0 >> CC2stat_cbit_bits) & CC2stat_cbit_mask);
01048 
01049   if (op == 0 && D == 0)
01050     {
01051       OUTS (outf, "CC = ");
01052       OUTS (outf, statbits (cbit));
01053     }
01054   else if (op == 1 && D == 0)
01055     {
01056       OUTS (outf, "CC|=");
01057       OUTS (outf, statbits (cbit));
01058     }
01059   else if (op == 2 && D == 0)
01060     {
01061       OUTS (outf, "CC&=");
01062       OUTS (outf, statbits (cbit));
01063     }
01064   else if (op == 3 && D == 0)
01065     {
01066       OUTS (outf, "CC^=");
01067       OUTS (outf, statbits (cbit));
01068     }
01069   else if (op == 0 && D == 1)
01070     {
01071       OUTS (outf, statbits (cbit));
01072       OUTS (outf, "=CC");
01073     }
01074   else if (op == 1 && D == 1)
01075     {
01076       OUTS (outf, statbits (cbit));
01077       OUTS (outf, "|=CC");
01078     }
01079   else if (op == 2 && D == 1)
01080     {
01081       OUTS (outf, statbits (cbit));
01082       OUTS (outf, "&=CC");
01083     }
01084   else if (op == 3 && D == 1)
01085     {
01086       OUTS (outf, statbits (cbit));
01087       OUTS (outf, "^=CC");
01088     }
01089   else
01090     return 0;
01091 
01092   return 2;
01093 }
01094 
01095 static int
01096 decode_BRCC_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
01097 {
01098   /* BRCC
01099      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01100      | 0 | 0 | 0 | 1 |.T.|.B.|.offset................................|
01101      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01102   int B = ((iw0 >> BRCC_B_bits) & BRCC_B_mask);
01103   int T = ((iw0 >> BRCC_T_bits) & BRCC_T_mask);
01104   int offset = ((iw0 >> BRCC_offset_bits) & BRCC_offset_mask);
01105 
01106   if (T == 1 && B == 1)
01107     {
01108       OUTS (outf, "IF CC JUMP ");
01109       OUTS (outf, pcrel10 (offset));
01110       OUTS (outf, "(BP)");
01111     }
01112   else if (T == 0 && B == 1)
01113     {
01114       OUTS (outf, "IF ! CC JUMP ");
01115       OUTS (outf, pcrel10 (offset));
01116       OUTS (outf, "(BP)");
01117     }
01118   else if (T == 1)
01119     {
01120       OUTS (outf, "IF CC JUMP ");
01121       OUTS (outf, pcrel10 (offset));
01122     }
01123   else if (T == 0)
01124     {
01125       OUTS (outf, "IF ! CC JUMP ");
01126       OUTS (outf, pcrel10 (offset));
01127     }
01128   else
01129     return 0;
01130 
01131   return 2;
01132 }
01133 
01134 static int
01135 decode_UJUMP_0 (TIword iw0, bfd_vma pc, disassemble_info *outf)
01136 {
01137   /* UJUMP
01138      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01139      | 0 | 0 | 1 | 0 |.offset........................................|
01140      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01141   int offset = ((iw0 >> UJump_offset_bits) & UJump_offset_mask);
01142 
01143   OUTS (outf, "JUMP.S  ");
01144   OUTS (outf, pcrel12 (offset));
01145   return 2;
01146 }
01147 
01148 static int
01149 decode_REGMV_0 (TIword iw0, disassemble_info *outf)
01150 {
01151   /* REGMV
01152      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01153      | 0 | 0 | 1 | 1 |.gd........|.gs........|.dst.......|.src.......|
01154      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01155   int gs  = ((iw0 >> RegMv_gs_bits) & RegMv_gs_mask);
01156   int gd  = ((iw0 >> RegMv_gd_bits) & RegMv_gd_mask);
01157   int src = ((iw0 >> RegMv_src_bits) & RegMv_src_mask);
01158   int dst = ((iw0 >> RegMv_dst_bits) & RegMv_dst_mask);
01159 
01160   OUTS (outf, allregs (dst, gd));
01161   OUTS (outf, "=");
01162   OUTS (outf, allregs (src, gs));
01163   return 2;
01164 }
01165 
01166 static int
01167 decode_ALU2op_0 (TIword iw0, disassemble_info *outf)
01168 {
01169   /* ALU2op
01170      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01171      | 0 | 1 | 0 | 0 | 0 | 0 |.opc...........|.src.......|.dst.......|
01172      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01173   int src = ((iw0 >> ALU2op_src_bits) & ALU2op_src_mask);
01174   int opc = ((iw0 >> ALU2op_opc_bits) & ALU2op_opc_mask);
01175   int dst = ((iw0 >> ALU2op_dst_bits) & ALU2op_dst_mask);
01176 
01177   if (opc == 0)
01178     {
01179       OUTS (outf, dregs (dst));
01180       OUTS (outf, ">>>=");
01181       OUTS (outf, dregs (src));
01182     }
01183   else if (opc == 1)
01184     {
01185       OUTS (outf, dregs (dst));
01186       OUTS (outf, ">>=");
01187       OUTS (outf, dregs (src));
01188     }
01189   else if (opc == 2)
01190     {
01191       OUTS (outf, dregs (dst));
01192       OUTS (outf, "<<=");
01193       OUTS (outf, dregs (src));
01194     }
01195   else if (opc == 3)
01196     {
01197       OUTS (outf, dregs (dst));
01198       OUTS (outf, "*=");
01199       OUTS (outf, dregs (src));
01200     }
01201   else if (opc == 4)
01202     {
01203       OUTS (outf, dregs (dst));
01204       OUTS (outf, "=(");
01205       OUTS (outf, dregs (dst));
01206       OUTS (outf, "+");
01207       OUTS (outf, dregs (src));
01208       OUTS (outf, ")<<1");
01209     }
01210   else if (opc == 5)
01211     {
01212       OUTS (outf, dregs (dst));
01213       OUTS (outf, "=(");
01214       OUTS (outf, dregs (dst));
01215       OUTS (outf, "+");
01216       OUTS (outf, dregs (src));
01217       OUTS (outf, ")<<2");
01218     }
01219   else if (opc == 8)
01220     {
01221       OUTS (outf, "DIVQ(");
01222       OUTS (outf, dregs (dst));
01223       OUTS (outf, ",");
01224       OUTS (outf, dregs (src));
01225       OUTS (outf, ")");
01226     }
01227   else if (opc == 9)
01228     {
01229       OUTS (outf, "DIVS(");
01230       OUTS (outf, dregs (dst));
01231       OUTS (outf, ",");
01232       OUTS (outf, dregs (src));
01233       OUTS (outf, ")");
01234     }
01235   else if (opc == 10)
01236     {
01237       OUTS (outf, dregs (dst));
01238       OUTS (outf, "=");
01239       OUTS (outf, dregs_lo (src));
01240       OUTS (outf, "(X)");
01241     }
01242   else if (opc == 11)
01243     {
01244       OUTS (outf, dregs (dst));
01245       OUTS (outf, "=");
01246       OUTS (outf, dregs_lo (src));
01247       OUTS (outf, "(Z)");
01248     }
01249   else if (opc == 12)
01250     {
01251       OUTS (outf, dregs (dst));
01252       OUTS (outf, "=");
01253       OUTS (outf, dregs_byte (src));
01254       OUTS (outf, "(X)");
01255     }
01256   else if (opc == 13)
01257     {
01258       OUTS (outf, dregs (dst));
01259       OUTS (outf, "=");
01260       OUTS (outf, dregs_byte (src));
01261       OUTS (outf, "(Z)");
01262     }
01263   else if (opc == 14)
01264     {
01265       OUTS (outf, dregs (dst));
01266       OUTS (outf, "=-");
01267       OUTS (outf, dregs (src));
01268     }
01269   else if (opc == 15)
01270     {
01271       OUTS (outf, dregs (dst));
01272       OUTS (outf, "=~");
01273       OUTS (outf, dregs (src));
01274     }
01275   else
01276     return 0;
01277 
01278   return 2;
01279 }
01280 
01281 static int
01282 decode_PTR2op_0 (TIword iw0, disassemble_info *outf)
01283 {
01284   /* PTR2op
01285      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01286      | 0 | 1 | 0 | 0 | 0 | 1 | 0 |.opc.......|.src.......|.dst.......|
01287      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01288   int src = ((iw0 >> PTR2op_src_bits) & PTR2op_dst_mask);
01289   int opc = ((iw0 >> PTR2op_opc_bits) & PTR2op_opc_mask);
01290   int dst = ((iw0 >> PTR2op_dst_bits) & PTR2op_dst_mask);
01291 
01292   if (opc == 0)
01293     {
01294       OUTS (outf, pregs (dst));
01295       OUTS (outf, "-=");
01296       OUTS (outf, pregs (src));
01297     }
01298   else if (opc == 1)
01299     {
01300       OUTS (outf, pregs (dst));
01301       OUTS (outf, "=");
01302       OUTS (outf, pregs (src));
01303       OUTS (outf, "<<2");
01304     }
01305   else if (opc == 3)
01306     {
01307       OUTS (outf, pregs (dst));
01308       OUTS (outf, "=");
01309       OUTS (outf, pregs (src));
01310       OUTS (outf, ">>2");
01311     }
01312   else if (opc == 4)
01313     {
01314       OUTS (outf, pregs (dst));
01315       OUTS (outf, "=");
01316       OUTS (outf, pregs (src));
01317       OUTS (outf, ">>1");
01318     }
01319   else if (opc == 5)
01320     {
01321       OUTS (outf, pregs (dst));
01322       OUTS (outf, "+=");
01323       OUTS (outf, pregs (src));
01324       OUTS (outf, "(BREV)");
01325     }
01326   else if (opc == 6)
01327     {
01328       OUTS (outf, pregs (dst));
01329       OUTS (outf, "=(");
01330       OUTS (outf, pregs (dst));
01331       OUTS (outf, "+");
01332       OUTS (outf, pregs (src));
01333       OUTS (outf, ")<<1");
01334     }
01335   else if (opc == 7)
01336     {
01337       OUTS (outf, pregs (dst));
01338       OUTS (outf, "=(");
01339       OUTS (outf, pregs (dst));
01340       OUTS (outf, "+");
01341       OUTS (outf, pregs (src));
01342       OUTS (outf, ")<<2");
01343     }
01344   else
01345     return 0;
01346 
01347   return 2;
01348 }
01349 
01350 static int
01351 decode_LOGI2op_0 (TIword iw0, disassemble_info *outf)
01352 {
01353   /* LOGI2op
01354      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01355      | 0 | 1 | 0 | 0 | 1 |.opc.......|.src...............|.dst.......|
01356      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01357   int src = ((iw0 >> LOGI2op_src_bits) & LOGI2op_src_mask);
01358   int opc = ((iw0 >> LOGI2op_opc_bits) & LOGI2op_opc_mask);
01359   int dst = ((iw0 >> LOGI2op_dst_bits) & LOGI2op_dst_mask);
01360 
01361   if (opc == 0)
01362     {
01363       OUTS (outf, "CC = ! BITTST (");
01364       OUTS (outf, dregs (dst));
01365       OUTS (outf, ",");
01366       OUTS (outf, uimm5 (src));
01367       OUTS (outf, ")");
01368     }
01369   else if (opc == 1)
01370     {
01371       OUTS (outf, "CC = BITTST (");
01372       OUTS (outf, dregs (dst));
01373       OUTS (outf, ",");
01374       OUTS (outf, uimm5 (src));
01375       OUTS (outf, ")");
01376     }
01377   else if (opc == 2)
01378     {
01379       OUTS (outf, "BITSET (");
01380       OUTS (outf, dregs (dst));
01381       OUTS (outf, ",");
01382       OUTS (outf, uimm5 (src));
01383       OUTS (outf, ")");
01384     }
01385   else if (opc == 3)
01386     {
01387       OUTS (outf, "BITTGL (");
01388       OUTS (outf, dregs (dst));
01389       OUTS (outf, ",");
01390       OUTS (outf, uimm5 (src));
01391       OUTS (outf, ")");
01392     }
01393   else if (opc == 4)
01394     {
01395       OUTS (outf, "BITCLR (");
01396       OUTS (outf, dregs (dst));
01397       OUTS (outf, ",");
01398       OUTS (outf, uimm5 (src));
01399       OUTS (outf, ")");
01400     }
01401   else if (opc == 5)
01402     {
01403       OUTS (outf, dregs (dst));
01404       OUTS (outf, ">>>=");
01405       OUTS (outf, uimm5 (src));
01406     }
01407   else if (opc == 6)
01408     {
01409       OUTS (outf, dregs (dst));
01410       OUTS (outf, ">>=");
01411       OUTS (outf, uimm5 (src));
01412     }
01413   else if (opc == 7)
01414     {
01415       OUTS (outf, dregs (dst));
01416       OUTS (outf, "<<=");
01417       OUTS (outf, uimm5 (src));
01418     }
01419   else
01420     return 0;
01421 
01422   return 2;
01423 }
01424 
01425 static int
01426 decode_COMP3op_0 (TIword iw0, disassemble_info *outf)
01427 {
01428   /* COMP3op
01429      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01430      | 0 | 1 | 0 | 1 |.opc.......|.dst.......|.src1......|.src0......|
01431      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01432   int opc  = ((iw0 >> COMP3op_opc_bits) & COMP3op_opc_mask);
01433   int dst  = ((iw0 >> COMP3op_dst_bits) & COMP3op_dst_mask);
01434   int src0 = ((iw0 >> COMP3op_src0_bits) & COMP3op_src0_mask);
01435   int src1 = ((iw0 >> COMP3op_src1_bits) & COMP3op_src1_mask);
01436 
01437   if (opc == 5 && src1 == src0)
01438     {
01439       OUTS (outf, pregs (dst));
01440       OUTS (outf, "=");
01441       OUTS (outf, pregs (src0));
01442       OUTS (outf, "<<1");
01443     }
01444   else if (opc == 1)
01445     {
01446       OUTS (outf, dregs (dst));
01447       OUTS (outf, "=");
01448       OUTS (outf, dregs (src0));
01449       OUTS (outf, "-");
01450       OUTS (outf, dregs (src1));
01451     }
01452   else if (opc == 2)
01453     {
01454       OUTS (outf, dregs (dst));
01455       OUTS (outf, "=");
01456       OUTS (outf, dregs (src0));
01457       OUTS (outf, "&");
01458       OUTS (outf, dregs (src1));
01459     }
01460   else if (opc == 3)
01461     {
01462       OUTS (outf, dregs (dst));
01463       OUTS (outf, "=");
01464       OUTS (outf, dregs (src0));
01465       OUTS (outf, "|");
01466       OUTS (outf, dregs (src1));
01467     }
01468   else if (opc == 4)
01469     {
01470       OUTS (outf, dregs (dst));
01471       OUTS (outf, "=");
01472       OUTS (outf, dregs (src0));
01473       OUTS (outf, "^");
01474       OUTS (outf, dregs (src1));
01475     }
01476   else if (opc == 5)
01477     {
01478       OUTS (outf, pregs (dst));
01479       OUTS (outf, "=");
01480       OUTS (outf, pregs (src0));
01481       OUTS (outf, "+");
01482       OUTS (outf, pregs (src1));
01483     }
01484   else if (opc == 6)
01485     {
01486       OUTS (outf, pregs (dst));
01487       OUTS (outf, "=");
01488       OUTS (outf, pregs (src0));
01489       OUTS (outf, "+(");
01490       OUTS (outf, pregs (src1));
01491       OUTS (outf, "<<1)");
01492     }
01493   else if (opc == 7)
01494     {
01495       OUTS (outf, pregs (dst));
01496       OUTS (outf, "=");
01497       OUTS (outf, pregs (src0));
01498       OUTS (outf, "+(");
01499       OUTS (outf, pregs (src1));
01500       OUTS (outf, "<<2)");
01501     }
01502   else if (opc == 0)
01503     {
01504       OUTS (outf, dregs (dst));
01505       OUTS (outf, "=");
01506       OUTS (outf, dregs (src0));
01507       OUTS (outf, "+");
01508       OUTS (outf, dregs (src1));
01509     }
01510   else
01511     return 0;
01512 
01513   return 2;
01514 }
01515 
01516 static int
01517 decode_COMPI2opD_0 (TIword iw0, disassemble_info *outf)
01518 {
01519   /* COMPI2opD
01520      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01521      | 0 | 1 | 1 | 0 | 0 |.op|..src......................|.dst.......|
01522      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01523   int op  = ((iw0 >> COMPI2opD_op_bits) & COMPI2opD_op_mask);
01524   int dst = ((iw0 >> COMPI2opD_dst_bits) & COMPI2opD_dst_mask);
01525   int src = ((iw0 >> COMPI2opD_src_bits) & COMPI2opD_src_mask);
01526 
01527   if (op == 0)
01528     {
01529       OUTS (outf, dregs (dst));
01530       OUTS (outf, "=");
01531       OUTS (outf, imm7 (src));
01532       OUTS (outf, "(x)");
01533     }
01534   else if (op == 1)
01535     {
01536       OUTS (outf, dregs (dst));
01537       OUTS (outf, "+=");
01538       OUTS (outf, imm7 (src));
01539     }
01540   else
01541     return 0;
01542 
01543   return 2;
01544 }
01545 
01546 static int
01547 decode_COMPI2opP_0 (TIword iw0, disassemble_info *outf)
01548 {
01549   /* COMPI2opP
01550      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01551      | 0 | 1 | 1 | 0 | 1 |.op|.src.......................|.dst.......|
01552      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01553   int op  = ((iw0 >> COMPI2opP_op_bits) & COMPI2opP_op_mask);
01554   int src = ((iw0 >> COMPI2opP_src_bits) & COMPI2opP_src_mask);
01555   int dst = ((iw0 >> COMPI2opP_dst_bits) & COMPI2opP_dst_mask);
01556 
01557   if (op == 0)
01558     {
01559       OUTS (outf, pregs (dst));
01560       OUTS (outf, "=");
01561       OUTS (outf, imm7 (src));
01562     }
01563   else if (op == 1)
01564     {
01565       OUTS (outf, pregs (dst));
01566       OUTS (outf, "+=");
01567       OUTS (outf, imm7 (src));
01568     }
01569   else
01570     return 0;
01571 
01572   return 2;
01573 }
01574 
01575 static int
01576 decode_LDSTpmod_0 (TIword iw0, disassemble_info *outf)
01577 {
01578   /* LDSTpmod
01579      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01580      | 1 | 0 | 0 | 0 |.W.|.aop...|.reg.......|.idx.......|.ptr.......|
01581      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01582   int W   = ((iw0 >> LDSTpmod_W_bits) & LDSTpmod_W_mask);
01583   int aop = ((iw0 >> LDSTpmod_aop_bits) & LDSTpmod_aop_mask);
01584   int idx = ((iw0 >> LDSTpmod_idx_bits) & LDSTpmod_idx_mask);
01585   int ptr = ((iw0 >> LDSTpmod_ptr_bits) & LDSTpmod_ptr_mask);
01586   int reg = ((iw0 >> LDSTpmod_reg_bits) & LDSTpmod_reg_mask);
01587 
01588   if (aop == 1 && W == 0 && idx == ptr)
01589     {
01590       OUTS (outf, dregs_lo (reg));
01591       OUTS (outf, "=W[");
01592       OUTS (outf, pregs (ptr));
01593       OUTS (outf, "]");
01594     }
01595   else if (aop == 2 && W == 0 && idx == ptr)
01596     {
01597       OUTS (outf, dregs_hi (reg));
01598       OUTS (outf, "=W[");
01599       OUTS (outf, pregs (ptr));
01600       OUTS (outf, "]");
01601     }
01602   else if (aop == 1 && W == 1 && idx == ptr)
01603     {
01604       OUTS (outf, "W[");
01605       OUTS (outf, pregs (ptr));
01606       OUTS (outf, "]=");
01607       OUTS (outf, dregs_lo (reg));
01608     }
01609   else if (aop == 2 && W == 1 && idx == ptr)
01610     {
01611       OUTS (outf, "W[");
01612       OUTS (outf, pregs (ptr));
01613       OUTS (outf, "]=");
01614       OUTS (outf, dregs_hi (reg));
01615     }
01616   else if (aop == 0 && W == 0)
01617     {
01618       OUTS (outf, dregs (reg));
01619       OUTS (outf, "=[");
01620       OUTS (outf, pregs (ptr));
01621       OUTS (outf, "++");
01622       OUTS (outf, pregs (idx));
01623       OUTS (outf, "]");
01624     }
01625   else if (aop == 1 && W == 0)
01626     {
01627       OUTS (outf, dregs_lo (reg));
01628       OUTS (outf, "=W[");
01629       OUTS (outf, pregs (ptr));
01630       OUTS (outf, "++");
01631       OUTS (outf, pregs (idx));
01632       OUTS (outf, "]");
01633     }
01634   else if (aop == 2 && W == 0)
01635     {
01636       OUTS (outf, dregs_hi (reg));
01637       OUTS (outf, "=W[");
01638       OUTS (outf, pregs (ptr));
01639       OUTS (outf, "++");
01640       OUTS (outf, pregs (idx));
01641       OUTS (outf, "]");
01642     }
01643   else if (aop == 3 && W == 0)
01644     {
01645       OUTS (outf, dregs (reg));
01646       OUTS (outf, "=W[");
01647       OUTS (outf, pregs (ptr));
01648       OUTS (outf, "++");
01649       OUTS (outf, pregs (idx));
01650       OUTS (outf, "] (Z)");
01651     }
01652   else if (aop == 3 && W == 1)
01653     {
01654       OUTS (outf, dregs (reg));
01655       OUTS (outf, "=W[");
01656       OUTS (outf, pregs (ptr));
01657       OUTS (outf, "++");
01658       OUTS (outf, pregs (idx));
01659       OUTS (outf, "](X)");
01660     }
01661   else if (aop == 0 && W == 1)
01662     {
01663       OUTS (outf, "[");
01664       OUTS (outf, pregs (ptr));
01665       OUTS (outf, "++");
01666       OUTS (outf, pregs (idx));
01667       OUTS (outf, "]=");
01668       OUTS (outf, dregs (reg));
01669     }
01670   else if (aop == 1 && W == 1)
01671     {
01672       OUTS (outf, "W[");
01673       OUTS (outf, pregs (ptr));
01674       OUTS (outf, "++");
01675       OUTS (outf, pregs (idx));
01676       OUTS (outf, "]=");
01677       OUTS (outf, dregs_lo (reg));
01678     }
01679   else if (aop == 2 && W == 1)
01680     {
01681       OUTS (outf, "W[");
01682       OUTS (outf, pregs (ptr));
01683       OUTS (outf, "++");
01684       OUTS (outf, pregs (idx));
01685       OUTS (outf, "]=");
01686       OUTS (outf, dregs_hi (reg));
01687     }
01688   else
01689     return 0;
01690 
01691   return 2;
01692 }
01693 
01694 static int
01695 decode_dagMODim_0 (TIword iw0, disassemble_info *outf)
01696 {
01697   /* dagMODim
01698      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01699      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 |.br| 1 | 1 |.op|.m.....|.i.....|
01700      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01701   int i  = ((iw0 >> DagMODim_i_bits) & DagMODim_i_mask);
01702   int m  = ((iw0 >> DagMODim_m_bits) & DagMODim_m_mask);
01703   int br = ((iw0 >> DagMODim_br_bits) & DagMODim_br_mask);
01704   int op = ((iw0 >> DagMODim_op_bits) & DagMODim_op_mask);
01705 
01706   if (op == 0 && br == 1)
01707     {
01708       OUTS (outf, iregs (i));
01709       OUTS (outf, "+=");
01710       OUTS (outf, mregs (m));
01711       OUTS (outf, "(BREV)");
01712     }
01713   else if (op == 0)
01714     {
01715       OUTS (outf, iregs (i));
01716       OUTS (outf, "+=");
01717       OUTS (outf, mregs (m));
01718     }
01719   else if (op == 1)
01720     {
01721       OUTS (outf, iregs (i));
01722       OUTS (outf, "-=");
01723       OUTS (outf, mregs (m));
01724     }
01725   else
01726     return 0;
01727 
01728   return 2;
01729 }
01730 
01731 static int
01732 decode_dagMODik_0 (TIword iw0, disassemble_info *outf)
01733 {
01734   /* dagMODik
01735      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01736      | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 |.op....|.i.....|
01737      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01738   int i  = ((iw0 >> DagMODik_i_bits) & DagMODik_i_mask);
01739   int op = ((iw0 >> DagMODik_op_bits) & DagMODik_op_mask);
01740 
01741   if (op == 0)
01742     {
01743       OUTS (outf, iregs (i));
01744       OUTS (outf, "+=2");
01745     }
01746   else if (op == 1)
01747     {
01748       OUTS (outf, iregs (i));
01749       OUTS (outf, "-=2");
01750     }
01751   else if (op == 2)
01752     {
01753       OUTS (outf, iregs (i));
01754       OUTS (outf, "+=4");
01755     }
01756   else if (op == 3)
01757     {
01758       OUTS (outf, iregs (i));
01759       OUTS (outf, "-=4");
01760     }
01761   else
01762     return 0;
01763 
01764   return 2;
01765 }
01766 
01767 static int
01768 decode_dspLDST_0 (TIword iw0, disassemble_info *outf)
01769 {
01770   /* dspLDST
01771      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01772      | 1 | 0 | 0 | 1 | 1 | 1 |.W.|.aop...|.m.....|.i.....|.reg.......|
01773      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01774   int i   = ((iw0 >> DspLDST_i_bits) & DspLDST_i_mask);
01775   int m   = ((iw0 >> DspLDST_m_bits) & DspLDST_m_mask);
01776   int W   = ((iw0 >> DspLDST_W_bits) & DspLDST_W_mask);
01777   int aop = ((iw0 >> DspLDST_aop_bits) & DspLDST_aop_mask);
01778   int reg = ((iw0 >> DspLDST_reg_bits) & DspLDST_reg_mask);
01779 
01780   if (aop == 0 && W == 0 && m == 0)
01781     {
01782       OUTS (outf, dregs (reg));
01783       OUTS (outf, "=[");
01784       OUTS (outf, iregs (i));
01785       OUTS (outf, "++]");
01786     }
01787   else if (aop == 0 && W == 0 && m == 1)
01788     {
01789       OUTS (outf, dregs_lo (reg));
01790       OUTS (outf, "=W[");
01791       OUTS (outf, iregs (i));
01792       OUTS (outf, "++]");
01793     }
01794   else if (aop == 0 && W == 0 && m == 2)
01795     {
01796       OUTS (outf, dregs_hi (reg));
01797       OUTS (outf, "=W[");
01798       OUTS (outf, iregs (i));
01799       OUTS (outf, "++]");
01800     }
01801   else if (aop == 1 && W == 0 && m == 0)
01802     {
01803       OUTS (outf, dregs (reg));
01804       OUTS (outf, "=[");
01805       OUTS (outf, iregs (i));
01806       OUTS (outf, "--]");
01807     }
01808   else if (aop == 1 && W == 0 && m == 1)
01809     {
01810       OUTS (outf, dregs_lo (reg));
01811       OUTS (outf, "=W[");
01812       OUTS (outf, iregs (i));
01813       OUTS (outf, "--]");
01814     }
01815   else if (aop == 1 && W == 0 && m == 2)
01816     {
01817       OUTS (outf, dregs_hi (reg));
01818       OUTS (outf, "=W[");
01819       OUTS (outf, iregs (i));
01820       OUTS (outf, "--]");
01821     }
01822   else if (aop == 2 && W == 0 && m == 0)
01823     {
01824       OUTS (outf, dregs (reg));
01825       OUTS (outf, "=[");
01826       OUTS (outf, iregs (i));
01827       OUTS (outf, "]");
01828     }
01829   else if (aop == 2 && W == 0 && m == 1)
01830     {
01831       OUTS (outf, dregs_lo (reg));
01832       OUTS (outf, "=W[");
01833       OUTS (outf, iregs (i));
01834       OUTS (outf, "]");
01835     }
01836   else if (aop == 2 && W == 0 && m == 2)
01837     {
01838       OUTS (outf, dregs_hi (reg));
01839       OUTS (outf, "=W[");
01840       OUTS (outf, iregs (i));
01841       OUTS (outf, "]");
01842     }
01843   else if (aop == 0 && W == 1 && m == 0)
01844     {
01845       OUTS (outf, "[");
01846       OUTS (outf, iregs (i));
01847       OUTS (outf, "++]=");
01848       OUTS (outf, dregs (reg));
01849     }
01850   else if (aop == 0 && W == 1 && m == 1)
01851     {
01852       OUTS (outf, "W[");
01853       OUTS (outf, iregs (i));
01854       OUTS (outf, "++]=");
01855       OUTS (outf, dregs_lo (reg));
01856     }
01857   else if (aop == 0 && W == 1 && m == 2)
01858     {
01859       OUTS (outf, "W[");
01860       OUTS (outf, iregs (i));
01861       OUTS (outf, "++]=");
01862       OUTS (outf, dregs_hi (reg));
01863     }
01864   else if (aop == 1 && W == 1 && m == 0)
01865     {
01866       OUTS (outf, "[");
01867       OUTS (outf, iregs (i));
01868       OUTS (outf, "--]=");
01869       OUTS (outf, dregs (reg));
01870     }
01871   else if (aop == 1 && W == 1 && m == 1)
01872     {
01873       OUTS (outf, "W[");
01874       OUTS (outf, iregs (i));
01875       OUTS (outf, "--]=");
01876       OUTS (outf, dregs_lo (reg));
01877     }
01878   else if (aop == 1 && W == 1 && m == 2)
01879     {
01880       OUTS (outf, "W[");
01881       OUTS (outf, iregs (i));
01882       OUTS (outf, "--]=");
01883       OUTS (outf, dregs_hi (reg));
01884     }
01885   else if (aop == 2 && W == 1 && m == 0)
01886     {
01887       OUTS (outf, "[");
01888       OUTS (outf, iregs (i));
01889       OUTS (outf, "]=");
01890       OUTS (outf, dregs (reg));
01891     }
01892   else if (aop == 2 && W == 1 && m == 1)
01893     {
01894       OUTS (outf, "W[");
01895       OUTS (outf, iregs (i));
01896       OUTS (outf, "]=");
01897       OUTS (outf, dregs_lo (reg));
01898     }
01899   else if (aop == 2 && W == 1 && m == 2)
01900     {
01901       OUTS (outf, "W[");
01902       OUTS (outf, iregs (i));
01903       OUTS (outf, "]=");
01904       OUTS (outf, dregs_hi (reg));
01905     }
01906   else if (aop == 3 && W == 0)
01907     {
01908       OUTS (outf, dregs (reg));
01909       OUTS (outf, "=[");
01910       OUTS (outf, iregs (i));
01911       OUTS (outf, "++");
01912       OUTS (outf, mregs (m));
01913       OUTS (outf, "]");
01914     }
01915   else if (aop == 3 && W == 1)
01916     {
01917       OUTS (outf, "[");
01918       OUTS (outf, iregs (i));
01919       OUTS (outf, "++");
01920       OUTS (outf, mregs (m));
01921       OUTS (outf, "]=");
01922       OUTS (outf, dregs (reg));
01923     }
01924   else
01925     return 0;
01926 
01927   return 2;
01928 }
01929 
01930 static int
01931 decode_LDST_0 (TIword iw0, disassemble_info *outf)
01932 {
01933   /* LDST
01934      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
01935      | 1 | 0 | 0 | 1 |.sz....|.W.|.aop...|.Z.|.ptr.......|.reg.......|
01936      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
01937   int Z   = ((iw0 >> LDST_Z_bits) & LDST_Z_mask);
01938   int W   = ((iw0 >> LDST_W_bits) & LDST_W_mask);
01939   int sz  = ((iw0 >> LDST_sz_bits) & LDST_sz_mask);
01940   int aop = ((iw0 >> LDST_aop_bits) & LDST_aop_mask);
01941   int reg = ((iw0 >> LDST_reg_bits) & LDST_reg_mask);
01942   int ptr = ((iw0 >> LDST_ptr_bits) & LDST_ptr_mask);
01943 
01944   if (aop == 0 && sz == 0 && Z == 0 && W == 0)
01945     {
01946       OUTS (outf, dregs (reg));
01947       OUTS (outf, "=[");
01948       OUTS (outf, pregs (ptr));
01949       OUTS (outf, "++]");
01950     }
01951   else if (aop == 0 && sz == 0 && Z == 1 && W == 0)
01952     {
01953       OUTS (outf, pregs (reg));
01954       OUTS (outf, "=[");
01955       OUTS (outf, pregs (ptr));
01956       OUTS (outf, "++]");
01957     }
01958   else if (aop == 0 && sz == 1 && Z == 0 && W == 0)
01959     {
01960       OUTS (outf, dregs (reg));
01961       OUTS (outf, "=W[");
01962       OUTS (outf, pregs (ptr));
01963       OUTS (outf, "++] (Z)");
01964     }
01965   else if (aop == 0 && sz == 1 && Z == 1 && W == 0)
01966     {
01967       OUTS (outf, dregs (reg));
01968       OUTS (outf, "=W[");
01969       OUTS (outf, pregs (ptr));
01970       OUTS (outf, "++](X)");
01971     }
01972   else if (aop == 0 && sz == 2 && Z == 0 && W == 0)
01973     {
01974       OUTS (outf, dregs (reg));
01975       OUTS (outf, "=B[");
01976       OUTS (outf, pregs (ptr));
01977       OUTS (outf, "++] (Z)");
01978     }
01979   else if (aop == 0 && sz == 2 && Z == 1 && W == 0)
01980     {
01981       OUTS (outf, dregs (reg));
01982       OUTS (outf, "=B[");
01983       OUTS (outf, pregs (ptr));
01984       OUTS (outf, "++](X)");
01985     }
01986   else if (aop == 1 && sz == 0 && Z == 0 && W == 0)
01987     {
01988       OUTS (outf, dregs (reg));
01989       OUTS (outf, "=[");
01990       OUTS (outf, pregs (ptr));
01991       OUTS (outf, "--]");
01992     }
01993   else if (aop == 1 && sz == 0 && Z == 1 && W == 0)
01994     {
01995       OUTS (outf, pregs (reg));
01996       OUTS (outf, "=[");
01997       OUTS (outf, pregs (ptr));
01998       OUTS (outf, "--]");
01999     }
02000   else if (aop == 1 && sz == 1 && Z == 0 && W == 0)
02001     {
02002       OUTS (outf, dregs (reg));
02003       OUTS (outf, "=W[");
02004       OUTS (outf, pregs (ptr));
02005       OUTS (outf, "--] (Z)");
02006     }
02007   else if (aop == 1 && sz == 1 && Z == 1 && W == 0)
02008     {
02009       OUTS (outf, dregs (reg));
02010       OUTS (outf, "=W[");
02011       OUTS (outf, pregs (ptr));
02012       OUTS (outf, "--](X)");
02013     }
02014   else if (aop == 1 && sz == 2 && Z == 0 && W == 0)
02015     {
02016       OUTS (outf, dregs (reg));
02017       OUTS (outf, "=B[");
02018       OUTS (outf, pregs (ptr));
02019       OUTS (outf, "--] (Z)");
02020     }
02021   else if (aop == 1 && sz == 2 && Z == 1 && W == 0)
02022     {
02023       OUTS (outf, dregs (reg));
02024       OUTS (outf, "=B[");
02025       OUTS (outf, pregs (ptr));
02026       OUTS (outf, "--](X)");
02027     }
02028   else if (aop == 2 && sz == 0 && Z == 0 && W == 0)
02029     {
02030       OUTS (outf, dregs (reg));
02031       OUTS (outf, "=[");
02032       OUTS (outf, pregs (ptr));
02033       OUTS (outf, "]");
02034     }
02035   else if (aop == 2 && sz == 0 && Z == 1 && W == 0)
02036     {
02037       OUTS (outf, pregs (reg));
02038       OUTS (outf, "=[");
02039       OUTS (outf, pregs (ptr));
02040       OUTS (outf, "]");
02041     }
02042   else if (aop == 2 && sz == 1 && Z == 0 && W == 0)
02043     {
02044       OUTS (outf, dregs (reg));
02045       OUTS (outf, "=W[");
02046       OUTS (outf, pregs (ptr));
02047       OUTS (outf, "] (Z)");
02048     }
02049   else if (aop == 2 && sz == 1 && Z == 1 && W == 0)
02050     {
02051       OUTS (outf, dregs (reg));
02052       OUTS (outf, "=W[");
02053       OUTS (outf, pregs (ptr));
02054       OUTS (outf, "](X)");
02055     }
02056   else if (aop == 2 && sz == 2 && Z == 0 && W == 0)
02057     {
02058       OUTS (outf, dregs (reg));
02059       OUTS (outf, "=B[");
02060       OUTS (outf, pregs (ptr));
02061       OUTS (outf, "] (Z)");
02062     }
02063   else if (aop == 2 && sz == 2 && Z == 1 && W == 0)
02064     {
02065       OUTS (outf, dregs (reg));
02066       OUTS (outf, "=B[");
02067       OUTS (outf, pregs (ptr));
02068       OUTS (outf, "](X)");
02069     }
02070   else if (aop == 0 && sz == 0 && Z == 0 && W == 1)
02071     {
02072       OUTS (outf, "[");
02073       OUTS (outf, pregs (ptr));
02074       OUTS (outf, "++]=");
02075       OUTS (outf, dregs (reg));
02076     }
02077   else if (aop == 0 && sz == 0 && Z == 1 && W == 1)
02078     {
02079       OUTS (outf, "[");
02080       OUTS (outf, pregs (ptr));
02081       OUTS (outf, "++]=");
02082       OUTS (outf, pregs (reg));
02083     }
02084   else if (aop == 0 && sz == 1 && Z == 0 && W == 1)
02085     {
02086       OUTS (outf, "W[");
02087       OUTS (outf, pregs (ptr));
02088       OUTS (outf, "++]=");
02089       OUTS (outf, dregs (reg));
02090     }
02091   else if (aop == 0 && sz == 2 && Z == 0 && W == 1)
02092     {
02093       OUTS (outf, "B[");
02094       OUTS (outf, pregs (ptr));
02095       OUTS (outf, "++]=");
02096       OUTS (outf, dregs (reg));
02097     }
02098   else if (aop == 1 && sz == 0 && Z == 0 && W == 1)
02099     {
02100       OUTS (outf, "[");
02101       OUTS (outf, pregs (ptr));
02102       OUTS (outf, "--]=");
02103       OUTS (outf, dregs (reg));
02104     }
02105   else if (aop == 1 && sz == 0 && Z == 1 && W == 1)
02106     {
02107       OUTS (outf, "[");
02108       OUTS (outf, pregs (ptr));
02109       OUTS (outf, "--]=");
02110       OUTS (outf, pregs (reg));
02111     }
02112   else if (aop == 1 && sz == 1 && Z == 0 && W == 1)
02113     {
02114       OUTS (outf, "W[");
02115       OUTS (outf, pregs (ptr));
02116       OUTS (outf, "--]=");
02117       OUTS (outf, dregs (reg));
02118     }
02119   else if (aop == 1 && sz == 2 && Z == 0 && W == 1)
02120     {
02121       OUTS (outf, "B[");
02122       OUTS (outf, pregs (ptr));
02123       OUTS (outf, "--]=");
02124       OUTS (outf, dregs (reg));
02125     }
02126   else if (aop == 2 && sz == 0 && Z == 0 && W == 1)
02127     {
02128       OUTS (outf, "[");
02129       OUTS (outf, pregs (ptr));
02130       OUTS (outf, "]=");
02131       OUTS (outf, dregs (reg));
02132     }
02133   else if (aop == 2 && sz == 0 && Z == 1 && W == 1)
02134     {
02135       OUTS (outf, "[");
02136       OUTS (outf, pregs (ptr));
02137       OUTS (outf, "]=");
02138       OUTS (outf, pregs (reg));
02139     }
02140   else if (aop == 2 && sz == 1 && Z == 0 && W == 1)
02141     {
02142       OUTS (outf, "W[");
02143       OUTS (outf, pregs (ptr));
02144       OUTS (outf, "]=");
02145       OUTS (outf, dregs (reg));
02146     }
02147   else if (aop == 2 && sz == 2 && Z == 0 && W == 1)
02148     {
02149       OUTS (outf, "B[");
02150       OUTS (outf, pregs (ptr));
02151       OUTS (outf, "]=");
02152       OUTS (outf, dregs (reg));
02153     }
02154   else
02155     return 0;
02156 
02157   return 2;
02158 }
02159 
02160 static int
02161 decode_LDSTiiFP_0 (TIword iw0, disassemble_info *outf)
02162 {
02163   /* LDSTiiFP
02164      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02165      | 1 | 0 | 1 | 1 | 1 | 0 |.W.|.offset............|.reg...........|
02166      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02167   int reg = ((iw0 >> LDSTiiFP_reg_bits) & LDSTiiFP_reg_mask);
02168   int offset = ((iw0 >> LDSTiiFP_offset_bits) & LDSTiiFP_offset_mask);
02169   int W = ((iw0 >> LDSTiiFP_W_bits) & LDSTiiFP_W_mask);
02170 
02171   if (W == 0)
02172     {
02173       OUTS (outf, dpregs (reg));
02174       OUTS (outf, "=[FP");
02175       OUTS (outf, negimm5s4 (offset));
02176       OUTS (outf, "]");
02177     }
02178   else if (W == 1)
02179     {
02180       OUTS (outf, "[FP");
02181       OUTS (outf, negimm5s4 (offset));
02182       OUTS (outf, "]=");
02183       OUTS (outf, dpregs (reg));
02184     }
02185   else
02186     return 0;
02187 
02188   return 2;
02189 }
02190 
02191 static int
02192 decode_LDSTii_0 (TIword iw0, disassemble_info *outf)
02193 {
02194   /* LDSTii
02195      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02196      | 1 | 0 | 1 |.W.|.op....|.offset........|.ptr.......|.reg.......|
02197      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02198   int reg = ((iw0 >> LDSTii_reg_bit) & LDSTii_reg_mask);
02199   int ptr = ((iw0 >> LDSTii_ptr_bit) & LDSTii_ptr_mask);
02200   int offset = ((iw0 >> LDSTii_offset_bit) & LDSTii_offset_mask);
02201   int op = ((iw0 >> LDSTii_op_bit) & LDSTii_op_mask);
02202   int W = ((iw0 >> LDSTii_W_bit) & LDSTii_W_mask);
02203 
02204   if (W == 0 && op == 0)
02205     {
02206       OUTS (outf, dregs (reg));
02207       OUTS (outf, "=[");
02208       OUTS (outf, pregs (ptr));
02209       OUTS (outf, "+");
02210       OUTS (outf, uimm4s4 (offset));
02211       OUTS (outf, "]");
02212     }
02213   else if (W == 0 && op == 1)
02214     {
02215       OUTS (outf, dregs (reg));
02216       OUTS (outf, "=W[");
02217       OUTS (outf, pregs (ptr));
02218       OUTS (outf, "+");
02219       OUTS (outf, uimm4s2 (offset));
02220       OUTS (outf, "] (Z)");
02221     }
02222   else if (W == 0 && op == 2)
02223     {
02224       OUTS (outf, dregs (reg));
02225       OUTS (outf, "=W[");
02226       OUTS (outf, pregs (ptr));
02227       OUTS (outf, "+");
02228       OUTS (outf, uimm4s2 (offset));
02229       OUTS (outf, "](X)");
02230     }
02231   else if (W == 0 && op == 3)
02232     {
02233       OUTS (outf, pregs (reg));
02234       OUTS (outf, "=[");
02235       OUTS (outf, pregs (ptr));
02236       OUTS (outf, "+");
02237       OUTS (outf, uimm4s4 (offset));
02238       OUTS (outf, "]");
02239     }
02240   else if (W == 1 && op == 0)
02241     {
02242       OUTS (outf, "[");
02243       OUTS (outf, pregs (ptr));
02244       OUTS (outf, "+");
02245       OUTS (outf, uimm4s4 (offset));
02246       OUTS (outf, "]=");
02247       OUTS (outf, dregs (reg));
02248     }
02249   else if (W == 1 && op == 1)
02250     {
02251       OUTS (outf, "W");
02252       OUTS (outf, "[");
02253       OUTS (outf, pregs (ptr));
02254       OUTS (outf, "+");
02255       OUTS (outf, uimm4s2 (offset));
02256       OUTS (outf, "]");
02257       OUTS (outf, "=");
02258       OUTS (outf, dregs (reg));
02259     }
02260   else if (W == 1 && op == 3)
02261     {
02262       OUTS (outf, "[");
02263       OUTS (outf, pregs (ptr));
02264       OUTS (outf, "+");
02265       OUTS (outf, uimm4s4 (offset));
02266       OUTS (outf, "]=");
02267       OUTS (outf, pregs (reg));
02268     }
02269   else
02270     return 0;
02271 
02272   return 2;
02273 }
02274 
02275 static int
02276 decode_LoopSetup_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
02277 {
02278   /* LoopSetup
02279      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02280      | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |.rop...|.c.|.soffset.......|
02281      |.reg...........| - | - |.eoffset...............................|
02282      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02283   int c   = ((iw0 >> (LoopSetup_c_bits - 16)) & LoopSetup_c_mask);
02284   int reg = ((iw1 >> LoopSetup_reg_bits) & LoopSetup_reg_mask);
02285   int rop = ((iw0 >> (LoopSetup_rop_bits - 16)) & LoopSetup_rop_mask);
02286   int soffset = ((iw0 >> (LoopSetup_soffset_bits - 16)) & LoopSetup_soffset_mask);
02287   int eoffset = ((iw1 >> LoopSetup_eoffset_bits) & LoopSetup_eoffset_mask);
02288 
02289   if (rop == 0)
02290     {
02291       OUTS (outf, "LSETUP");
02292       OUTS (outf, "(");
02293       OUTS (outf, pcrel4 (soffset));
02294       OUTS (outf, ",");
02295       OUTS (outf, lppcrel10 (eoffset));
02296       OUTS (outf, ")");
02297       OUTS (outf, counters (c));
02298     }
02299   else if (rop == 1)
02300     {
02301       OUTS (outf, "LSETUP");
02302       OUTS (outf, "(");
02303       OUTS (outf, pcrel4 (soffset));
02304       OUTS (outf, ",");
02305       OUTS (outf, lppcrel10 (eoffset));
02306       OUTS (outf, ")");
02307       OUTS (outf, counters (c));
02308       OUTS (outf, "=");
02309       OUTS (outf, pregs (reg));
02310     }
02311   else if (rop == 3)
02312     {
02313       OUTS (outf, "LSETUP");
02314       OUTS (outf, "(");
02315       OUTS (outf, pcrel4 (soffset));
02316       OUTS (outf, ",");
02317       OUTS (outf, lppcrel10 (eoffset));
02318       OUTS (outf, ")");
02319       OUTS (outf, counters (c));
02320       OUTS (outf, "=");
02321       OUTS (outf, pregs (reg));
02322       OUTS (outf, ">>1");
02323     }
02324   else
02325     return 0;
02326 
02327   return 4;
02328 }
02329 
02330 static int
02331 decode_LDIMMhalf_0 (TIword iw0, TIword iw1, disassemble_info *outf)
02332 {
02333   /* LDIMMhalf
02334      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02335      | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |.Z.|.H.|.S.|.grp...|.reg.......|
02336      |.hword.........................................................|
02337      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02338   int H = ((iw0 >> (LDIMMhalf_H_bits - 16)) & LDIMMhalf_H_mask);
02339   int Z = ((iw0 >> (LDIMMhalf_Z_bits - 16)) & LDIMMhalf_Z_mask);
02340   int S = ((iw0 >> (LDIMMhalf_S_bits - 16)) & LDIMMhalf_S_mask);
02341   int reg = ((iw0 >> (LDIMMhalf_reg_bits - 16)) & LDIMMhalf_reg_mask);
02342   int grp = ((iw0 >> (LDIMMhalf_grp_bits - 16)) & LDIMMhalf_grp_mask);
02343   int hword = ((iw1 >> LDIMMhalf_hword_bits) & LDIMMhalf_hword_mask);
02344 
02345   if (grp == 0 && H == 0 && S == 0 && Z == 0)
02346     {
02347       OUTS (outf, dregs_lo (reg));
02348       OUTS (outf, "=");
02349       OUTS (outf, imm16 (hword));
02350     }
02351   else if (grp == 0 && H == 1 && S == 0 && Z == 0)
02352     {
02353       OUTS (outf, dregs_hi (reg));
02354       OUTS (outf, "=");
02355       OUTS (outf, imm16 (hword));
02356     }
02357   else if (grp == 0 && H == 0 && S == 1 && Z == 0)
02358     {
02359       OUTS (outf, dregs (reg));
02360       OUTS (outf, "=");
02361       OUTS (outf, imm16 (hword));
02362       OUTS (outf, " (X)");
02363     }
02364   else if (H == 0 && S == 1 && Z == 0)
02365     {
02366       OUTS (outf, regs (reg, grp));
02367       OUTS (outf, "=");
02368       OUTS (outf, imm16 (hword));
02369       OUTS (outf, " (X)");
02370     }
02371   else if (H == 0 && S == 0 && Z == 1)
02372     {
02373       OUTS (outf, regs (reg, grp));
02374       OUTS (outf, "=");
02375       OUTS (outf, luimm16 (hword));
02376       OUTS (outf, "(Z)");
02377     }
02378   else if (H == 0 && S == 0 && Z == 0)
02379     {
02380       OUTS (outf, regs_lo (reg, grp));
02381       OUTS (outf, "=");
02382       OUTS (outf, luimm16 (hword));
02383     }
02384   else if (H == 1 && S == 0 && Z == 0)
02385     {
02386       OUTS (outf, regs_hi (reg, grp));
02387       OUTS (outf, "=");
02388       OUTS (outf, huimm16 (hword));
02389     }
02390   else
02391     return 0;
02392 
02393   return 4;
02394 }
02395 
02396 static int
02397 decode_CALLa_0 (TIword iw0, TIword iw1, bfd_vma pc, disassemble_info *outf)
02398 {
02399   /* CALLa
02400      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02401      | 1 | 1 | 1 | 0 | 0 | 0 | 1 |.S.|.msw...........................|
02402      |.lsw...........................................................|
02403      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02404   int S   = ((iw0 >> (CALLa_S_bits - 16)) & CALLa_S_mask);
02405   int lsw = ((iw1 >> 0) & 0xffff);
02406   int msw = ((iw0 >> 0) & 0xff);
02407 
02408   if (S == 1)
02409     OUTS (outf, "CALL  ");
02410   else if (S == 0)
02411     OUTS (outf, "JUMP.L  ");
02412   else
02413     return 0;
02414 
02415   OUTS (outf, pcrel24 (((msw) << 16) | (lsw)));
02416   return 4;
02417 }
02418 
02419 static int
02420 decode_LDSTidxI_0 (TIword iw0, TIword iw1, disassemble_info *outf)
02421 {
02422   /* LDSTidxI
02423      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02424      | 1 | 1 | 1 | 0 | 0 | 1 |.W.|.Z.|.sz....|.ptr.......|.reg.......|
02425      |.offset........................................................|
02426      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02427   int Z = ((iw0 >> (LDSTidxI_Z_bits - 16)) & LDSTidxI_Z_mask);
02428   int W = ((iw0 >> (LDSTidxI_W_bits - 16)) & LDSTidxI_W_mask);
02429   int sz = ((iw0 >> (LDSTidxI_sz_bits - 16)) & LDSTidxI_sz_mask);
02430   int reg = ((iw0 >> (LDSTidxI_reg_bits - 16)) & LDSTidxI_reg_mask);
02431   int ptr = ((iw0 >> (LDSTidxI_ptr_bits - 16)) & LDSTidxI_ptr_mask);
02432   int offset = ((iw1 >> LDSTidxI_offset_bits) & LDSTidxI_offset_mask);
02433 
02434   if (W == 0 && sz == 0 && Z == 0)
02435     {
02436       OUTS (outf, dregs (reg));
02437       OUTS (outf, "=[");
02438       OUTS (outf, pregs (ptr));
02439       OUTS (outf, "+");
02440       OUTS (outf, imm16s4 (offset));
02441       OUTS (outf, "]");
02442     }
02443   else if (W == 0 && sz == 0 && Z == 1)
02444     {
02445       OUTS (outf, pregs (reg));
02446       OUTS (outf, "=[");
02447       OUTS (outf, pregs (ptr));
02448       OUTS (outf, "+");
02449       OUTS (outf, imm16s4 (offset));
02450       OUTS (outf, "]");
02451     }
02452   else if (W == 0 && sz == 1 && Z == 0)
02453     {
02454       OUTS (outf, dregs (reg));
02455       OUTS (outf, "=W[");
02456       OUTS (outf, pregs (ptr));
02457       OUTS (outf, "+");
02458       OUTS (outf, imm16s2 (offset));
02459       OUTS (outf, "] (Z)");
02460     }
02461   else if (W == 0 && sz == 1 && Z == 1)
02462     {
02463       OUTS (outf, dregs (reg));
02464       OUTS (outf, "=W[");
02465       OUTS (outf, pregs (ptr));
02466       OUTS (outf, "+");
02467       OUTS (outf, imm16s2 (offset));
02468       OUTS (outf, "](X)");
02469     }
02470   else if (W == 0 && sz == 2 && Z == 0)
02471     {
02472       OUTS (outf, dregs (reg));
02473       OUTS (outf, "=B[");
02474       OUTS (outf, pregs (ptr));
02475       OUTS (outf, "+");
02476       OUTS (outf, imm16 (offset));
02477       OUTS (outf, "] (Z)");
02478     }
02479   else if (W == 0 && sz == 2 && Z == 1)
02480     {
02481       OUTS (outf, dregs (reg));
02482       OUTS (outf, "=B[");
02483       OUTS (outf, pregs (ptr));
02484       OUTS (outf, "+");
02485       OUTS (outf, imm16 (offset));
02486       OUTS (outf, "](X)");
02487     }
02488   else if (W == 1 && sz == 0 && Z == 0)
02489     {
02490       OUTS (outf, "[");
02491       OUTS (outf, pregs (ptr));
02492       OUTS (outf, "+");
02493       OUTS (outf, imm16s4 (offset));
02494       OUTS (outf, "]=");
02495       OUTS (outf, dregs (reg));
02496     }
02497   else if (W == 1 && sz == 0 && Z == 1)
02498     {
02499       OUTS (outf, "[");
02500       OUTS (outf, pregs (ptr));
02501       OUTS (outf, "+");
02502       OUTS (outf, imm16s4 (offset));
02503       OUTS (outf, "]=");
02504       OUTS (outf, pregs (reg));
02505     }
02506   else if (W == 1 && sz == 1 && Z == 0)
02507     {
02508       OUTS (outf, "W[");
02509       OUTS (outf, pregs (ptr));
02510       OUTS (outf, "+");
02511       OUTS (outf, imm16s2 (offset));
02512       OUTS (outf, "]=");
02513       OUTS (outf, dregs (reg));
02514     }
02515   else if (W == 1 && sz == 2 && Z == 0)
02516     {
02517       OUTS (outf, "B[");
02518       OUTS (outf, pregs (ptr));
02519       OUTS (outf, "+");
02520       OUTS (outf, imm16 (offset));
02521       OUTS (outf, "]=");
02522       OUTS (outf, dregs (reg));
02523     }
02524   else
02525     return 0;
02526 
02527   return 4;
02528 }
02529 
02530 static int
02531 decode_linkage_0 (TIword iw0, TIword iw1, disassemble_info *outf)
02532 {
02533   /* linkage
02534      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02535      | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |.R.|
02536      |.framesize.....................................................|
02537      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02538   int R = ((iw0 >> (Linkage_R_bits - 16)) & Linkage_R_mask);
02539   int framesize = ((iw1 >> Linkage_framesize_bits) & Linkage_framesize_mask);
02540 
02541   if (R == 0)
02542     {
02543       OUTS (outf, "LINK ");
02544       OUTS (outf, uimm16s4 (framesize));
02545     }
02546   else if (R == 1)
02547     OUTS (outf, "UNLINK");
02548   else
02549     return 0;
02550 
02551   return 4;
02552 }
02553 
02554 static int
02555 decode_dsp32mac_0 (TIword iw0, TIword iw1, disassemble_info *outf)
02556 {
02557   /* dsp32mac
02558      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02559      | 1 | 1 | 0 | 0 |.M.| 0 | 0 |.mmod..........|.MM|.P.|.w1|.op1...|
02560      |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
02561      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02562   int op1  = ((iw0 >> (DSP32Mac_op1_bits - 16)) & DSP32Mac_op1_mask);
02563   int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
02564   int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
02565   int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
02566   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
02567   int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
02568   int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
02569   int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
02570   int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
02571   int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
02572   int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
02573   int op0  = ((iw1 >> DSP32Mac_op0_bits) & DSP32Mac_op0_mask);
02574   int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
02575   int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
02576 
02577   if (w0 == 0 && w1 == 0 && op1 == 3 && op0 == 3)
02578     return 0;
02579 
02580   if (op1 == 3 && MM)
02581     return 0;
02582 
02583   if ((w1 || w0) && mmod == M_W32)
02584     return 0;
02585 
02586   if (((1 << mmod) & (P ? 0x31b : 0x1b5f)) == 0)
02587     return 0;
02588 
02589   if (w1 == 1 || op1 != 3)
02590     {
02591       if (w1)
02592        OUTS (outf, P ? dregs (dst + 1) : dregs_hi (dst));
02593 
02594       if (op1 == 3)
02595        OUTS (outf, " = A1");
02596       else
02597        {
02598          if (w1)
02599            OUTS (outf, " = (");
02600          decode_macfunc (1, op1, h01, h11, src0, src1, outf);
02601          if (w1)
02602            OUTS (outf, ")");
02603        }
02604 
02605       if (w0 == 1 || op0 != 3)
02606        {
02607          if (MM)
02608            OUTS (outf, " (M)");
02609          MM = 0;
02610          OUTS (outf, ", ");
02611        }
02612     }
02613 
02614   if (w0 == 1 || op0 != 3)
02615     {
02616       if (w0)
02617        OUTS (outf, P ? dregs (dst) : dregs_lo (dst));
02618 
02619       if (op0 == 3)
02620        OUTS (outf, " = A0");
02621       else
02622        {
02623          if (w0)
02624            OUTS (outf, " = (");
02625          decode_macfunc (0, op0, h00, h10, src0, src1, outf);
02626          if (w0)
02627            OUTS (outf, ")");
02628        }
02629     }
02630 
02631   decode_optmode (mmod, MM, outf);
02632 
02633   return 4;
02634 }
02635 
02636 static int
02637 decode_dsp32mult_0 (TIword iw0, TIword iw1, disassemble_info *outf)
02638 {
02639   /* dsp32mult
02640      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02641      | 1 | 1 | 0 | 0 |.M.| 0 | 1 |.mmod..........|.MM|.P.|.w1|.op1...|
02642      |.h01|.h11|.w0|.op0...|.h00|.h10|.dst.......|.src0......|.src1..|
02643      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02644   int w1   = ((iw0 >> (DSP32Mac_w1_bits - 16)) & DSP32Mac_w1_mask);
02645   int P    = ((iw0 >> (DSP32Mac_p_bits - 16)) & DSP32Mac_p_mask);
02646   int MM   = ((iw0 >> (DSP32Mac_MM_bits - 16)) & DSP32Mac_MM_mask);
02647   int mmod = ((iw0 >> (DSP32Mac_mmod_bits - 16)) & DSP32Mac_mmod_mask);
02648   int w0   = ((iw1 >> DSP32Mac_w0_bits) & DSP32Mac_w0_mask);
02649   int src0 = ((iw1 >> DSP32Mac_src0_bits) & DSP32Mac_src0_mask);
02650   int src1 = ((iw1 >> DSP32Mac_src1_bits) & DSP32Mac_src1_mask);
02651   int dst  = ((iw1 >> DSP32Mac_dst_bits) & DSP32Mac_dst_mask);
02652   int h10  = ((iw1 >> DSP32Mac_h10_bits) & DSP32Mac_h10_mask);
02653   int h00  = ((iw1 >> DSP32Mac_h00_bits) & DSP32Mac_h00_mask);
02654   int h11  = ((iw1 >> DSP32Mac_h11_bits) & DSP32Mac_h11_mask);
02655   int h01  = ((iw1 >> DSP32Mac_h01_bits) & DSP32Mac_h01_mask);
02656 
02657   if (w1 == 0 && w0 == 0)
02658     return 0;
02659 
02660   if (((1 << mmod) & (P ? 0x313 : 0x1b57)) == 0)
02661     return 0;
02662 
02663   if (w1)
02664     {
02665       OUTS (outf, P ? dregs (dst | 1) : dregs_hi (dst));
02666       OUTS (outf, " = ");
02667       decode_multfunc (h01, h11, src0, src1, outf);
02668 
02669       if (w0)
02670        {
02671          if (MM)
02672            OUTS (outf, " (M)");
02673          MM = 0;
02674          OUTS (outf, ", ");
02675        }
02676     }
02677 
02678   if (w0)
02679     {
02680       OUTS (outf, dregs (dst));
02681       OUTS (outf, " = ");
02682       decode_multfunc (h00, h10, src0, src1, outf);
02683     }
02684 
02685   decode_optmode (mmod, MM, outf);
02686   return 4;
02687 }
02688 
02689 static int
02690 decode_dsp32alu_0 (TIword iw0, TIword iw1, disassemble_info *outf)
02691 {
02692   /* dsp32alu
02693      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
02694      | 1 | 1 | 0 | 0 |.M.| 1 | 0 | - | - | - |.HL|.aopcde............|
02695      |.aop...|.s.|.x.|.dst0......|.dst1......|.src0......|.src1......|
02696      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
02697   int s    = ((iw1 >> DSP32Alu_s_bits) & DSP32Alu_s_mask);
02698   int x    = ((iw1 >> DSP32Alu_x_bits) & DSP32Alu_x_mask);
02699   int aop  = ((iw1 >> DSP32Alu_aop_bits) & DSP32Alu_aop_mask);
02700   int src0 = ((iw1 >> DSP32Alu_src0_bits) & DSP32Alu_src0_mask);
02701   int src1 = ((iw1 >> DSP32Alu_src1_bits) & DSP32Alu_src1_mask);
02702   int dst0 = ((iw1 >> DSP32Alu_dst0_bits) & DSP32Alu_dst0_mask);
02703   int dst1 = ((iw1 >> DSP32Alu_dst1_bits) & DSP32Alu_dst1_mask);
02704   int HL   = ((iw0 >> (DSP32Alu_HL_bits - 16)) & DSP32Alu_HL_mask);
02705   int aopcde = ((iw0 >> (DSP32Alu_aopcde_bits - 16)) & DSP32Alu_aopcde_mask);
02706 
02707   if (aop == 0 && aopcde == 9 && HL == 0 && s == 0)
02708     {
02709       OUTS (outf, "A0.L=");
02710       OUTS (outf, dregs_lo (src0));
02711     }
02712   else if (aop == 2 && aopcde == 9 && HL == 1 && s == 0)
02713     {
02714       OUTS (outf, "A1.H=");
02715       OUTS (outf, dregs_hi (src0));
02716     }
02717   else if (aop == 2 && aopcde == 9 && HL == 0 && s == 0)
02718     {
02719       OUTS (outf, "A1.L=");
02720       OUTS (outf, dregs_lo (src0));
02721     }
02722   else if (aop == 0 && aopcde == 9 && HL == 1 && s == 0)
02723     {
02724       OUTS (outf, "A0.H=");
02725       OUTS (outf, dregs_hi (src0));
02726     }
02727   else if (x == 1 && HL == 1 && aop == 3 && aopcde == 5)
02728     {
02729       OUTS (outf, dregs_hi (dst0));
02730       OUTS (outf, "=");
02731       OUTS (outf, dregs (src0));
02732       OUTS (outf, "-");
02733       OUTS (outf, dregs (src1));
02734       OUTS (outf, "(RND20)");
02735     }
02736   else if (x == 1 && HL == 1 && aop == 2 && aopcde == 5)
02737     {
02738       OUTS (outf, dregs_hi (dst0));
02739       OUTS (outf, "=");
02740       OUTS (outf, dregs (src0));
02741       OUTS (outf, "+");
02742       OUTS (outf, dregs (src1));
02743       OUTS (outf, "(RND20)");
02744     }
02745   else if (x == 0 && HL == 0 && aop == 1 && aopcde == 5)
02746     {
02747       OUTS (outf, dregs_lo (dst0));
02748       OUTS (outf, "=");
02749       OUTS (outf, dregs (src0));
02750       OUTS (outf, "-");
02751       OUTS (outf, dregs (src1));
02752       OUTS (outf, "(RND12)");
02753     }
02754   else if (x == 0 && HL == 0 && aop == 0 && aopcde == 5)
02755     {
02756       OUTS (outf, dregs_lo (dst0));
02757       OUTS (outf, "=");
02758       OUTS (outf, dregs (src0));
02759       OUTS (outf, "+");
02760       OUTS (outf, dregs (src1));
02761       OUTS (outf, "(RND12)");
02762     }
02763   else if (x == 1 && HL == 0 && aop == 3 && aopcde == 5)
02764     {
02765       OUTS (outf, dregs_lo (dst0));
02766       OUTS (outf, "=");
02767       OUTS (outf, dregs (src0));
02768       OUTS (outf, "-");
02769       OUTS (outf, dregs (src1));
02770       OUTS (outf, "(RND20)");
02771     }
02772   else if (x == 0 && HL == 1 && aop == 0 && aopcde == 5)
02773     {
02774       OUTS (outf, dregs_hi (dst0));
02775       OUTS (outf, "=");
02776       OUTS (outf, dregs (src0));
02777       OUTS (outf, "+");
02778       OUTS (outf, dregs (src1));
02779       OUTS (outf, "(RND12)");
02780     }
02781   else if (x == 1 && HL == 0 && aop == 2 && aopcde == 5)
02782     {
02783       OUTS (outf, dregs_lo (dst0));
02784       OUTS (outf, "=");
02785       OUTS (outf, dregs (src0));
02786       OUTS (outf, "+");
02787       OUTS (outf, dregs (src1));
02788       OUTS (outf, "(RND20)");
02789     }
02790   else if (x == 0 && HL == 1 && aop == 1 && aopcde == 5)
02791     {
02792       OUTS (outf, dregs_hi (dst0));
02793       OUTS (outf, "=");
02794       OUTS (outf, dregs (src0));
02795       OUTS (outf, "-");
02796       OUTS (outf, dregs (src1));
02797       OUTS (outf, "(RND12)");
02798     }
02799   else if (HL == 1 && aop == 0 && aopcde == 2)
02800     {
02801       OUTS (outf, dregs_hi (dst0));
02802       OUTS (outf, "=");
02803       OUTS (outf, dregs_lo (src0));
02804       OUTS (outf, "+");
02805       OUTS (outf, dregs_lo (src1));
02806       OUTS (outf, " ");
02807       amod1 (s, x, outf);
02808     }
02809   else if (HL == 1 && aop == 1 && aopcde == 2)
02810     {
02811       OUTS (outf, dregs_hi (dst0));
02812       OUTS (outf, "=");
02813       OUTS (outf, dregs_lo (src0));
02814       OUTS (outf, "+");
02815       OUTS (outf, dregs_hi (src1));
02816       OUTS (outf, " ");
02817       amod1 (s, x, outf);
02818     }
02819   else if (HL == 1 && aop == 2 && aopcde == 2)
02820     {
02821       OUTS (outf, dregs_hi (dst0));
02822       OUTS (outf, "=");
02823       OUTS (outf, dregs_hi (src0));
02824       OUTS (outf, "+");
02825       OUTS (outf, dregs_lo (src1));
02826       OUTS (outf, " ");
02827       amod1 (s, x, outf);
02828     }
02829   else if (HL == 1 && aop == 3 && aopcde == 2)
02830     {
02831       OUTS (outf, dregs_hi (dst0));
02832       OUTS (outf, "=");
02833       OUTS (outf, dregs_hi (src0));
02834       OUTS (outf, "+");
02835       OUTS (outf, dregs_hi (src1));
02836       OUTS (outf, " ");
02837       amod1 (s, x, outf);
02838     }
02839   else if (HL == 0 && aop == 0 && aopcde == 3)
02840     {
02841       OUTS (outf, dregs_lo (dst0));
02842       OUTS (outf, "=");
02843       OUTS (outf, dregs_lo (src0));
02844       OUTS (outf, "-");
02845       OUTS (outf, dregs_lo (src1));
02846       OUTS (outf, " ");
02847       amod1 (s, x, outf);
02848     }
02849   else if (HL == 0 && aop == 1 && aopcde == 3)
02850     {
02851       OUTS (outf, dregs_lo (dst0));
02852       OUTS (outf, "=");
02853       OUTS (outf, dregs_lo (src0));
02854       OUTS (outf, "-");
02855       OUTS (outf, dregs_hi (src1));
02856       OUTS (outf, " ");
02857       amod1 (s, x, outf);
02858     }
02859   else if (HL == 0 && aop == 3 && aopcde == 2)
02860     {
02861       OUTS (outf, dregs_lo (dst0));
02862       OUTS (outf, "=");
02863       OUTS (outf, dregs_hi (src0));
02864       OUTS (outf, "+");
02865       OUTS (outf, dregs_hi (src1));
02866       OUTS (outf, " ");
02867       amod1 (s, x, outf);
02868     }
02869   else if (HL == 1 && aop == 0 && aopcde == 3)
02870     {
02871       OUTS (outf, dregs_hi (dst0));
02872       OUTS (outf, "=");
02873       OUTS (outf, dregs_lo (src0));
02874       OUTS (outf, "-");
02875       OUTS (outf, dregs_lo (src1));
02876       OUTS (outf, " ");
02877       amod1 (s, x, outf);
02878     }
02879   else if (HL == 1 && aop == 1 && aopcde == 3)
02880     {
02881       OUTS (outf, dregs_hi (dst0));
02882       OUTS (outf, "=");
02883       OUTS (outf, dregs_lo (src0));
02884       OUTS (outf, "-");
02885       OUTS (outf, dregs_hi (src1));
02886       OUTS (outf, " ");
02887       amod1 (s, x, outf);
02888     }
02889   else if (HL == 1 && aop == 2 && aopcde == 3)
02890     {
02891       OUTS (outf, dregs_hi (dst0));
02892       OUTS (outf, "=");
02893       OUTS (outf, dregs_hi (src0));
02894       OUTS (outf, "-");
02895       OUTS (outf, dregs_lo (src1));
02896       OUTS (outf, " ");
02897       amod1 (s, x, outf);
02898     }
02899   else if (HL == 1 && aop == 3 && aopcde == 3)
02900     {
02901       OUTS (outf, dregs_hi (dst0));
02902       OUTS (outf, "=");
02903       OUTS (outf, dregs_hi (src0));
02904       OUTS (outf, "-");
02905       OUTS (outf, dregs_hi (src1));
02906       OUTS (outf, " ");
02907       amod1 (s, x, outf);
02908     }
02909   else if (HL == 0 && aop == 2 && aopcde == 2)
02910     {
02911       OUTS (outf, dregs_lo (dst0));
02912       OUTS (outf, "=");
02913       OUTS (outf, dregs_hi (src0));
02914       OUTS (outf, "+");
02915       OUTS (outf, dregs_lo (src1));
02916       OUTS (outf, " ");
02917       amod1 (s, x, outf);
02918     }
02919   else if (HL == 0 && aop == 1 && aopcde == 2)
02920     {
02921       OUTS (outf, dregs_lo (dst0));
02922       OUTS (outf, "=");
02923       OUTS (outf, dregs_lo (src0));
02924       OUTS (outf, "+");
02925       OUTS (outf, dregs_hi (src1));
02926       OUTS (outf, " ");
02927       amod1 (s, x, outf);
02928     }
02929   else if (HL == 0 && aop == 2 && aopcde == 3)
02930     {
02931       OUTS (outf, dregs_lo (dst0));
02932       OUTS (outf, "=");
02933       OUTS (outf, dregs_hi (src0));
02934       OUTS (outf, "-");
02935       OUTS (outf, dregs_lo (src1));
02936       OUTS (outf, " ");
02937       amod1 (s, x, outf);
02938     }
02939   else if (HL == 0 && aop == 3 && aopcde == 3)
02940     {
02941       OUTS (outf, dregs_lo (dst0));
02942       OUTS (outf, "=");
02943       OUTS (outf, dregs_hi (src0));
02944       OUTS (outf, "-");
02945       OUTS (outf, dregs_hi (src1));
02946       OUTS (outf, " ");
02947       amod1 (s, x, outf);
02948     }
02949   else if (HL == 0 && aop == 0 && aopcde == 2)
02950     {
02951       OUTS (outf, dregs_lo (dst0));
02952       OUTS (outf, "=");
02953       OUTS (outf, dregs_lo (src0));
02954       OUTS (outf, "+");
02955       OUTS (outf, dregs_lo (src1));
02956       OUTS (outf, " ");
02957       amod1 (s, x, outf);
02958     }
02959   else if (aop == 0 && aopcde == 9 && s == 1)
02960     {
02961       OUTS (outf, "A0=");
02962       OUTS (outf, dregs (src0));
02963     }
02964   else if (aop == 3 && aopcde == 11 && s == 0)
02965     OUTS (outf, "A0-=A1");
02966 
02967   else if (aop == 3 && aopcde == 11 && s == 1)
02968     OUTS (outf, "A0-=A1(W32)");
02969 
02970   else if (aop == 3 && aopcde == 22 && HL == 1)
02971     {
02972       OUTS (outf, dregs (dst0));
02973       OUTS (outf, "=BYTEOP2M(");
02974       OUTS (outf, dregs (src0 + 1));
02975       OUTS (outf, ":");
02976       OUTS (outf, imm5 (src0));
02977       OUTS (outf, ",");
02978       OUTS (outf, dregs (src1 + 1));
02979       OUTS (outf, ":");
02980       OUTS (outf, imm5 (src1));
02981       OUTS (outf, ")(TH");
02982       if (s == 1)
02983        OUTS (outf, ", R)");
02984       else
02985        OUTS (outf, ")");
02986     }
02987   else if (aop == 3 && aopcde == 22 && HL == 0)
02988     {
02989       OUTS (outf, dregs (dst0));
02990       OUTS (outf, "=BYTEOP2M(");
02991       OUTS (outf, dregs (src0 + 1));
02992       OUTS (outf, ":");
02993       OUTS (outf, imm5 (src0));
02994       OUTS (outf, ",");
02995       OUTS (outf, dregs (src1 + 1));
02996       OUTS (outf, ":");
02997       OUTS (outf, imm5 (src1));
02998       OUTS (outf, ")(TL");
02999       if (s == 1)
03000        OUTS (outf, ", R)");
03001       else
03002        OUTS (outf, ")");
03003     }
03004   else if (aop == 2 && aopcde == 22 && HL == 1)
03005     {
03006       OUTS (outf, dregs (dst0));
03007       OUTS (outf, "=BYTEOP2M(");
03008       OUTS (outf, dregs (src0 + 1));
03009       OUTS (outf, ":");
03010       OUTS (outf, imm5 (src0));
03011       OUTS (outf, ",");
03012       OUTS (outf, dregs (src1 + 1));
03013       OUTS (outf, ":");
03014       OUTS (outf, imm5 (src1));
03015       OUTS (outf, ")(RNDH");
03016       if (s == 1)
03017        OUTS (outf, ", R)");
03018       else
03019        OUTS (outf, ")");
03020     }
03021   else if (aop == 2 && aopcde == 22 && HL == 0)
03022     {
03023       OUTS (outf, dregs (dst0));
03024       OUTS (outf, "=BYTEOP2M(");
03025       OUTS (outf, dregs (src0 + 1));
03026       OUTS (outf, ":");
03027       OUTS (outf, imm5 (src0));
03028       OUTS (outf, ",");
03029       OUTS (outf, dregs (src1 + 1));
03030       OUTS (outf, ":");
03031       OUTS (outf, imm5 (src1));
03032       OUTS (outf, ")(RNDL");
03033       if (s == 1)
03034        OUTS (outf, ", R)");
03035       else
03036        OUTS (outf, ")");
03037     }
03038   else if (aop == 1 && aopcde == 22 && HL == 1)
03039     {
03040       OUTS (outf, dregs (dst0));
03041       OUTS (outf, "=BYTEOP2P(");
03042       OUTS (outf, dregs (src0 + 1));
03043       OUTS (outf, ":");
03044       OUTS (outf, imm5 (src0));
03045       OUTS (outf, ",");
03046       OUTS (outf, dregs (src1 + 1));
03047       OUTS (outf, ":");
03048       OUTS (outf, imm5 (src1));
03049       OUTS (outf, ")(TH");
03050       if (s == 1)
03051        OUTS (outf, ", R)");
03052       else
03053        OUTS (outf, ")");
03054     }
03055   else if (aop == 1 && aopcde == 22 && HL == 0)
03056     {
03057       OUTS (outf, dregs (dst0));
03058       OUTS (outf, "=BYTEOP2P(");
03059       OUTS (outf, dregs (src0 + 1));
03060       OUTS (outf, ":");
03061       OUTS (outf, imm5 (src0));
03062       OUTS (outf, ",");
03063       OUTS (outf, dregs (src1 + 1));
03064       OUTS (outf, ":");
03065       OUTS (outf, imm5 (src1));
03066       OUTS (outf, ")(TL");
03067       if (s == 1)
03068        OUTS (outf, ", R)");
03069       else
03070        OUTS (outf, ")");
03071     }
03072   else if (aop == 0 && aopcde == 22 && HL == 1)
03073     {
03074       OUTS (outf, dregs (dst0));
03075       OUTS (outf, "=BYTEOP2P(");
03076       OUTS (outf, dregs (src0 + 1));
03077       OUTS (outf, ":");
03078       OUTS (outf, imm5 (src0));
03079       OUTS (outf, ",");
03080       OUTS (outf, dregs (src1 + 1));
03081       OUTS (outf, ":");
03082       OUTS (outf, imm5 (src1));
03083       OUTS (outf, ")(RNDH");
03084       if (s == 1)
03085        OUTS (outf, ", R)");
03086       else
03087        OUTS (outf, ")");
03088     }
03089   else if (aop == 0 && aopcde == 22 && HL == 0)
03090     {
03091       OUTS (outf, dregs (dst0));
03092       OUTS (outf, "=BYTEOP2P(");
03093       OUTS (outf, dregs (src0 + 1));
03094       OUTS (outf, ":");
03095       OUTS (outf, imm5 (src0));
03096       OUTS (outf, ",");
03097       OUTS (outf, dregs (src1 + 1));
03098       OUTS (outf, ":");
03099       OUTS (outf, imm5 (src1));
03100       OUTS (outf, ")(RNDL");
03101       if (s == 1)
03102        OUTS (outf, ", R)");
03103       else
03104        OUTS (outf, ")");
03105     }
03106   else if (aop == 0 && s == 0 && aopcde == 8)
03107     OUTS (outf, "A0=0");
03108 
03109   else if (aop == 0 && s == 1 && aopcde == 8)
03110     OUTS (outf, "A0=A0(S)");
03111 
03112   else if (aop == 1 && s == 0 && aopcde == 8)
03113     OUTS (outf, "A1=0");
03114 
03115   else if (aop == 1 && s == 1 && aopcde == 8)
03116     OUTS (outf, "A1=A1(S)");
03117 
03118   else if (aop == 2 && s == 0 && aopcde == 8)
03119     OUTS (outf, "A1=A0=0");
03120 
03121   else if (aop == 2 && s == 1 && aopcde == 8)
03122     OUTS (outf, "A1=A1(S),A0=A0(S)");
03123 
03124   else if (aop == 3 && s == 0 && aopcde == 8)
03125     OUTS (outf, "A0=A1");
03126 
03127   else if (aop == 3 && s == 1 && aopcde == 8)
03128     OUTS (outf, "A1=A0");
03129 
03130   else if (aop == 1 && aopcde == 9 && s == 0)
03131     {
03132       OUTS (outf, "A0.x=");
03133       OUTS (outf, dregs_lo (src0));
03134     }
03135   else if (aop == 1 && HL == 0 && aopcde == 11)
03136     {
03137       OUTS (outf, dregs_lo (dst0));
03138       OUTS (outf, "=(A0+=A1)");
03139     }
03140   else if (aop == 3 && HL == 0 && aopcde == 16)
03141     OUTS (outf, "A1= ABS A0,A0= ABS A0");
03142 
03143   else if (aop == 0 && aopcde == 23 && HL == 1)
03144     {
03145       OUTS (outf, dregs (dst0));
03146       OUTS (outf, "=BYTEOP3P(");
03147       OUTS (outf, dregs (src0 + 1));
03148       OUTS (outf, ":");
03149       OUTS (outf, imm5 (src0));
03150       OUTS (outf, ",");
03151       OUTS (outf, dregs (src1 + 1));
03152       OUTS (outf, ":");
03153       OUTS (outf, imm5 (src1));
03154       OUTS (outf, ")(HI");
03155       if (s == 1)
03156        OUTS (outf, ", R)");
03157       else
03158        OUTS (outf, ")");
03159     }
03160   else if (aop == 3 && aopcde == 9 && s == 0)
03161     {
03162       OUTS (outf, "A1.x=");
03163       OUTS (outf, dregs_lo (src0));
03164     }
03165   else if (aop == 1 && HL == 1 && aopcde == 16)
03166     OUTS (outf, "A1= ABS A1");
03167 
03168   else if (aop == 0 && HL == 1 && aopcde == 16)
03169     OUTS (outf, "A1= ABS A0");
03170 
03171   else if (aop == 2 && aopcde == 9 && s == 1)
03172     {
03173       OUTS (outf, "A1=");
03174       OUTS (outf, dregs (src0));
03175     }
03176   else if (HL == 0 && aop == 3 && aopcde == 12)
03177     {
03178       OUTS (outf, dregs_lo (dst0));
03179       OUTS (outf, "=");
03180       OUTS (outf, dregs (src0));
03181       OUTS (outf, "(RND)");
03182     }
03183   else if (aop == 1 && HL == 0 && aopcde == 16)
03184     OUTS (outf, "A0= ABS A1");
03185 
03186   else if (aop == 0 && HL == 0 && aopcde == 16)
03187     OUTS (outf, "A0= ABS A0");
03188 
03189   else if (aop == 3 && HL == 0 && aopcde == 15)
03190     {
03191       OUTS (outf, dregs (dst0));
03192       OUTS (outf, "=-");
03193       OUTS (outf, dregs (src0));
03194       OUTS (outf, "(V)");
03195     }
03196   else if (aop == 3 && s == 1 && HL == 0 && aopcde == 7)
03197     {
03198       OUTS (outf, dregs (dst0));
03199       OUTS (outf, "=-");
03200       OUTS (outf, dregs (src0));
03201       OUTS (outf, "(S)");
03202     }
03203   else if (aop == 3 && s == 0 && HL == 0 && aopcde == 7)
03204     {
03205       OUTS (outf, dregs (dst0));
03206       OUTS (outf, "=-");
03207       OUTS (outf, dregs (src0));
03208       OUTS (outf, "(NS)");
03209     }
03210   else if (aop == 1 && HL == 1 && aopcde == 11)
03211     {
03212       OUTS (outf, dregs_hi (dst0));
03213       OUTS (outf, "=(A0+=A1)");
03214     }
03215   else if (aop == 2 && aopcde == 11 && s == 0)
03216     OUTS (outf, "A0+=A1");
03217 
03218   else if (aop == 2 && aopcde == 11 && s == 1)
03219     OUTS (outf, "A0+=A1(W32)");
03220 
03221   else if (aop == 3 && HL == 0 && aopcde == 14)
03222     OUTS (outf, "A1=-A1,A0=-A0");
03223 
03224   else if (HL == 1 && aop == 3 && aopcde == 12)
03225     {
03226       OUTS (outf, dregs_hi (dst0));
03227       OUTS (outf, "=");
03228       OUTS (outf, dregs (src0));
03229       OUTS (outf, "(RND)");
03230     }
03231   else if (aop == 0 && aopcde == 23 && HL == 0)
03232     {
03233       OUTS (outf, dregs (dst0));
03234       OUTS (outf, "=BYTEOP3P(");
03235       OUTS (outf, dregs (src0 + 1));
03236       OUTS (outf, ":");
03237       OUTS (outf, imm5 (src0));
03238       OUTS (outf, ",");
03239       OUTS (outf, dregs (src1 + 1));
03240       OUTS (outf, ":");
03241       OUTS (outf, imm5 (src1));
03242       OUTS (outf, ")(LO");
03243       if (s == 1)
03244        OUTS (outf, ", R)");
03245       else
03246        OUTS (outf, ")");
03247     }
03248   else if (aop == 0 && HL == 0 && aopcde == 14)
03249     OUTS (outf, "A0=-A0");
03250 
03251   else if (aop == 1 && HL == 0 && aopcde == 14)
03252     OUTS (outf, "A0=-A1");
03253 
03254   else if (aop == 0 && HL == 1 && aopcde == 14)
03255     OUTS (outf, "A1=-A0");
03256 
03257   else if (aop == 1 && HL == 1 && aopcde == 14)
03258     OUTS (outf, "A1=-A1");
03259 
03260   else if (aop == 0 && aopcde == 12)
03261     {
03262       OUTS (outf, dregs_hi (dst0));
03263       OUTS (outf, "=");
03264       OUTS (outf, dregs_lo (dst0));
03265       OUTS (outf, "=SIGN(");
03266       OUTS (outf, dregs_hi (src0));
03267       OUTS (outf, ")*");
03268       OUTS (outf, dregs_hi (src1));
03269       OUTS (outf, "+SIGN(");
03270       OUTS (outf, dregs_lo (src0));
03271       OUTS (outf, ")*");
03272       OUTS (outf, dregs_lo (src1));
03273       OUTS (outf, ")");
03274     }
03275   else if (aop == 2 && aopcde == 0)
03276     {
03277       OUTS (outf, dregs (dst0));
03278       OUTS (outf, "=");
03279       OUTS (outf, dregs (src0));
03280       OUTS (outf, "-|+");
03281       OUTS (outf, dregs (src1));
03282       OUTS (outf, " ");
03283       amod0 (s, x, outf);
03284     }
03285   else if (aop == 1 && aopcde == 12)
03286     {
03287       OUTS (outf, dregs (dst1));
03288       OUTS (outf, "=A1.L+A1.H,");
03289       OUTS (outf, dregs (dst0));
03290       OUTS (outf, "=A0.L+A0.H");
03291     }
03292   else if (aop == 2 && aopcde == 4)
03293     {
03294       OUTS (outf, dregs (dst1));
03295       OUTS (outf, "=");
03296       OUTS (outf, dregs (src0));
03297       OUTS (outf, "+");
03298       OUTS (outf, dregs (src1));
03299       OUTS (outf, ",");
03300       OUTS (outf, dregs (dst0));
03301       OUTS (outf, "=");
03302       OUTS (outf, dregs (src0));
03303       OUTS (outf, "-");
03304       OUTS (outf, dregs (src1));
03305       OUTS (outf, " ");
03306       amod1 (s, x, outf);
03307     }
03308   else if (HL == 0 && aopcde == 1)
03309     {
03310       OUTS (outf, dregs (dst1));
03311       OUTS (outf, "=");
03312       OUTS (outf, dregs (src0));
03313       OUTS (outf, "+|+");
03314       OUTS (outf, dregs (src1));
03315       OUTS (outf, ",");
03316       OUTS (outf, dregs (dst0));
03317       OUTS (outf, "=");
03318       OUTS (outf, dregs (src0));
03319       OUTS (outf, "-|-");
03320       OUTS (outf, dregs (src1));
03321       amod0amod2 (s, x, aop, outf);
03322     }
03323   else if (aop == 0 && aopcde == 11)
03324     {
03325       OUTS (outf, dregs (dst0));
03326       OUTS (outf, "=(A0+=A1)");
03327     }
03328   else if (aop == 0 && aopcde == 10)
03329     {
03330       OUTS (outf, dregs_lo (dst0));
03331       OUTS (outf, "=A0.x");
03332     }
03333   else if (aop == 1 && aopcde == 10)
03334     {
03335       OUTS (outf, dregs_lo (dst0));
03336       OUTS (outf, "=A1.x");
03337     }
03338   else if (aop == 1 && aopcde == 0)
03339     {
03340       OUTS (outf, dregs (dst0));
03341       OUTS (outf, "=");
03342       OUTS (outf, dregs (src0));
03343       OUTS (outf, "+|-");
03344       OUTS (outf, dregs (src1));
03345       OUTS (outf, " ");
03346       amod0 (s, x, outf);
03347     }
03348   else if (aop == 3 && aopcde == 0)
03349     {
03350       OUTS (outf, dregs (dst0));
03351       OUTS (outf, "=");
03352       OUTS (outf, dregs (src0));
03353       OUTS (outf, "-|-");
03354       OUTS (outf, dregs (src1));
03355       OUTS (outf, " ");
03356       amod0 (s, x, outf);
03357     }
03358   else if (aop == 1 && aopcde == 4)
03359     {
03360       OUTS (outf, dregs (dst0));
03361       OUTS (outf, "=");
03362       OUTS (outf, dregs (src0));
03363       OUTS (outf, "-");
03364       OUTS (outf, dregs (src1));
03365       OUTS (outf, " ");
03366       amod1 (s, x, outf);
03367     }
03368   else if (aop == 0 && aopcde == 17)
03369     {
03370       OUTS (outf, dregs (dst1));
03371       OUTS (outf, "=A1+A0,");
03372       OUTS (outf, dregs (dst0));
03373       OUTS (outf, "=A1-A0 ");
03374       amod1 (s, x, outf);
03375     }
03376   else if (aop == 1 && aopcde == 17)
03377     {
03378       OUTS (outf, dregs (dst1));
03379       OUTS (outf, "=A0+A1,");
03380       OUTS (outf, dregs (dst0));
03381       OUTS (outf, "=A0-A1 ");
03382       amod1 (s, x, outf);
03383     }
03384   else if (aop == 0 && aopcde == 18)
03385     {
03386       OUTS (outf, "SAA(");
03387       OUTS (outf, dregs (src0 + 1));
03388       OUTS (outf, ":");
03389       OUTS (outf, imm5 (src0));
03390       OUTS (outf, ",");
03391       OUTS (outf, dregs (src1 + 1));
03392       OUTS (outf, ":");
03393       OUTS (outf, imm5 (src1));
03394       OUTS (outf, ") ");
03395       aligndir (s, outf);
03396     }
03397   else if (aop == 3 && aopcde == 18)
03398     OUTS (outf, "DISALGNEXCPT");
03399 
03400   else if (aop == 0 && aopcde == 20)
03401     {
03402       OUTS (outf, dregs (dst0));
03403       OUTS (outf, "=BYTEOP1P(");
03404       OUTS (outf, dregs (src0 + 1));
03405       OUTS (outf, ":");
03406       OUTS (outf, imm5 (src0));
03407       OUTS (outf, ",");
03408       OUTS (outf, dregs (src1 + 1));
03409       OUTS (outf, ":");
03410       OUTS (outf, imm5 (src1));
03411       OUTS (outf, ")");
03412       aligndir (s, outf);
03413     }
03414   else if (aop == 1 && aopcde == 20)
03415     {
03416       OUTS (outf, dregs (dst0));
03417       OUTS (outf, "=BYTEOP1P(");
03418       OUTS (outf, dregs (src0 + 1));
03419       OUTS (outf, ":");
03420       OUTS (outf, imm5 (src0));
03421       OUTS (outf, ",");
03422       OUTS (outf, dregs (src1 + 1));
03423       OUTS (outf, ":");
03424       OUTS (outf, imm5 (src1));
03425       OUTS (outf, ")(T");
03426       if (s == 1)
03427        OUTS (outf, ", R)");
03428       else
03429        OUTS (outf, ")");
03430     }
03431   else if (aop == 0 && aopcde == 21)
03432     {
03433       OUTS (outf, "(");
03434       OUTS (outf, dregs (dst1));
03435       OUTS (outf, ",");
03436       OUTS (outf, dregs (dst0));
03437       OUTS (outf, ")=BYTEOP16P(");
03438       OUTS (outf, dregs (src0 + 1));
03439       OUTS (outf, ":");
03440       OUTS (outf, imm5 (src0));
03441       OUTS (outf, ",");
03442       OUTS (outf, dregs (src1 + 1));
03443       OUTS (outf, ":");
03444       OUTS (outf, imm5 (src1));
03445       OUTS (outf, ") ");
03446       aligndir (s, outf);
03447     }
03448   else if (aop == 1 && aopcde == 21)
03449     {
03450       OUTS (outf, "(");
03451       OUTS (outf, dregs (dst1));
03452       OUTS (outf, ",");
03453       OUTS (outf, dregs (dst0));
03454       OUTS (outf, ")=BYTEOP16M(");
03455       OUTS (outf, dregs (src0 + 1));
03456       OUTS (outf, ":");
03457       OUTS (outf, imm5 (src0));
03458       OUTS (outf, ",");
03459       OUTS (outf, dregs (src1 + 1));
03460       OUTS (outf, ":");
03461       OUTS (outf, imm5 (src1));
03462       OUTS (outf, ") ");
03463       aligndir (s, outf);
03464     }
03465   else if (aop == 2 && aopcde == 7)
03466     {
03467       OUTS (outf, dregs (dst0));
03468       OUTS (outf, "= ABS ");
03469       OUTS (outf, dregs (src0));
03470     }
03471   else if (aop == 1 && aopcde == 7)
03472     {
03473       OUTS (outf, dregs (dst0));
03474       OUTS (outf, "=MIN(");
03475       OUTS (outf, dregs (src0));
03476       OUTS (outf, ",");
03477       OUTS (outf, dregs (src1));
03478       OUTS (outf, ")");
03479     }
03480   else if (aop == 0 && aopcde == 7)
03481     {
03482       OUTS (outf, dregs (dst0));
03483       OUTS (outf, "=MAX(");
03484       OUTS (outf, dregs (src0));
03485       OUTS (outf, ",");
03486       OUTS (outf, dregs (src1));
03487       OUTS (outf, ")");
03488     }
03489   else if (aop == 2 && aopcde == 6)
03490     {
03491       OUTS (outf, dregs (dst0));
03492       OUTS (outf, "= ABS ");
03493       OUTS (outf, dregs (src0));
03494       OUTS (outf, "(V)");
03495     }
03496   else if (aop == 1 && aopcde == 6)
03497     {
03498       OUTS (outf, dregs (dst0));
03499       OUTS (outf, "=MIN(");
03500       OUTS (outf, dregs (src0));
03501       OUTS (outf, ",");
03502       OUTS (outf, dregs (src1));
03503       OUTS (outf, ")(V)");
03504     }
03505   else if (aop == 0 && aopcde == 6)
03506     {
03507       OUTS (outf, dregs (dst0));
03508       OUTS (outf, "=MAX(");
03509       OUTS (outf, dregs (src0));
03510       OUTS (outf, ",");
03511       OUTS (outf, dregs (src1));
03512       OUTS (outf, ")(V)");
03513     }
03514   else if (HL == 1 && aopcde == 1)
03515     {
03516       OUTS (outf, dregs (dst1));
03517       OUTS (outf, "=");
03518       OUTS (outf, dregs (src0));
03519       OUTS (outf, "+|-");
03520       OUTS (outf, dregs (src1));
03521       OUTS (outf, ",");
03522       OUTS (outf, dregs (dst0));
03523       OUTS (outf, "=");
03524       OUTS (outf, dregs (src0));
03525       OUTS (outf, "-|+");
03526       OUTS (outf, dregs (src1));
03527       amod0amod2 (s, x, aop, outf);
03528     }
03529   else if (aop == 0 && aopcde == 4)
03530     {
03531       OUTS (outf, dregs (dst0));
03532       OUTS (outf, "=");
03533       OUTS (outf, dregs (src0));
03534       OUTS (outf, "+");
03535       OUTS (outf, dregs (src1));
03536       OUTS (outf, " ");
03537       amod1 (s, x, outf);
03538     }
03539   else if (aop == 0 && aopcde == 0)
03540     {
03541       OUTS (outf, dregs (dst0));
03542       OUTS (outf, "=");
03543       OUTS (outf, dregs (src0));
03544       OUTS (outf, "+|+");
03545       OUTS (outf, dregs (src1));
03546       OUTS (outf, " ");
03547       amod0 (s, x, outf);
03548     }
03549   else if (aop == 0 && aopcde == 24)
03550     {
03551       OUTS (outf, dregs (dst0));
03552       OUTS (outf, "=BYTEPACK(");
03553       OUTS (outf, dregs (src0));
03554       OUTS (outf, ",");
03555       OUTS (outf, dregs (src1));
03556       OUTS (outf, ")");
03557     }
03558   else if (aop == 1 && aopcde == 24)
03559     {
03560       OUTS (outf, "(");
03561       OUTS (outf, dregs (dst1));
03562       OUTS (outf, ",");
03563       OUTS (outf, dregs (dst0));
03564       OUTS (outf, ") = BYTEUNPACK ");
03565       OUTS (outf, dregs (src0 + 1));
03566       OUTS (outf, ":");
03567       OUTS (outf, imm5 (src0));
03568       OUTS (outf, " ");
03569       aligndir (s, outf);
03570     }
03571   else if (aopcde == 13)
03572     {
03573       OUTS (outf, "(");
03574       OUTS (outf, dregs (dst1));
03575       OUTS (outf, ",");
03576       OUTS (outf, dregs (dst0));
03577       OUTS (outf, ") = SEARCH ");
03578       OUTS (outf, dregs (src0));
03579       OUTS (outf, "(");
03580       searchmod (aop, outf);
03581       OUTS (outf, ")");
03582     }
03583   else
03584     return 0;
03585 
03586   return 4;
03587 }
03588 
03589 static int
03590 decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf)
03591 {
03592   /* dsp32shift
03593      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
03594      | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 0 | - | - |.sopcde............|
03595      |.sop...|.HLs...|.dst0......| - | - | - |.src0......|.src1......|
03596      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
03597   int HLs  = ((iw1 >> DSP32Shift_HLs_bits) & DSP32Shift_HLs_mask);
03598   int sop  = ((iw1 >> DSP32Shift_sop_bits) & DSP32Shift_sop_mask);
03599   int src0 = ((iw1 >> DSP32Shift_src0_bits) & DSP32Shift_src0_mask);
03600   int src1 = ((iw1 >> DSP32Shift_src1_bits) & DSP32Shift_src1_mask);
03601   int dst0 = ((iw1 >> DSP32Shift_dst0_bits) & DSP32Shift_dst0_mask);
03602   int sopcde = ((iw0 >> (DSP32Shift_sopcde_bits - 16)) & DSP32Shift_sopcde_mask);
03603   const char *acc01 = (HLs & 1) == 0 ? "A0" : "A1";
03604 
03605   if (HLs == 0 && sop == 0 && sopcde == 0)
03606     {
03607       OUTS (outf, dregs_lo (dst0));
03608       OUTS (outf, "= ASHIFT ");
03609       OUTS (outf, dregs_lo (src1));
03610       OUTS (outf, " BY ");
03611       OUTS (outf, dregs_lo (src0));
03612     }
03613   else if (HLs == 1 && sop == 0 && sopcde == 0)
03614     {
03615       OUTS (outf, dregs_lo (dst0));
03616       OUTS (outf, "= ASHIFT ");
03617       OUTS (outf, dregs_hi (src1));
03618       OUTS (outf, " BY ");
03619       OUTS (outf, dregs_lo (src0));
03620     }
03621   else if (HLs == 2 && sop == 0 && sopcde == 0)
03622     {
03623       OUTS (outf, dregs_hi (dst0));
03624       OUTS (outf, "= ASHIFT ");
03625       OUTS (outf, dregs_lo (src1));
03626       OUTS (outf, " BY ");
03627       OUTS (outf, dregs_lo (src0));
03628     }
03629   else if (HLs == 3 && sop == 0 && sopcde == 0)
03630     {
03631       OUTS (outf, dregs_hi (dst0));
03632       OUTS (outf, "= ASHIFT ");
03633       OUTS (outf, dregs_hi (src1));
03634       OUTS (outf, " BY ");
03635       OUTS (outf, dregs_lo (src0));
03636     }
03637   else if (HLs == 0 && sop == 1 && sopcde == 0)
03638     {
03639       OUTS (outf, dregs_lo (dst0));
03640       OUTS (outf, "= ASHIFT ");
03641       OUTS (outf, dregs_lo (src1));
03642       OUTS (outf, " BY ");
03643       OUTS (outf, dregs_lo (src0));
03644       OUTS (outf, "(S)");
03645     }
03646   else if (HLs == 1 && sop == 1 && sopcde == 0)
03647     {
03648       OUTS (outf, dregs_lo (dst0));
03649       OUTS (outf, "= ASHIFT ");
03650       OUTS (outf, dregs_hi (src1));
03651       OUTS (outf, " BY ");
03652       OUTS (outf, dregs_lo (src0));
03653       OUTS (outf, "(S)");
03654     }
03655   else if (HLs == 2 && sop == 1 && sopcde == 0)
03656     {
03657       OUTS (outf, dregs_hi (dst0));
03658       OUTS (outf, "= ASHIFT ");
03659       OUTS (outf, dregs_lo (src1));
03660       OUTS (outf, " BY ");
03661       OUTS (outf, dregs_lo (src0));
03662       OUTS (outf, "(S)");
03663     }
03664   else if (HLs == 3 && sop == 1 && sopcde == 0)
03665     {
03666       OUTS (outf, dregs_hi (dst0));
03667       OUTS (outf, "= ASHIFT ");
03668       OUTS (outf, dregs_hi (src1));
03669       OUTS (outf, " BY ");
03670       OUTS (outf, dregs_lo (src0));
03671       OUTS (outf, "(S)");
03672     }
03673   else if (sop == 2 && sopcde == 0)
03674     {
03675       OUTS (outf, (HLs & 2) == 0 ? dregs_lo (dst0) : dregs_hi (dst0));
03676       OUTS (outf, "= LSHIFT ");
03677       OUTS (outf, (HLs & 1) == 0 ? dregs_lo (src1) : dregs_hi (src1));
03678       OUTS (outf, " BY ");
03679       OUTS (outf, dregs_lo (src0));
03680     }
03681   else if (sop == 0 && sopcde == 3)
03682     {
03683       OUTS (outf, acc01);
03684       OUTS (outf, "= ASHIFT ");
03685       OUTS (outf, acc01);
03686       OUTS (outf, " BY ");
03687       OUTS (outf, dregs_lo (src0));
03688     }
03689   else if (sop == 1 && sopcde == 3)
03690     {
03691       OUTS (outf, acc01);
03692       OUTS (outf, "= LSHIFT ");
03693       OUTS (outf, acc01);
03694       OUTS (outf, " BY ");
03695       OUTS (outf, dregs_lo (src0));
03696     }
03697   else if (sop == 2 && sopcde == 3)
03698     {
03699       OUTS (outf, acc01);
03700       OUTS (outf, "= ROT ");
03701       OUTS (outf, acc01);
03702       OUTS (outf, " BY ");
03703       OUTS (outf, dregs_lo (src0));
03704     }
03705   else if (sop == 3 && sopcde == 3)
03706     {
03707       OUTS (outf, dregs (dst0));
03708       OUTS (outf, "= ROT ");
03709       OUTS (outf, dregs (src1));
03710       OUTS (outf, " BY ");
03711       OUTS (outf, dregs_lo (src0));
03712     }
03713   else if (sop == 1 && sopcde == 1)
03714     {
03715       OUTS (outf, dregs (dst0));
03716       OUTS (outf, "= ASHIFT ");
03717       OUTS (outf, dregs (src1));
03718       OUTS (outf, " BY ");
03719       OUTS (outf, dregs_lo (src0));
03720       OUTS (outf, "(V,S)");
03721     }
03722   else if (sop == 0 && sopcde == 1)
03723     {
03724       OUTS (outf, dregs (dst0));
03725       OUTS (outf, "= ASHIFT ");
03726       OUTS (outf, dregs (src1));
03727       OUTS (outf, " BY ");
03728       OUTS (outf, dregs_lo (src0));
03729       OUTS (outf, "(V)");
03730     }
03731   else if (sop == 0 && sopcde == 2)
03732     {
03733       OUTS (outf, dregs (dst0));
03734       OUTS (outf, "= ASHIFT ");
03735       OUTS (outf, dregs (src1));
03736       OUTS (outf, " BY ");
03737       OUTS (outf, dregs_lo (src0));
03738     }
03739   else if (sop == 1 && sopcde == 2)
03740     {
03741       OUTS (outf, dregs (dst0));
03742       OUTS (outf, "= ASHIFT ");
03743       OUTS (outf, dregs (src1));
03744       OUTS (outf, " BY ");
03745       OUTS (outf, dregs_lo (src0));
03746       OUTS (outf, "(S)");
03747     }
03748   else if (sop == 2 && sopcde == 2)
03749     {
03750       OUTS (outf, dregs (dst0));
03751       OUTS (outf, "=SHIFT ");
03752       OUTS (outf, dregs (src1));
03753       OUTS (outf, " BY ");
03754       OUTS (outf, dregs_lo (src0));
03755     }
03756   else if (sop == 3 && sopcde == 2)
03757     {
03758       OUTS (outf, dregs (dst0));
03759       OUTS (outf, "= ROT ");
03760       OUTS (outf, dregs (src1));
03761       OUTS (outf, " BY ");
03762       OUTS (outf, dregs_lo (src0));
03763     }
03764   else if (sop == 2 && sopcde == 1)
03765     {
03766       OUTS (outf, dregs (dst0));
03767       OUTS (outf, "=SHIFT ");
03768       OUTS (outf, dregs (src1));
03769       OUTS (outf, " BY ");
03770       OUTS (outf, dregs_lo (src0));
03771       OUTS (outf, "(V)");
03772     }
03773   else if (sop == 0 && sopcde == 4)
03774     {
03775       OUTS (outf, dregs (dst0));
03776       OUTS (outf, "=PACK");
03777       OUTS (outf, "(");
03778       OUTS (outf, dregs_lo (src1));
03779       OUTS (outf, ",");
03780       OUTS (outf, dregs_lo (src0));
03781       OUTS (outf, ")");
03782     }
03783   else if (sop == 1 && sopcde == 4)
03784     {
03785       OUTS (outf, dregs (dst0));
03786       OUTS (outf, "=PACK(");
03787       OUTS (outf, dregs_lo (src1));
03788       OUTS (outf, ",");
03789       OUTS (outf, dregs_hi (src0));
03790       OUTS (outf, ")");
03791     }
03792   else if (sop == 2 && sopcde == 4)
03793     {
03794       OUTS (outf, dregs (dst0));
03795       OUTS (outf, "=PACK(");
03796       OUTS (outf, dregs_hi (src1));
03797       OUTS (outf, ",");
03798       OUTS (outf, dregs_lo (src0));
03799       OUTS (outf, ")");
03800     }
03801   else if (sop == 3 && sopcde == 4)
03802     {
03803       OUTS (outf, dregs (dst0));
03804       OUTS (outf, "=PACK(");
03805       OUTS (outf, dregs_hi (src1));
03806       OUTS (outf, ",");
03807       OUTS (outf, dregs_hi (src0));
03808       OUTS (outf, ")");
03809     }
03810   else if (sop == 0 && sopcde == 5)
03811     {
03812       OUTS (outf, dregs_lo (dst0));
03813       OUTS (outf, "=SIGNBITS ");
03814       OUTS (outf, dregs (src1));
03815     }
03816   else if (sop == 1 && sopcde == 5)
03817     {
03818       OUTS (outf, dregs_lo (dst0));
03819       OUTS (outf, "=SIGNBITS ");
03820       OUTS (outf, dregs_lo (src1));
03821     }
03822   else if (sop == 2 && sopcde == 5)
03823     {
03824       OUTS (outf, dregs_lo (dst0));
03825       OUTS (outf, "=SIGNBITS ");
03826       OUTS (outf, dregs_hi (src1));
03827     }
03828   else if (sop == 0 && sopcde == 6)
03829     {
03830       OUTS (outf, dregs_lo (dst0));
03831       OUTS (outf, "=SIGNBITS A0");
03832     }
03833   else if (sop == 1 && sopcde == 6)
03834     {
03835       OUTS (outf, dregs_lo (dst0));
03836       OUTS (outf, "=SIGNBITS A1");
03837     }
03838   else if (sop == 3 && sopcde == 6)
03839     {
03840       OUTS (outf, dregs_lo (dst0));
03841       OUTS (outf, "=ONES ");
03842       OUTS (outf, dregs (src1));
03843     }
03844   else if (sop == 0 && sopcde == 7)
03845     {
03846       OUTS (outf, dregs_lo (dst0));
03847       OUTS (outf, "=EXPADJ (");
03848       OUTS (outf, dregs (src1));
03849       OUTS (outf, ",");
03850       OUTS (outf, dregs_lo (src0));
03851       OUTS (outf, ")");
03852     }
03853   else if (sop == 1 && sopcde == 7)
03854     {
03855       OUTS (outf, dregs_lo (dst0));
03856       OUTS (outf, "=EXPADJ (");
03857       OUTS (outf, dregs (src1));
03858       OUTS (outf, ",");
03859       OUTS (outf, dregs_lo (src0));
03860       OUTS (outf, ") (V)");
03861     }
03862   else if (sop == 2 && sopcde == 7)
03863     {
03864       OUTS (outf, dregs_lo (dst0));
03865       OUTS (outf, "=EXPADJ (");
03866       OUTS (outf, dregs_lo (src1));
03867       OUTS (outf, ",");
03868       OUTS (outf, dregs_lo (src0));
03869       OUTS (outf, ")");
03870     }
03871   else if (sop == 3 && sopcde == 7)
03872     {
03873       OUTS (outf, dregs_lo (dst0));
03874       OUTS (outf, "=EXPADJ (");
03875       OUTS (outf, dregs_hi (src1));
03876       OUTS (outf, ",");
03877       OUTS (outf, dregs_lo (src0));
03878       OUTS (outf, ")");
03879     }
03880   else if (sop == 0 && sopcde == 8)
03881     {
03882       OUTS (outf, "BITMUX (");
03883       OUTS (outf, dregs (src0));
03884       OUTS (outf, ",");
03885       OUTS (outf, dregs (src1));
03886       OUTS (outf, ",A0 )(ASR)");
03887     }
03888   else if (sop == 1 && sopcde == 8)
03889     {
03890       OUTS (outf, "BITMUX (");
03891       OUTS (outf, dregs (src0));
03892       OUTS (outf, ",");
03893       OUTS (outf, dregs (src1));
03894       OUTS (outf, ",A0 )(ASL)");
03895     }
03896   else if (sop == 0 && sopcde == 9)
03897     {
03898       OUTS (outf, dregs_lo (dst0));
03899       OUTS (outf, "=VIT_MAX (");
03900       OUTS (outf, dregs (src1));
03901       OUTS (outf, ") (ASL)");
03902     }
03903   else if (sop == 1 && sopcde == 9)
03904     {
03905       OUTS (outf, dregs_lo (dst0));
03906       OUTS (outf, "=VIT_MAX (");
03907       OUTS (outf, dregs (src1));
03908       OUTS (outf, ") (ASR)");
03909     }
03910   else if (sop == 2 && sopcde == 9)
03911     {
03912       OUTS (outf, dregs (dst0));
03913       OUTS (outf, "=VIT_MAX(");
03914       OUTS (outf, dregs (src1));
03915       OUTS (outf, ",");
03916       OUTS (outf, dregs (src0));
03917       OUTS (outf, ")(ASL)");
03918     }
03919   else if (sop == 3 && sopcde == 9)
03920     {
03921       OUTS (outf, dregs (dst0));
03922       OUTS (outf, "=VIT_MAX(");
03923       OUTS (outf, dregs (src1));
03924       OUTS (outf, ",");
03925       OUTS (outf, dregs (src0));
03926       OUTS (outf, ")(ASR)");
03927     }
03928   else if (sop == 0 && sopcde == 10)
03929     {
03930       OUTS (outf, dregs (dst0));
03931       OUTS (outf, "=EXTRACT(");
03932       OUTS (outf, dregs (src1));
03933       OUTS (outf, ",");
03934       OUTS (outf, dregs_lo (src0));
03935       OUTS (outf, ") (Z)");
03936     }
03937   else if (sop == 1 && sopcde == 10)
03938     {
03939       OUTS (outf, dregs (dst0));
03940       OUTS (outf, "=EXTRACT(");
03941       OUTS (outf, dregs (src1));
03942       OUTS (outf, ",");
03943       OUTS (outf, dregs_lo (src0));
03944       OUTS (outf, ")(X)");
03945     }
03946   else if (sop == 2 && sopcde == 10)
03947     {
03948       OUTS (outf, dregs (dst0));
03949       OUTS (outf, "=DEPOSIT(");
03950       OUTS (outf, dregs (src1));
03951       OUTS (outf, ",");
03952       OUTS (outf, dregs (src0));
03953       OUTS (outf, ")");
03954     }
03955   else if (sop == 3 && sopcde == 10)
03956     {
03957       OUTS (outf, dregs (dst0));
03958       OUTS (outf, "=DEPOSIT(");
03959       OUTS (outf, dregs (src1));
03960       OUTS (outf, ",");
03961       OUTS (outf, dregs (src0));
03962       OUTS (outf, ")(X)");
03963     }
03964   else if (sop == 0 && sopcde == 11)
03965     {
03966       OUTS (outf, dregs_lo (dst0));
03967       OUTS (outf, "=CC=BXORSHIFT(A0,");
03968       OUTS (outf, dregs (src0));
03969       OUTS (outf, ")");
03970     }
03971   else if (sop == 1 && sopcde == 11)
03972     {
03973       OUTS (outf, dregs_lo (dst0));
03974       OUTS (outf, "=CC=BXOR(A0,");
03975       OUTS (outf, dregs (src0));
03976       OUTS (outf, ")");
03977     }
03978   else if (sop == 0 && sopcde == 12)
03979     OUTS (outf, "A0=BXORSHIFT(A0,A1 ,CC)");
03980 
03981   else if (sop == 1 && sopcde == 12)
03982     {
03983       OUTS (outf, dregs_lo (dst0));
03984       OUTS (outf, "=CC=BXOR( A0,A1 ,CC )");
03985     }
03986   else if (sop == 0 && sopcde == 13)
03987     {
03988       OUTS (outf, dregs (dst0));
03989       OUTS (outf, "=ALIGN8(");
03990       OUTS (outf, dregs (src1));
03991       OUTS (outf, ",");
03992       OUTS (outf, dregs (src0));
03993       OUTS (outf, ")");
03994     }
03995   else if (sop == 1 && sopcde == 13)
03996     {
03997       OUTS (outf, dregs (dst0));
03998       OUTS (outf, "=ALIGN16(");
03999       OUTS (outf, dregs (src1));
04000       OUTS (outf, ",");
04001       OUTS (outf, dregs (src0));
04002       OUTS (outf, ")");
04003     }
04004   else if (sop == 2 && sopcde == 13)
04005     {
04006       OUTS (outf, dregs (dst0));
04007       OUTS (outf, "=ALIGN24(");
04008       OUTS (outf, dregs (src1));
04009       OUTS (outf, ",");
04010       OUTS (outf, dregs (src0));
04011       OUTS (outf, ")");
04012     }
04013   else
04014     return 0;
04015 
04016   return 4;
04017 }
04018 
04019 static int
04020 decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
04021 {
04022   /* dsp32shiftimm
04023      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
04024      | 1 | 1 | 0 | 0 |.M.| 1 | 1 | 0 | 1 | - | - |.sopcde............|
04025      |.sop...|.HLs...|.dst0......|.immag.................|.src1......|
04026      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
04027   int src1     = ((iw1 >> DSP32ShiftImm_src1_bits) & DSP32ShiftImm_src1_mask);
04028   int sop      = ((iw1 >> DSP32ShiftImm_sop_bits) & DSP32ShiftImm_sop_mask);
04029   int bit8     = ((iw1 >> 8) & 0x1);
04030   int immag    = ((iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
04031   int newimmag = (-(iw1 >> DSP32ShiftImm_immag_bits) & DSP32ShiftImm_immag_mask);
04032   int dst0     = ((iw1 >> DSP32ShiftImm_dst0_bits) & DSP32ShiftImm_dst0_mask);
04033   int sopcde   = ((iw0 >> (DSP32ShiftImm_sopcde_bits - 16)) & DSP32ShiftImm_sopcde_mask);
04034   int HLs      = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
04035 
04036 
04037   if (sop == 0 && sopcde == 0)
04038     {
04039       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
04040       OUTS (outf, " = ");
04041       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
04042       OUTS (outf, " >>> ");
04043       OUTS (outf, uimm4 (newimmag));
04044     }
04045   else if (sop == 1 && sopcde == 0 && bit8 == 0)
04046     {
04047       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
04048       OUTS (outf, " = ");
04049       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
04050       OUTS (outf, " << ");
04051       OUTS (outf, uimm4 (immag));
04052       OUTS (outf, " (S)");
04053     }
04054   else if (sop == 1 && sopcde == 0 && bit8 == 1)
04055     {
04056       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
04057       OUTS (outf, " = ");
04058       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
04059       OUTS (outf, " >>> ");
04060       OUTS (outf, uimm4 (newimmag));
04061       OUTS (outf, " (S)");
04062     }
04063   else if (sop == 2 && sopcde == 0 && bit8 == 0)
04064     {
04065       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
04066       OUTS (outf, " = ");
04067       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
04068       OUTS (outf, " << ");
04069       OUTS (outf, uimm4 (immag));
04070     }
04071   else if (sop == 2 && sopcde == 0 && bit8 == 1)
04072     {
04073       OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
04074       OUTS (outf, " = ");
04075       OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
04076       OUTS (outf, " >> ");
04077       OUTS (outf, uimm4 (newimmag));
04078     }
04079   else if (sop == 2 && sopcde == 3 && HLs == 1)
04080     {
04081       OUTS (outf, "A1= ROT A1 BY ");
04082       OUTS (outf, imm6 (immag));
04083     }
04084   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 0)
04085     {
04086       OUTS (outf, "A0=A0<<");
04087       OUTS (outf, uimm5 (immag));
04088     }
04089   else if (sop == 0 && sopcde == 3 && HLs == 0 && bit8 == 1)
04090     {
04091       OUTS (outf, "A0=A0>>>");
04092       OUTS (outf, uimm5 (newimmag));
04093     }
04094   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 0)
04095     {
04096       OUTS (outf, "A1=A1<<");
04097       OUTS (outf, uimm5 (immag));
04098     }
04099   else if (sop == 0 && sopcde == 3 && HLs == 1 && bit8 == 1)
04100     {
04101       OUTS (outf, "A1=A1>>>");
04102       OUTS (outf, uimm5 (newimmag));
04103     }
04104   else if (sop == 1 && sopcde == 3 && HLs == 0)
04105     {
04106       OUTS (outf, "A0=A0>>");
04107       OUTS (outf, uimm5 (newimmag));
04108     }
04109   else if (sop == 1 && sopcde == 3 && HLs == 1)
04110     {
04111       OUTS (outf, "A1=A1>>");
04112       OUTS (outf, uimm5 (newimmag));
04113     }
04114   else if (sop == 2 && sopcde == 3 && HLs == 0)
04115     {
04116       OUTS (outf, "A0= ROT A0 BY ");
04117       OUTS (outf, imm6 (immag));
04118     }
04119   else if (sop == 1 && sopcde == 1 && bit8 == 0)
04120     {
04121       OUTS (outf, dregs (dst0));
04122       OUTS (outf, "=");
04123       OUTS (outf, dregs (src1));
04124       OUTS (outf, "<<");
04125       OUTS (outf, uimm5 (immag));
04126       OUTS (outf, " (V, S)");
04127     }
04128   else if (sop == 1 && sopcde == 1 && bit8 == 1)
04129     {
04130       OUTS (outf, dregs (dst0));
04131       OUTS (outf, "=");
04132       OUTS (outf, dregs (src1));
04133       OUTS (outf, ">>>");
04134       OUTS (outf, imm5 (-immag));
04135       OUTS (outf, " (V)");
04136     }
04137   else if (sop == 2 && sopcde == 1 && bit8 == 1)
04138     {
04139       OUTS (outf, dregs (dst0));
04140       OUTS (outf, "=");
04141       OUTS (outf, dregs (src1));
04142       OUTS (outf, " >> ");
04143       OUTS (outf, uimm5 (newimmag));
04144       OUTS (outf, " (V)");
04145     }
04146   else if (sop == 2 && sopcde == 1 && bit8 == 0)
04147     {
04148       OUTS (outf, dregs (dst0));
04149       OUTS (outf, "=");
04150       OUTS (outf, dregs (src1));
04151       OUTS (outf, "<<");
04152       OUTS (outf, imm5 (immag));
04153       OUTS (outf, " (V)");
04154     }
04155   else if (sop == 0 && sopcde == 1)
04156     {
04157       OUTS (outf, dregs (dst0));
04158       OUTS (outf, "=");
04159       OUTS (outf, dregs (src1));
04160       OUTS (outf, ">>>");
04161       OUTS (outf, uimm5 (newimmag));
04162       OUTS (outf, " (V)");
04163     }
04164   else if (sop == 1 && sopcde == 2)
04165     {
04166       OUTS (outf, dregs (dst0));
04167       OUTS (outf, "=");
04168       OUTS (outf, dregs (src1));
04169       OUTS (outf, "<<");
04170       OUTS (outf, uimm5 (immag));
04171       OUTS (outf, "(S)");
04172     }
04173   else if (sop == 2 && sopcde == 2 && bit8 == 1)
04174     {
04175       OUTS (outf, dregs (dst0));
04176       OUTS (outf, "=");
04177       OUTS (outf, dregs (src1));
04178       OUTS (outf, ">>");
04179       OUTS (outf, uimm5 (newimmag));
04180     }
04181   else if (sop == 2 && sopcde == 2 && bit8 == 0)
04182     {
04183       OUTS (outf, dregs (dst0));
04184       OUTS (outf, "=");
04185       OUTS (outf, dregs (src1));
04186       OUTS (outf, "<<");
04187       OUTS (outf, uimm5 (immag));
04188     }
04189   else if (sop == 3 && sopcde == 2)
04190     {
04191       OUTS (outf, dregs (dst0));
04192       OUTS (outf, "= ROT ");
04193       OUTS (outf, dregs (src1));
04194       OUTS (outf, " BY ");
04195       OUTS (outf, imm6 (immag));
04196     }
04197   else if (sop == 0 && sopcde == 2)
04198     {
04199       OUTS (outf, dregs (dst0));
04200       OUTS (outf, "=");
04201       OUTS (outf, dregs (src1));
04202       OUTS (outf, ">>>");
04203       OUTS (outf, uimm5 (newimmag));
04204     }
04205   else
04206     return 0;
04207 
04208   return 4;
04209 }
04210 
04211 static int
04212 decode_pseudoDEBUG_0 (TIword iw0, disassemble_info *outf)
04213 {
04214   /* pseudoDEBUG
04215      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
04216      | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 |.fn....|.grp.......|.reg.......|
04217      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
04218   int fn  = ((iw0 >> PseudoDbg_fn_bits) & PseudoDbg_fn_mask);
04219   int grp = ((iw0 >> PseudoDbg_grp_bits) & PseudoDbg_grp_mask);
04220   int reg = ((iw0 >> PseudoDbg_reg_bits) & PseudoDbg_reg_mask);
04221 
04222   if (reg == 0 && fn == 3)
04223     OUTS (outf, "DBG A0");
04224 
04225   else if (reg == 1 && fn == 3)
04226     OUTS (outf, "DBG A1");
04227 
04228   else if (reg == 3 && fn == 3)
04229     OUTS (outf, "ABORT");
04230 
04231   else if (reg == 4 && fn == 3)
04232     OUTS (outf, "HLT");
04233 
04234   else if (reg == 5 && fn == 3)
04235     OUTS (outf, "DBGHALT");
04236 
04237   else if (reg == 6 && fn == 3)
04238     {
04239       OUTS (outf, "DBGCMPLX(");
04240       OUTS (outf, dregs (grp));
04241       OUTS (outf, ")");
04242     }
04243   else if (reg == 7 && fn == 3)
04244     OUTS (outf, "DBG");
04245 
04246   else if (grp == 0 && fn == 2)
04247     {
04248       OUTS (outf, "OUTC");
04249       OUTS (outf, dregs (reg));
04250     }
04251   else if (fn == 0)
04252     {
04253       OUTS (outf, "DBG");
04254       OUTS (outf, allregs (reg, grp));
04255     }
04256   else if (fn == 1)
04257     {
04258       OUTS (outf, "PRNT");
04259       OUTS (outf, allregs (reg, grp));
04260     }
04261   else
04262     return 0;
04263 
04264   return 2;
04265 }
04266 
04267 static int
04268 decode_pseudodbg_assert_0 (TIword iw0, TIword iw1, disassemble_info *outf)
04269 {
04270   /* pseudodbg_assert
04271      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+
04272      | 1 | 1 | 1 | 1 | 0 | - | - | - | - | - |.dbgop.....|.regtest...|
04273      |.expected......................................................|
04274      +---+---+---+---|---+---+---+---|---+---+---+---|---+---+---+---+  */
04275   int expected = ((iw1 >> PseudoDbg_Assert_expected_bits) & PseudoDbg_Assert_expected_mask);
04276   int dbgop    = ((iw0 >> (PseudoDbg_Assert_dbgop_bits - 16)) & PseudoDbg_Assert_dbgop_mask);
04277   int regtest  = ((iw0 >> (PseudoDbg_Assert_regtest_bits - 16)) & PseudoDbg_Assert_regtest_mask);
04278 
04279   if (dbgop == 0)
04280     {
04281       OUTS (outf, "DBGA(");
04282       OUTS (outf, dregs_lo (regtest));
04283       OUTS (outf, ",");
04284       OUTS (outf, uimm16 (expected));
04285       OUTS (outf, ")");
04286     }
04287   else if (dbgop == 1)
04288     {
04289       OUTS (outf, "DBGA(");
04290       OUTS (outf, dregs_hi (regtest));
04291       OUTS (outf, ",");
04292       OUTS (outf, uimm16 (expected));
04293       OUTS (outf, ")");
04294     }
04295   else if (dbgop == 2)
04296     {
04297       OUTS (outf, "DBGAL(");
04298       OUTS (outf, dregs (regtest));
04299       OUTS (outf, ",");
04300       OUTS (outf, uimm16 (expected));
04301       OUTS (outf, ")");
04302     }
04303   else if (dbgop == 3)
04304     {
04305       OUTS (outf, "DBGAH(");
04306       OUTS (outf, dregs (regtest));
04307       OUTS (outf, ",");
04308       OUTS (outf, uimm16 (expected));
04309       OUTS (outf, ")");
04310     }
04311   else
04312     return 0;
04313   return 4;
04314 }
04315 
04316 int
04317 _print_insn_bfin (bfd_vma pc, disassemble_info *outf)
04318 {
04319   bfd_byte buf[4];
04320   TIword iw0;
04321   TIword iw1;
04322   int status;
04323   int rv = 0;
04324 
04325   status = (*outf->read_memory_func) (pc & ~0x1, buf, 2, outf);
04326   status = (*outf->read_memory_func) ((pc + 2) & ~0x1, buf + 2, 2, outf);
04327 
04328   iw0 = bfd_getl16 (buf);
04329   iw1 = bfd_getl16 (buf + 2);
04330 
04331   if ((iw0 & 0xf7ff) == 0xc003 && iw1 == 0x1800)
04332     {
04333       OUTS (outf, "mnop");
04334       return 4;
04335     }
04336   else if ((iw0 & 0xff00) == 0x0000)
04337     rv = decode_ProgCtrl_0 (iw0, outf);
04338   else if ((iw0 & 0xffc0) == 0x0240)
04339     rv = decode_CaCTRL_0 (iw0, outf);
04340   else if ((iw0 & 0xff80) == 0x0100)
04341     rv = decode_PushPopReg_0 (iw0, outf);
04342   else if ((iw0 & 0xfe00) == 0x0400)
04343     rv = decode_PushPopMultiple_0 (iw0, outf);
04344   else if ((iw0 & 0xfe00) == 0x0600)
04345     rv = decode_ccMV_0 (iw0, outf);
04346   else if ((iw0 & 0xf800) == 0x0800)
04347     rv = decode_CCflag_0 (iw0, outf);
04348   else if ((iw0 & 0xffe0) == 0x0200)
04349     rv = decode_CC2dreg_0 (iw0, outf);
04350   else if ((iw0 & 0xff00) == 0x0300)
04351     rv = decode_CC2stat_0 (iw0, outf);
04352   else if ((iw0 & 0xf000) == 0x1000)
04353     rv = decode_BRCC_0 (iw0, pc, outf);
04354   else if ((iw0 & 0xf000) == 0x2000)
04355     rv = decode_UJUMP_0 (iw0, pc, outf);
04356   else if ((iw0 & 0xf000) == 0x3000)
04357     rv = decode_REGMV_0 (iw0, outf);
04358   else if ((iw0 & 0xfc00) == 0x4000)
04359     rv = decode_ALU2op_0 (iw0, outf);
04360   else if ((iw0 & 0xfe00) == 0x4400)
04361     rv = decode_PTR2op_0 (iw0, outf);
04362   else if ((iw0 & 0xf800) == 0x4800)
04363     rv = decode_LOGI2op_0 (iw0, outf);
04364   else if ((iw0 & 0xf000) == 0x5000)
04365     rv = decode_COMP3op_0 (iw0, outf);
04366   else if ((iw0 & 0xf800) == 0x6000)
04367     rv = decode_COMPI2opD_0 (iw0, outf);
04368   else if ((iw0 & 0xf800) == 0x6800)
04369     rv = decode_COMPI2opP_0 (iw0, outf);
04370   else if ((iw0 & 0xf000) == 0x8000)
04371     rv = decode_LDSTpmod_0 (iw0, outf);
04372   else if ((iw0 & 0xff60) == 0x9e60)
04373     rv = decode_dagMODim_0 (iw0, outf);
04374   else if ((iw0 & 0xfff0) == 0x9f60)
04375     rv = decode_dagMODik_0 (iw0, outf);
04376   else if ((iw0 & 0xfc00) == 0x9c00)
04377     rv = decode_dspLDST_0 (iw0, outf);
04378   else if ((iw0 & 0xf000) == 0x9000)
04379     rv = decode_LDST_0 (iw0, outf);
04380   else if ((iw0 & 0xfc00) == 0xb800)
04381     rv = decode_LDSTiiFP_0 (iw0, outf);
04382   else if ((iw0 & 0xe000) == 0xA000)
04383     rv = decode_LDSTii_0 (iw0, outf);
04384   else if ((iw0 & 0xff80) == 0xe080 && (iw1 & 0x0C00) == 0x0000)
04385     rv = decode_LoopSetup_0 (iw0, iw1, pc, outf);
04386   else if ((iw0 & 0xff00) == 0xe100 && (iw1 & 0x0000) == 0x0000)
04387     rv = decode_LDIMMhalf_0 (iw0, iw1, outf);
04388   else if ((iw0 & 0xfe00) == 0xe200 && (iw1 & 0x0000) == 0x0000)
04389     rv = decode_CALLa_0 (iw0, iw1, pc, outf);
04390   else if ((iw0 & 0xfc00) == 0xe400 && (iw1 & 0x0000) == 0x0000)
04391     rv = decode_LDSTidxI_0 (iw0, iw1, outf);
04392   else if ((iw0 & 0xfffe) == 0xe800 && (iw1 & 0x0000) == 0x0000)
04393     rv = decode_linkage_0 (iw0, iw1, outf);
04394   else if ((iw0 & 0xf600) == 0xc000 && (iw1 & 0x0000) == 0x0000)
04395     rv = decode_dsp32mac_0 (iw0, iw1, outf);
04396   else if ((iw0 & 0xf600) == 0xc200 && (iw1 & 0x0000) == 0x0000)
04397     rv = decode_dsp32mult_0 (iw0, iw1, outf);
04398   else if ((iw0 & 0xf7c0) == 0xc400 && (iw1 & 0x0000) == 0x0000)
04399     rv = decode_dsp32alu_0 (iw0, iw1, outf);
04400   else if ((iw0 & 0xf780) == 0xc600 && (iw1 & 0x01c0) == 0x0000)
04401     rv = decode_dsp32shift_0 (iw0, iw1, outf);
04402   else if ((iw0 & 0xf780) == 0xc680 && (iw1 & 0x0000) == 0x0000)
04403     rv = decode_dsp32shiftimm_0 (iw0, iw1, outf);
04404   else if ((iw0 & 0xff00) == 0xf800)
04405     rv = decode_pseudoDEBUG_0 (iw0, outf);
04406 #if 0
04407   else if ((iw0 & 0xFF00) == 0xF900)
04408     rv = decode_pseudoOChar_0 (iw0, iw1, pc, outf);
04409 #endif
04410   else if ((iw0 & 0xFFC0) == 0xf000 && (iw1 & 0x0000) == 0x0000)
04411     rv = decode_pseudodbg_assert_0 (iw0, iw1, outf);
04412 
04413   return rv;
04414 }
04415 
04416 
04417 int
04418 print_insn_bfin (bfd_vma pc, disassemble_info *outf)
04419 {
04420   bfd_byte buf[2];
04421   unsigned short iw0;
04422   int status;
04423   int count = 0;
04424 
04425   status = (*outf->read_memory_func) (pc & ~0x01, buf, 2, outf);
04426   iw0 = bfd_getl16 (buf);
04427 
04428   count += _print_insn_bfin (pc, outf);
04429 
04430   /* Proper display of multiple issue instructions.  */
04431 
04432   if ((iw0 & 0xc000) == 0xc000 && (iw0 & BIT_MULTI_INS)
04433       && ((iw0 & 0xe800) != 0xe800 /* Not Linkage.  */ ))
04434     {
04435       outf->fprintf_func (outf->stream, " || ");
04436       count += _print_insn_bfin (pc + 4, outf);
04437       outf->fprintf_func (outf->stream, " || ");
04438       count += _print_insn_bfin (pc + 6, outf);
04439     }
04440   if (count == 0)
04441     {
04442       outf->fprintf_func (outf->stream, "ILLEGAL");
04443       return 2;
04444     }
04445   outf->fprintf_func (outf->stream, ";");
04446   return count;
04447 }