Back to index

cell-binutils  2.17cvs20070401
Defines | Functions
bfin-aux.h File Reference
#include "bfin-defs.h"
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Defines

#define REG_T   Register *

Functions

INSTR_T bfin_gen_dsp32mac (int op1, int mm, int mmod, int w1, int p, int h01, int h11, int h00, int h10, int op0, REG_T dst, REG_T src0, REG_T src1, int w0)
INSTR_T bfin_gen_dsp32mult (int op1, int mm, int mmod, int w1, int p, int h01, int h11, int h00, int h10, int op0, REG_T dst, REG_T src0, REG_T src1, int w0)
INSTR_T bfin_gen_dsp32alu (int HL, int aopcde, int aop, int s, int x, REG_T dst0, REG_T dst1, REG_T src0, REG_T src1)
INSTR_T bfin_gen_dsp32shift (int sopcde, REG_T dst0, REG_T src0, REG_T src1, int sop, int hls)
INSTR_T bfin_gen_dsp32shiftimm (int sopcde, REG_T dst0, int immag, REG_T src1, int sop, int hls)
INSTR_T bfin_gen_ldimmhalf (REG_T reg, int h, int s, int z, Expr_Node *hword, int reloc)
INSTR_T bfin_gen_ldstidxi (REG_T ptr, REG_T reg, int w, int sz, int z, Expr_Node *offset)
INSTR_T bfin_gen_ldst (REG_T ptr, REG_T reg, int aop, int sz, int z, int w)
INSTR_T bfin_gen_ldstii (REG_T ptr, REG_T reg, Expr_Node *offset, int w, int op)
INSTR_T bfin_gen_ldstiifp (REG_T reg, Expr_Node *offset, int w)
INSTR_T bfin_gen_ldstpmod (REG_T ptr, REG_T reg, int aop, int w, REG_T idx)
INSTR_T bfin_gen_dspldst (REG_T i, REG_T reg, int aop, int w, int m)
INSTR_T bfin_gen_alu2op (REG_T dst, REG_T src, int opc)
INSTR_T bfin_gen_compi2opd (REG_T dst, int src, int op)
INSTR_T bfin_gen_compi2opp (REG_T dst, int src, int op)
INSTR_T bfin_gen_dagmodik (REG_T i, int op)
INSTR_T bfin_gen_dagmodim (REG_T i, REG_T m, int op, int br)
INSTR_T bfin_gen_ptr2op (REG_T dst, REG_T src, int opc)
INSTR_T bfin_gen_logi2op (int dst, int src, int opc)
INSTR_T bfin_gen_comp3op (REG_T src0, REG_T src1, REG_T dst, int opc)
INSTR_T bfin_gen_ccmv (REG_T src, REG_T dst, int t)
INSTR_T bfin_gen_ccflag (REG_T x, int y, int opc, int i, int g)
INSTR_T bfin_gen_cc2stat (int cbit, int op, int d)
INSTR_T bfin_gen_regmv (REG_T src, REG_T dst)
INSTR_T bfin_gen_cc2dreg (int op, REG_T reg)
INSTR_T bfin_gen_brcc (int t, int b, Expr_Node *offset)
INSTR_T bfin_gen_ujump (Expr_Node *offset)
INSTR_T bfin_gen_cactrl (REG_T reg, int a, int op)
INSTR_T bfin_gen_progctrl (int prgfunc, int poprnd)
INSTR_T bfin_gen_loopsetup (Expr_Node *soffset, REG_T c, int rop, Expr_Node *eoffset, REG_T reg)
INSTR_T bfin_gen_loop (Expr_Node *expr, REG_T reg, int rop, REG_T preg)
INSTR_T bfin_gen_pushpopmultiple (int dr, int pr, int d, int p, int w)
INSTR_T bfin_gen_pushpopreg (REG_T reg, int w)
INSTR_T bfin_gen_calla (Expr_Node *addr, int s)
INSTR_T bfin_gen_linkage (int r, int framesize)
INSTR_T bfin_gen_pseudodbg (int fn, int reg, int grp)
INSTR_T bfin_gen_pseudodbg_assert (int dbgop, REG_T regtest, int expected)
bfd_boolean bfin_resource_conflict (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)
INSTR_T bfin_gen_multi_instr (INSTR_T dsp32, INSTR_T dsp16_grp1, INSTR_T dsp16_grp2)

Define Documentation

#define REG_T   Register *

Definition at line 24 of file bfin-aux.h.


Function Documentation

INSTR_T bfin_gen_alu2op ( REG_T  dst,
REG_T  src,
int  opc 
)

Definition at line 1652 of file tc-bfin.c.

{
  INIT (ALU2op);

  ASSIGN_R (dst);
  ASSIGN_R (src);
  ASSIGN (opc);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_brcc ( int  t,
int  b,
Expr_Node *  offset 
)

Definition at line 1625 of file tc-bfin.c.

{
  int offset;
  INIT (BRCC);

  ASSIGN (T);
  ASSIGN (B);
  offset = ((EXPR_VALUE (poffset) >> 1));
  ASSIGN (offset);
  return conscode (gencode (c_code.opcode), Expr_Node_Gen_Reloc (poffset, BFD_RELOC_BFIN_10_PCREL));
}

Here is the call graph for this function:

INSTR_T bfin_gen_cactrl ( REG_T  reg,
int  a,
int  op 
)

Definition at line 1819 of file tc-bfin.c.

{
  INIT (CaCTRL);

  ASSIGN_R (reg);
  ASSIGN (a);
  ASSIGN (op);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_calla ( Expr_Node *  addr,
int  s 
)

Definition at line 1382 of file tc-bfin.c.

{
  int val;
  int high_val;
  int reloc = 0;
  INIT (CALLa);

  switch(S){
   case 0 : reloc = BFD_RELOC_BFIN_24_PCREL_JUMP_L; break;
   case 1 : reloc = BFD_RELOC_24_PCREL; break;
   case 2 : reloc = BFD_RELOC_BFIN_PLTPC; break;
   default : break;
  }

  ASSIGN (S);

  val = EXPR_VALUE (addr) >> 1;
  high_val = val >> 16;

  return conscode (gencode (HI (c_code.opcode) | (high_val & 0xff)),
                     Expr_Node_Gen_Reloc (addr, reloc));
  }

Here is the call graph for this function:

INSTR_T bfin_gen_cc2dreg ( int  op,
REG_T  reg 
)

Definition at line 1797 of file tc-bfin.c.

{
  INIT (CC2dreg);

  ASSIGN (op);
  ASSIGN_R (reg);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_cc2stat ( int  cbit,
int  op,
int  d 
)

Definition at line 1768 of file tc-bfin.c.

{
  INIT (CC2stat);

  ASSIGN (cbit);
  ASSIGN (op);
  ASSIGN (D);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_ccflag ( REG_T  x,
int  y,
int  opc,
int  i,
int  g 
)

Definition at line 1737 of file tc-bfin.c.

{
  INIT (CCflag);

  ASSIGN_R (x);
  ASSIGN (y);
  ASSIGN (opc);
  ASSIGN (I);
  ASSIGN (G);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_ccmv ( REG_T  src,
REG_T  dst,
int  t 
)

Definition at line 1751 of file tc-bfin.c.

{
  int s, d;
  INIT (CCmv);

  ASSIGN_R (src);
  ASSIGN_R (dst);
  s = (GROUP (src));
  ASSIGN (s);
  d = (GROUP (dst));
  ASSIGN (d);
  ASSIGN (T);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_comp3op ( REG_T  src0,
REG_T  src1,
REG_T  dst,
int  opc 
)

Definition at line 1724 of file tc-bfin.c.

{
  INIT (COMP3op);

  ASSIGN_R (src0);
  ASSIGN_R (src1);
  ASSIGN_R (dst);
  ASSIGN (opc);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_compi2opd ( REG_T  dst,
int  src,
int  op 
)

Definition at line 1664 of file tc-bfin.c.

{
  INIT (COMPI2opD);

  ASSIGN_R (dst);
  ASSIGN (src);
  ASSIGN (op);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_compi2opp ( REG_T  dst,
int  src,
int  op 
)

Definition at line 1676 of file tc-bfin.c.

{
  INIT (COMPI2opP);

  ASSIGN_R (dst);
  ASSIGN (src);
  ASSIGN (op);

  return GEN_OPCODE16 ();
}

Definition at line 1688 of file tc-bfin.c.

{
  INIT (DagMODik);

  ASSIGN_R (i);
  ASSIGN (op);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_dagmodim ( REG_T  i,
REG_T  m,
int  op,
int  br 
)

Definition at line 1699 of file tc-bfin.c.

{
  INIT (DagMODim);

  ASSIGN_R (i);
  ASSIGN_R (m);
  ASSIGN (op);
  ASSIGN (br);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_dsp32alu ( int  HL,
int  aopcde,
int  aop,
int  s,
int  x,
REG_T  dst0,
REG_T  dst1,
REG_T  src0,
REG_T  src1 
)

Definition at line 1303 of file tc-bfin.c.

{
  INIT (DSP32Alu);

  ASSIGN (HL);
  ASSIGN (aopcde);
  ASSIGN (aop);
  ASSIGN (s);
  ASSIGN (x);
  ASSIGN_R (dst0);
  ASSIGN_R (dst1);
  ASSIGN_R (src0);
  ASSIGN_R (src1);

  return GEN_OPCODE32 ();
}
INSTR_T bfin_gen_dsp32mac ( int  op1,
int  mm,
int  mmod,
int  w1,
int  p,
int  h01,
int  h11,
int  h00,
int  h10,
int  op0,
REG_T  dst,
REG_T  src0,
REG_T  src1,
int  w0 
)

Definition at line 1239 of file tc-bfin.c.

{
  INIT (DSP32Mac);

  ASSIGN (op0);
  ASSIGN (op1);
  ASSIGN (MM);
  ASSIGN (mmod);
  ASSIGN (w0);
  ASSIGN (w1);
  ASSIGN (h01);
  ASSIGN (h11);
  ASSIGN (h00);
  ASSIGN (h10);
  ASSIGN (P);

  /* If we have full reg assignments, mask out LSB to encode
  single or simultaneous even/odd register moves.  */
  if (P)
    {
      dst->regno &= 0x06;
    }

  ASSIGN_R (dst);
  ASSIGN_R (src0);
  ASSIGN_R (src1);

  return GEN_OPCODE32 ();
}
INSTR_T bfin_gen_dsp32mult ( int  op1,
int  mm,
int  mmod,
int  w1,
int  p,
int  h01,
int  h11,
int  h00,
int  h10,
int  op0,
REG_T  dst,
REG_T  src0,
REG_T  src1,
int  w0 
)

Definition at line 1272 of file tc-bfin.c.

{
  INIT (DSP32Mult);

  ASSIGN (op0);
  ASSIGN (op1);
  ASSIGN (MM);
  ASSIGN (mmod);
  ASSIGN (w0);
  ASSIGN (w1);
  ASSIGN (h01);
  ASSIGN (h11);
  ASSIGN (h00);
  ASSIGN (h10);
  ASSIGN (P);

  if (P)
    {
      dst->regno &= 0x06;
    }

  ASSIGN_R (dst);
  ASSIGN_R (src0);
  ASSIGN_R (src1);

  return GEN_OPCODE32 ();
}
INSTR_T bfin_gen_dsp32shift ( int  sopcde,
REG_T  dst0,
REG_T  src0,
REG_T  src1,
int  sop,
int  hls 
)

Definition at line 1322 of file tc-bfin.c.

{
  INIT (DSP32Shift);

  ASSIGN (sopcde);
  ASSIGN (sop);
  ASSIGN (HLs);

  ASSIGN_R (dst0);
  ASSIGN_R (src0);
  ASSIGN_R (src1);

  return GEN_OPCODE32 ();
}
INSTR_T bfin_gen_dsp32shiftimm ( int  sopcde,
REG_T  dst0,
int  immag,
REG_T  src1,
int  sop,
int  hls 
)

Definition at line 1339 of file tc-bfin.c.

{
  INIT (DSP32ShiftImm);

  ASSIGN (sopcde);
  ASSIGN (sop);
  ASSIGN (HLs);

  ASSIGN_R (dst0);
  ASSIGN (immag);
  ASSIGN_R (src1);

  return GEN_OPCODE32 ();
}
INSTR_T bfin_gen_dspldst ( REG_T  i,
REG_T  reg,
int  aop,
int  w,
int  m 
)

Definition at line 1599 of file tc-bfin.c.

{
  INIT (DspLDST);

  ASSIGN_R (i);
  ASSIGN_R (reg);
  ASSIGN (aop);
  ASSIGN (W);
  ASSIGN (m);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_ldimmhalf ( REG_T  reg,
int  h,
int  s,
int  z,
Expr_Node *  hword,
int  reloc 
)

Definition at line 1420 of file tc-bfin.c.

{
  int grp, hword;
  unsigned val = EXPR_VALUE (phword);
  INIT (LDIMMhalf);

  ASSIGN (H);
  ASSIGN (S);
  ASSIGN (Z);

  ASSIGN_R (reg);
  grp = (GROUP (reg));
  ASSIGN (grp);
  if (reloc == 2)
    {
      return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, BFD_RELOC_BFIN_16_IMM));
    }
  else if (reloc == 1)
    {
      return conscode (gencode (HI (c_code.opcode)), Expr_Node_Gen_Reloc (phword, IS_H (*reg) ? BFD_RELOC_BFIN_16_HIGH : BFD_RELOC_BFIN_16_LOW));
    }
  else
    {
      hword = val;
      ASSIGN (hword);
    }
  return GEN_OPCODE32 ();
}

Here is the call graph for this function:

INSTR_T bfin_gen_ldst ( REG_T  ptr,
REG_T  reg,
int  aop,
int  sz,
int  z,
int  w 
)

Definition at line 1513 of file tc-bfin.c.

{
  INIT (LDST);

  if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
    {
      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
      return 0;
    }

  ASSIGN_R (ptr);
  ASSIGN_R (reg);
  ASSIGN (aop);
  ASSIGN (sz);
  ASSIGN (Z);
  ASSIGN (W);

  return GEN_OPCODE16 ();
}

Here is the call graph for this function:

INSTR_T bfin_gen_ldstidxi ( REG_T  ptr,
REG_T  reg,
int  w,
int  sz,
int  z,
Expr_Node *  offset 
)

Definition at line 1450 of file tc-bfin.c.

{
  INIT (LDSTidxI);

  if (!IS_PREG (*ptr) || (!IS_DREG (*reg) && !Z))
    {
      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
      return 0;
    }

  ASSIGN_R (ptr);
  ASSIGN_R (reg);
  ASSIGN (W);
  ASSIGN (sz);

  ASSIGN (Z);

  if (poffset->type != Expr_Node_Constant)
    {
      /* a GOT relocation such as R0 = [P5 + symbol@GOT] */
      /* distinguish between R0 = [P5 + symbol@GOT] and
        P5 = [P5 + _current_shared_library_p5_offset_]
      */
      if (poffset->type == Expr_Node_Reloc
         && !strcmp (poffset->value.s_value,
                    "_current_shared_library_p5_offset_"))
       {
         return  conscode (gencode (HI (c_code.opcode)),
                         Expr_Node_Gen_Reloc(poffset, BFD_RELOC_16));
       }
      else if (poffset->type != Expr_Node_GOT_Reloc)
       abort ();

      return conscode (gencode (HI (c_code.opcode)),
                     Expr_Node_Gen_Reloc(poffset->Left_Child,
                                      poffset->value.i_value));
    }
  else
    {
      int value, offset;
      switch (sz)
       {                           // load/store access size
       case 0:                     // 32 bit
         value = EXPR_VALUE (poffset) >> 2;
         break;
       case 1:                     // 16 bit
         value = EXPR_VALUE (poffset) >> 1;
         break;
       case 2:                     // 8 bit
         value = EXPR_VALUE (poffset);
         break;
       default:
         abort ();
       }

      offset = (value & 0xffff);
      ASSIGN (offset);
      return GEN_OPCODE32 ();
    }
}

Here is the call graph for this function:

INSTR_T bfin_gen_ldstii ( REG_T  ptr,
REG_T  reg,
Expr_Node *  offset,
int  w,
int  op 
)

Definition at line 1534 of file tc-bfin.c.

{
  int offset;
  int value = 0;
  INIT (LDSTii);


  if (!IS_PREG (*ptr))
    {
      fprintf (stderr, "Warning: possible mixup of Preg/Dreg\n");
      return 0;
    }

  switch (op)
    {
    case 1:
    case 2:
      value = EXPR_VALUE (poffset) >> 1;
      break;
    case 0:
    case 3:
      value = EXPR_VALUE (poffset) >> 2;
      break;
    }

  ASSIGN_R (ptr);
  ASSIGN_R (reg);

  offset = value;
  ASSIGN (offset);
  ASSIGN (W);
  ASSIGN (op);

  return GEN_OPCODE16 ();
}

Here is the call graph for this function:

INSTR_T bfin_gen_ldstiifp ( REG_T  reg,
Expr_Node *  offset,
int  w 
)

Definition at line 1571 of file tc-bfin.c.

{
  /* Set bit 4 if it's a Preg.  */
  int reg = (sreg->regno & CODE_MASK) | (IS_PREG (*sreg) ? 0x8 : 0x0);
  int offset = ((~(EXPR_VALUE (poffset) >> 2)) & 0x1f) + 1;
  INIT (LDSTiiFP);
  ASSIGN (reg);
  ASSIGN (offset);
  ASSIGN (W);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_ldstpmod ( REG_T  ptr,
REG_T  reg,
int  aop,
int  w,
REG_T  idx 
)

Definition at line 1585 of file tc-bfin.c.

{
  INIT (LDSTpmod);

  ASSIGN_R (ptr);
  ASSIGN_R (reg);
  ASSIGN (aop);
  ASSIGN (W);
  ASSIGN_R (idx);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_linkage ( int  r,
int  framesize 
)

Definition at line 1406 of file tc-bfin.c.

{
  INIT (Linkage);

  ASSIGN (R);
  ASSIGN (framesize);

  return GEN_OPCODE32 ();
}
INSTR_T bfin_gen_logi2op ( int  dst,
int  src,
int  opc 
)

Definition at line 1613 of file tc-bfin.c.

{
  INIT (LOGI2op);

  ASSIGN (opc);
  ASSIGN (src);
  ASSIGN (dst);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_loop ( Expr_Node *  expr,
REG_T  reg,
int  rop,
REG_T  preg 
)

Definition at line 1922 of file tc-bfin.c.

{
  const char *loopsym;
  char *lbeginsym, *lendsym;
  Expr_Node_Value lbeginval, lendval;
  Expr_Node *lbegin, *lend;

  loopsym = expr->value.s_value;
  lbeginsym = (char *) xmalloc (strlen (loopsym) + strlen ("__BEGIN") + 1);
  lendsym = (char *) xmalloc (strlen (loopsym) + strlen ("__END") + 1);

  lbeginsym[0] = 0;
  lendsym[0] = 0;

  strcat (lbeginsym, loopsym);
  strcat (lbeginsym, "__BEGIN");

  strcat (lendsym, loopsym);
  strcat (lendsym, "__END");

  lbeginval.s_value = lbeginsym;
  lendval.s_value = lendsym;

  lbegin = Expr_Node_Create (Expr_Node_Reloc, lbeginval, NULL, NULL);
  lend   = Expr_Node_Create (Expr_Node_Reloc, lendval, NULL, NULL);
  return bfin_gen_loopsetup(lbegin, reg, rop, lend, preg);
}

Here is the call graph for this function:

INSTR_T bfin_gen_loopsetup ( Expr_Node *  soffset,
REG_T  c,
int  rop,
Expr_Node *  eoffset,
REG_T  reg 
)

Definition at line 1358 of file tc-bfin.c.

{
  int soffset, eoffset;
  INIT (LoopSetup);

  soffset = (EXPR_VALUE (psoffset) >> 1);
  ASSIGN (soffset);
  eoffset = (EXPR_VALUE (peoffset) >> 1);
  ASSIGN (eoffset);
  ASSIGN (rop);
  ASSIGN_R (c);
  ASSIGN_R (reg);

  return
      conscode (gencode (HI (c_code.opcode)),
              conctcode (Expr_Node_Gen_Reloc (psoffset, BFD_RELOC_BFIN_5_PCREL),
                        conctcode (gencode (LO (c_code.opcode)), Expr_Node_Gen_Reloc (peoffset, BFD_RELOC_BFIN_11_PCREL))));

}

Here is the call graph for this function:

Here is the caller graph for this function:

INSTR_T bfin_gen_multi_instr ( INSTR_T  dsp32,
INSTR_T  dsp16_grp1,
INSTR_T  dsp16_grp2 
)

Definition at line 1887 of file tc-bfin.c.

{
  INSTR_T walk;

  /* If it's a 0, convert into MNOP. */
  if (dsp32)
    {
      walk = dsp32->next;
      SET_MULTI_INSTRUCTION_BIT (dsp32);
    }
  else
    {
      dsp32 = gencode (0xc803);
      walk = gencode (0x1800);
      dsp32->next = walk;
    }

  if (!dsp16_grp1)
    {
      dsp16_grp1 = gencode (0x0000);
    }

  if (!dsp16_grp2)
    {
      dsp16_grp2 = gencode (0x0000);
    }

  walk->next = dsp16_grp1;
  dsp16_grp1->next = dsp16_grp2;
  dsp16_grp2->next = NULL_CODE;

  return dsp32;
}

Here is the call graph for this function:

INSTR_T bfin_gen_progctrl ( int  prgfunc,
int  poprnd 
)

Definition at line 1808 of file tc-bfin.c.

{
  INIT (ProgCtrl);

  ASSIGN (prgfunc);
  ASSIGN (poprnd);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_pseudodbg ( int  fn,
int  reg,
int  grp 
)

Definition at line 1861 of file tc-bfin.c.

{
  INIT (PseudoDbg);

  ASSIGN (fn);
  ASSIGN (reg);
  ASSIGN (grp);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_pseudodbg_assert ( int  dbgop,
REG_T  regtest,
int  expected 
)

Definition at line 1873 of file tc-bfin.c.

{
  INIT (PseudoDbg_Assert);

  ASSIGN (dbgop);
  ASSIGN_R (regtest);
  ASSIGN (expected);

  return GEN_OPCODE32 ();
}
INSTR_T bfin_gen_ptr2op ( REG_T  dst,
REG_T  src,
int  opc 
)

Definition at line 1712 of file tc-bfin.c.

{
  INIT (PTR2op);

  ASSIGN_R (dst);
  ASSIGN_R (src);
  ASSIGN (opc);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_pushpopmultiple ( int  dr,
int  pr,
int  d,
int  p,
int  w 
)

Definition at line 1831 of file tc-bfin.c.

{
  INIT (PushPopMultiple);

  ASSIGN (dr);
  ASSIGN (pr);
  ASSIGN (d);
  ASSIGN (p);
  ASSIGN (W);

  return GEN_OPCODE16 ();
}

Definition at line 1845 of file tc-bfin.c.

{
  int grp;
  INIT (PushPopReg);

  ASSIGN_R (reg);
  grp = (GROUP (reg));
  ASSIGN (grp);
  ASSIGN (W);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_regmv ( REG_T  src,
REG_T  dst 
)

Definition at line 1780 of file tc-bfin.c.

{
  int gs, gd;
  INIT (RegMv);

  ASSIGN_R (src);
  ASSIGN_R (dst);

  gs = (GROUP (src));
  ASSIGN (gs);
  gd = (GROUP (dst));
  ASSIGN (gd);

  return GEN_OPCODE16 ();
}
INSTR_T bfin_gen_ujump ( Expr_Node *  offset)

Definition at line 1638 of file tc-bfin.c.

{
  int offset;
  INIT (UJump);

  offset = ((EXPR_VALUE (poffset) >> 1));
  ASSIGN (offset);

  return conscode (gencode (c_code.opcode),
                   Expr_Node_Gen_Reloc (
                       poffset, BFD_RELOC_BFIN_12_PCREL_JUMP_S));
}

Here is the call graph for this function:

bfd_boolean bfin_resource_conflict ( INSTR_T  dsp32,
INSTR_T  dsp16_grp1,
INSTR_T  dsp16_grp2 
)