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cell-binutils  2.17cvs20070401
astest2.d
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00001 #objdump: -Dr
00002 #name: PowerPC test 2
00003 
00004 .*: +file format elf32-powerpc
00005 
00006 Disassembly of section \.text:
00007 
00008 0+0000000 <foo>:
00009    0:  60 00 00 00   nop
00010    4:  60 00 00 00   nop
00011    8:  60 00 00 00   nop
00012    c:  48 00 00 04   b       10 <foo\+0x10>
00013   10:  48 00 00 08   b       18 <foo\+0x18>
00014   14:  48 00 00 00   b       14 <foo\+0x14>
00015                      14: R_PPC_REL24      x
00016   18:  48 00 00 04   b       1c <foo\+0x1c>
00017                      18: R_PPC_REL24      \.data\+0x4
00018   1c:  48 00 00 00   b       1c <foo\+0x1c>
00019                      1c: R_PPC_REL24      z
00020   20:  48 00 00 14   b       34 <foo\+0x34>
00021                      20: R_PPC_REL24      z\+0x14
00022   24:  48 00 00 04   b       28 <foo\+0x28>
00023   28:  48 00 00 00   b       28 <foo\+0x28>
00024                      28: R_PPC_REL24      a
00025   2c:  48 00 00 50   b       7c <apfour>
00026   30:  48 00 00 04   b       34 <foo\+0x34>
00027                      30: R_PPC_REL24      a\+0x4
00028   34:  48 00 00 4c   b       80 <apfour\+0x4>
00029   38:  48 00 00 00   b       38 <foo\+0x38>
00030                      38: R_PPC_LOCAL24PC  a
00031   3c:  48 00 00 40   b       7c <apfour>
00032   40:  00 00 00 40   \.long 0x40
00033                      40: R_PPC_ADDR32     \.text\+0x40
00034   44:  00 00 00 4c   \.long 0x4c
00035                      44: R_PPC_ADDR32     \.text\+0x4c
00036   48:  00 00 00 00   \.long 0x0
00037                      48: R_PPC_REL32      x
00038   4c:  00 00 00 04   \.long 0x4
00039                      4c: R_PPC_REL32      x\+0x4
00040   50:  00 00 00 00   \.long 0x0
00041                      50: R_PPC_REL32      z
00042   54:  00 00 00 04   \.long 0x4
00043                      54: R_PPC_REL32      \.data\+0x4
00044   58:  00 00 00 00   \.long 0x0
00045                      58: R_PPC_ADDR32     x
00046   5c:  00 00 00 04   \.long 0x4
00047                      5c: R_PPC_ADDR32     \.data\+0x4
00048   60:  00 00 00 00   \.long 0x0
00049                      60: R_PPC_ADDR32     z
00050   64:  ff ff ff fc   fnmsub  f31,f31,f31,f31
00051                      64: R_PPC_ADDR32     x\+0xf+ffffffc
00052   68:  00 00 00 00   \.long 0x0
00053                      68: R_PPC_ADDR32     \.data
00054   6c:  ff ff ff fc   fnmsub  f31,f31,f31,f31
00055                      6c: R_PPC_ADDR32     z\+0xf+ffffffc
00056   70:  00 00 00 08   \.long 0x8
00057   74:  00 00 00 08   \.long 0x8
00058 
00059 0+0000078 <a>:
00060   78:  00 00 00 00   \.long 0x0
00061                      78: R_PPC_ADDR32     a
00062 
00063 0+000007c <apfour>:
00064   7c:  00 00 00 7c   \.long 0x7c
00065                      7c: R_PPC_ADDR32     \.text\+0x7c
00066   80:  00 00 00 7c   \.long 0x7c
00067                      80: R_PPC_ADDR32     \.text\+0x7c
00068   84:  ff ff ff fc   fnmsub  f31,f31,f31,f31
00069   88:  00 00 00 7e   \.long 0x7e
00070                      88: R_PPC_ADDR32     \.text\+0x7e
00071   8c:  00 00 00 00   \.long 0x0
00072   90:  60 00 00 00   nop
00073   94:  40 a5 ff fc   ble-    cr1,90 <apfour\+0x14>
00074   98:  41 a9 ff f8   bgt-    cr2,90 <apfour\+0x14>
00075   9c:  40 8d ff f4   ble\+    cr3,90 <apfour\+0x14>
00076   a0:  41 91 ff f0   bgt\+    cr4,90 <apfour\+0x14>
00077   a4:  40 95 00 10   ble-    cr5,b4 <nop>
00078   a8:  41 99 00 0c   bgt-    cr6,b4 <nop>
00079   ac:  40 bd 00 08   ble\+    cr7,b4 <nop>
00080   b0:  41 a1 00 04   bgt\+    b4 <nop>
00081 Disassembly of section \.data:
00082 
00083 0+0000000 <x>:
00084    0:  00 00 00 00   \.long 0x0
00085 
00086 0+0000004 <y>:
00087    4:  00 00 00 00   \.long 0x0