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cell-binutils  2.17cvs20070401
arm-dis.c
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00001 /* Instruction printing code for the ARM
00002    Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
00003    Free Software Foundation, Inc.
00004    Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
00005    Modification by James G. Smith (jsmith@cygnus.co.uk)
00006 
00007    This file is part of libopcodes.
00008 
00009    This program is free software; you can redistribute it and/or modify it under
00010    the terms of the GNU General Public License as published by the Free
00011    Software Foundation; either version 2 of the License, or (at your option)
00012    any later version.
00013 
00014    This program is distributed in the hope that it will be useful, but WITHOUT
00015    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
00016    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
00017    more details.
00018 
00019    You should have received a copy of the GNU General Public License
00020    along with this program; if not, write to the Free Software
00021    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
00022 
00023 #include "sysdep.h"
00024 
00025 #include "dis-asm.h"
00026 #include "opcode/arm.h"
00027 #include "opintl.h"
00028 #include "safe-ctype.h"
00029 #include "floatformat.h"
00030 
00031 /* FIXME: This shouldn't be done here.  */
00032 #include "coff/internal.h"
00033 #include "libcoff.h"
00034 #include "elf-bfd.h"
00035 #include "elf/internal.h"
00036 #include "elf/arm.h"
00037 
00038 /* FIXME: Belongs in global header.  */
00039 #ifndef strneq
00040 #define strneq(a,b,n)       (strncmp ((a), (b), (n)) == 0)
00041 #endif
00042 
00043 #ifndef NUM_ELEM
00044 #define NUM_ELEM(a)     (sizeof (a) / sizeof (a)[0])
00045 #endif
00046 
00047 struct opcode32
00048 {
00049   unsigned long arch;              /* Architecture defining this insn.  */
00050   unsigned long value, mask;       /* Recognise insn if (op&mask)==value.  */
00051   const char *assembler;    /* How to disassemble this insn.  */
00052 };
00053 
00054 struct opcode16
00055 {
00056   unsigned long arch;              /* Architecture defining this insn.  */
00057   unsigned short value, mask;      /* Recognise insn if (op&mask)==value.  */
00058   const char *assembler;    /* How to disassemble this insn.  */
00059 };
00060 
00061 /* print_insn_coprocessor recognizes the following format control codes:
00062 
00063    %%                %
00064 
00065    %c                print condition code (always bits 28-31 in ARM mode)
00066    %u                print condition code (unconditional in ARM mode)
00067    %A                print address for ldc/stc/ldf/stf instruction
00068    %B                print vstm/vldm register list
00069    %C                print vstr/vldr address operand
00070    %I                   print cirrus signed shift immediate: bits 0..3|4..6
00071    %F                print the COUNT field of a LFM/SFM instruction.
00072    %P                print floating point precision in arithmetic insn
00073    %Q                print floating point precision in ldf/stf insn
00074    %R                print floating point rounding mode
00075 
00076    %<bitfield>r             print as an ARM register
00077    %<bitfield>d             print the bitfield in decimal
00078    %<bitfield>k             print immediate for VFPv3 conversion instruction
00079    %<bitfield>x             print the bitfield in hex
00080    %<bitfield>X             print the bitfield as 1 hex digit without leading "0x"
00081    %<bitfield>f             print a floating point constant if >7 else a
00082                      floating point register
00083    %<bitfield>w         print as an iWMMXt width field - [bhwd]ss/us
00084    %<bitfield>g         print as an iWMMXt 64-bit register
00085    %<bitfield>G         print as an iWMMXt general purpose or control register
00086    %<bitfield>D             print as a NEON D register
00087    %<bitfield>Q             print as a NEON Q register
00088 
00089    %y<code>          print a single precision VFP reg.
00090                        Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
00091    %z<code>          print a double precision VFP reg
00092                        Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
00093 
00094    %<bitfield>'c     print specified char iff bitfield is all ones
00095    %<bitfield>`c     print specified char iff bitfield is all zeroes
00096    %<bitfield>?ab...    select from array of values in big endian order
00097    
00098    %L                print as an iWMMXt N/M width field.
00099    %Z                print the Immediate of a WSHUFH instruction.
00100    %l                like 'A' except use byte offsets for 'B' & 'H'
00101                      versions.
00102    %i                print 5-bit immediate in bits 8,3..0
00103                      (print "32" when 0)
00104    %r                print register offset address for wldt/wstr instruction
00105 */
00106 
00107 /* Common coprocessor opcodes shared between Arm and Thumb-2.  */
00108 
00109 static const struct opcode32 coprocessor_opcodes[] =
00110 {
00111   /* XScale instructions.  */
00112   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
00113   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
00114   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
00115   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
00116   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
00117     
00118   /* Intel Wireless MMX technology instructions.  */
00119 #define FIRST_IWMMXT_INSN 0x0e130130
00120 #define IWMMXT_INSN_COUNT 73
00121   {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
00122   {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
00123   {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
00124   {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
00125   {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
00126   {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
00127   {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
00128   {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
00129   {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
00130   {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
00131   {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
00132   {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
00133   {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
00134   {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
00135   {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
00136   {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
00137   {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
00138   {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
00139   {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
00140   {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
00141   {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
00142   {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
00143   {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
00144   {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
00145   {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
00146   {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00147   {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00148   {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
00149   {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
00150   {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
00151   {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
00152   {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
00153   {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
00154   {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00155   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
00156   {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
00157   {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
00158   {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00159   {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
00160   {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
00161   {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
00162   {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
00163   {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
00164   {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
00165   {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
00166   {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
00167   {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
00168   {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
00169   {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
00170   {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00171   {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
00172   {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
00173   {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
00174   {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
00175   {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
00176   {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
00177   {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
00178   {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
00179   {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
00180   {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
00181   {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
00182   {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
00183   {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
00184   {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
00185   {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
00186   {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
00187   {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
00188   {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00189   {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
00190   {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
00191   {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
00192   {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
00193   {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00194   {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
00195   {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
00196 
00197   /* Floating point coprocessor (FPA) instructions */
00198   {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
00199   {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
00200   {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
00201   {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
00202   {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
00203   {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
00204   {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
00205   {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
00206   {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
00207   {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
00208   {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
00209   {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
00210   {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
00211   {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
00212   {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
00213   {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
00214   {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
00215   {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
00216   {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
00217   {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
00218   {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
00219   {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
00220   {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
00221   {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
00222   {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
00223   {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
00224   {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
00225   {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
00226   {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
00227   {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
00228   {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
00229   {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
00230   {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
00231   {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
00232   {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
00233   {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
00234   {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
00235   {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
00236   {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
00237   {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
00238   {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
00239   {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
00240   {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
00241 
00242   /* Register load/store */
00243   {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"},
00244   {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"},
00245   {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
00246   {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
00247   {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"},
00248   {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"},
00249 
00250   /* Data transfer between ARM and NEON registers */
00251   {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
00252   {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
00253   {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
00254   {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
00255   {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
00256   {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
00257   {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
00258   {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
00259   {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
00260   {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
00261   {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
00262   {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
00263   {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
00264   {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
00265 
00266   /* Floating point coprocessor (VFP) instructions */
00267   {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"},
00268   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"},
00269   {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"},
00270   {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"},
00271   {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"},
00272   {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"},
00273   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"},
00274   {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"},
00275   {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"},
00276   {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"},
00277   {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"},
00278   {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"},
00279   {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"},
00280   {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"},
00281   {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"},
00282   {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"},
00283   {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"},
00284   {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"},
00285   {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"},
00286   {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"},
00287   {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"},
00288   {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"},
00289   {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"},
00290   {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"},
00291   {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"},
00292   {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"},
00293   {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"},
00294   {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"},
00295   {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"},
00296   {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"},
00297   {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"},
00298   {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"},
00299   {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"},
00300   {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"},
00301   {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"},
00302   {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"},
00303   {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"},
00304   {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"},
00305   {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"},
00306   {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"},
00307   {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"},
00308   {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"},
00309   {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"},
00310   {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"},
00311   {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"},
00312   {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"},
00313   {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"},
00314   {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"},
00315   {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"},
00316   {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"},
00317   {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"},
00318   {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"},
00319   {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"},
00320   {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"},
00321   {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"},
00322   {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"},
00323   {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"},
00324   {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"},
00325   {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"},
00326   {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"},
00327   {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"},
00328   {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"},
00329   {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"},
00330   {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"},
00331   {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"},
00332   {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"},
00333   {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"},
00334   {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"},
00335   {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"},
00336   {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"},
00337   {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"},
00338   {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"},
00339   {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"},
00340   {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"},
00341   {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"},
00342   {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"},
00343   {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"},
00344   {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"},
00345   {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"},
00346 
00347   /* Cirrus coprocessor instructions.  */
00348   {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
00349   {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
00350   {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
00351   {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, 
00352   {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
00353   {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
00354   {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
00355   {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
00356   {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
00357   {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
00358   {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
00359   {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
00360   {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
00361   {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
00362   {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
00363   {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
00364   {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
00365   {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
00366   {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
00367   {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
00368   {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
00369   {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
00370   {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
00371   {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
00372   {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
00373   {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
00374   {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
00375   {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
00376   {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
00377   {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
00378   {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
00379   {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
00380   {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
00381   {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
00382   {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
00383   {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
00384   {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
00385   {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
00386   {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
00387   {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
00388   {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
00389   {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
00390   {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
00391   {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
00392   {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
00393   {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
00394   {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
00395   {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
00396   {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
00397   {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
00398   {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
00399   {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
00400   {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
00401   {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
00402   {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
00403   {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
00404   {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
00405   {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
00406   {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
00407   {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
00408   {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
00409   {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
00410   {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
00411   {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
00412   {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
00413   {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
00414   {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
00415   {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
00416   {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
00417   {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
00418   {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
00419   {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
00420   {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
00421   {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
00422   {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
00423   {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
00424   {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
00425   {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
00426   {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
00427   {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
00428   {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
00429   {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
00430   {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
00431   {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
00432 
00433   /* Generic coprocessor instructions */
00434   {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
00435   {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
00436   {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
00437   {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
00438   {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
00439   {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%c%22'l\t%8-11d, cr%12-15d, %A"},
00440   {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%c%22'l\t%8-11d, cr%12-15d, %A"},
00441 
00442   /* V6 coprocessor instructions */
00443   {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
00444   {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"},
00445 
00446   /* V5 coprocessor instructions */
00447   {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
00448   {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
00449   {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
00450   {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
00451   {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
00452 
00453   {0, 0, 0, 0}
00454 };
00455 
00456 /* Neon opcode table:  This does not encode the top byte -- that is
00457    checked by the print_insn_neon routine, as it depends on whether we are
00458    doing thumb32 or arm32 disassembly.  */
00459 
00460 /* print_insn_neon recognizes the following format control codes:
00461 
00462    %%                %
00463 
00464    %c                print condition code
00465    %A                print v{st,ld}[1234] operands
00466    %B                print v{st,ld}[1234] any one operands
00467    %C                print v{st,ld}[1234] single->all operands
00468    %D                print scalar
00469    %E                print vmov, vmvn, vorr, vbic encoded constant
00470    %F                print vtbl,vtbx register list
00471 
00472    %<bitfield>r             print as an ARM register
00473    %<bitfield>d             print the bitfield in decimal
00474    %<bitfield>e         print the 2^N - bitfield in decimal
00475    %<bitfield>D             print as a NEON D register
00476    %<bitfield>Q             print as a NEON Q register
00477    %<bitfield>R             print as a NEON D or Q register
00478    %<bitfield>Sn     print byte scaled width limited by n
00479    %<bitfield>Tn     print short scaled width limited by n
00480    %<bitfield>Un     print long scaled width limited by n
00481    
00482    %<bitfield>'c     print specified char iff bitfield is all ones
00483    %<bitfield>`c     print specified char iff bitfield is all zeroes
00484    %<bitfield>?ab...    select from array of values in big endian order  */
00485 
00486 static const struct opcode32 neon_opcodes[] =
00487 {
00488   /* Extract */
00489   {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
00490   {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
00491 
00492   /* Move data element to all lanes */
00493   {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
00494   {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
00495   {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
00496 
00497   /* Table lookup */
00498   {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
00499   {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
00500   
00501   /* Two registers, miscellaneous */
00502   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
00503   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
00504   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
00505   {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
00506   {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
00507   {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
00508   {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
00509   {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
00510   {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
00511   {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
00512   {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
00513   {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
00514   {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
00515   {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
00516   {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
00517   {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
00518   {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
00519   {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
00520   {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
00521   {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
00522   {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
00523   {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
00524   {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
00525   {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
00526   {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
00527   {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
00528   {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
00529   {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
00530   {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
00531   {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
00532   {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
00533   {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
00534   {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
00535 
00536   /* Three registers of the same length */
00537   {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00538   {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00539   {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00540   {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00541   {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00542   {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00543   {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00544   {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
00545   {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00546   {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00547   {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00548   {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00549   {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00550   {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00551   {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00552   {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00553   {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00554   {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00555   {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00556   {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00557   {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00558   {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00559   {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00560   {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00561   {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00562   {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
00563   {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
00564   {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00565   {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00566   {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
00567   {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00568   {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
00569   {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00570   {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00571   {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
00572   {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00573   {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
00574   {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00575   {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00576   {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
00577   {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00578   {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00579   {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
00580   {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
00581   {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
00582   {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
00583   {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00584   {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00585   {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00586   {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00587   {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00588   {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00589   {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
00590 
00591   /* One register and an immediate value */
00592   {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
00593   {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
00594   {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
00595   {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
00596   {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
00597   {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
00598   {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
00599   {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
00600   {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
00601   {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
00602   {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
00603   {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
00604   {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
00605 
00606   /* Two registers and a shift amount */
00607   {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
00608   {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
00609   {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
00610   {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
00611   {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
00612   {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
00613   {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
00614   {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
00615   {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
00616   {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
00617   {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
00618   {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
00619   {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
00620   {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
00621   {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
00622   {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
00623   {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
00624   {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
00625   {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
00626   {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
00627   {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
00628   {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
00629   {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
00630   {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
00631   {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
00632   {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
00633   {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
00634   {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
00635   {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
00636   {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
00637   {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
00638   {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
00639   {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
00640   {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
00641   {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
00642   {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
00643   {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
00644   {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
00645   {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
00646   {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
00647   {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
00648   {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
00649   {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
00650   {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
00651   {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
00652   {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
00653   {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
00654   {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
00655   {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
00656   {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
00657   {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
00658   {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
00659   {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
00660   {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
00661   {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
00662   {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
00663   {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
00664   {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
00665 
00666   /* Three registers of different lengths */
00667   {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00668   {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
00669   {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
00670   {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00671   {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00672   {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00673   {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
00674   {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
00675   {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00676   {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
00677   {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00678   {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
00679   {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00680   {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00681   {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00682   {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00683   {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
00684 
00685   /* Two registers and a scalar */
00686   {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
00687   {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
00688   {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
00689   {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
00690   {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
00691   {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
00692   {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
00693   {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
00694   {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
00695   {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
00696   {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
00697   {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
00698   {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
00699   {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
00700   {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
00701   {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
00702   {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
00703   {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
00704   {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
00705   {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
00706   {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
00707   {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
00708 
00709   /* Element and structure load/store */
00710   {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
00711   {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
00712   {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
00713   {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
00714   {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
00715   {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
00716   {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
00717   {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
00718   {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
00719   {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
00720   {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
00721   {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
00722   {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
00723   {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
00724   {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
00725   {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
00726   {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
00727   {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
00728   {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
00729 
00730   {0,0 ,0, 0}
00731 };
00732 
00733 /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb.  All three are partially
00734    ordered: they must be searched linearly from the top to obtain a correct
00735    match.  */
00736 
00737 /* print_insn_arm recognizes the following format control codes:
00738 
00739    %%                %
00740 
00741    %a                print address for ldr/str instruction
00742    %s                   print address for ldr/str halfword/signextend instruction
00743    %b                print branch destination
00744    %c                print condition code (always bits 28-31)
00745    %m                print register mask for ldm/stm instruction
00746    %o                print operand2 (immediate or register + shift)
00747    %p                print 'p' iff bits 12-15 are 15
00748    %t                print 't' iff bit 21 set and bit 24 clear
00749    %B                print arm BLX(1) destination
00750    %C                print the PSR sub type.
00751    %U                print barrier type.
00752    %P                print address for pli instruction.
00753 
00754    %<bitfield>r             print as an ARM register
00755    %<bitfield>d             print the bitfield in decimal
00756    %<bitfield>W         print the bitfield plus one in decimal 
00757    %<bitfield>x             print the bitfield in hex
00758    %<bitfield>X             print the bitfield as 1 hex digit without leading "0x"
00759    
00760    %<bitfield>'c     print specified char iff bitfield is all ones
00761    %<bitfield>`c     print specified char iff bitfield is all zeroes
00762    %<bitfield>?ab...    select from array of values in big endian order
00763 
00764    %e                   print arm SMI operand (bits 0..7,8..19).
00765    %E                print the LSB and WIDTH fields of a BFI or BFC instruction.
00766    %V                   print the 16-bit immediate field of a MOVT or MOVW instruction.  */
00767 
00768 static const struct opcode32 arm_opcodes[] =
00769 {
00770   /* ARM instructions.  */
00771   {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"},
00772   {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
00773   {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%c%20's\t%16-19r, %0-3r, %8-11r"},
00774   {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%c%20's\t%16-19r, %0-3r, %8-11r, %12-15r"},
00775   {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%c%22'b\t%12-15r, %0-3r, [%16-19r]"},
00776   {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
00777   {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"},
00778 
00779   /* V7 instructions.  */
00780   {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
00781   {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
00782   {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
00783   {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
00784   {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
00785 
00786   /* ARM V6T2 instructions.  */
00787   {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"},
00788   {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"},
00789   {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00790   {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "str%cht\t%12-15r, %s"},
00791   {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%c%6's%5?hbt\t%12-15r, %s"},
00792   {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"},
00793   {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"},
00794   {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"},
00795   {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
00796 
00797   /* ARM V6Z instructions.  */
00798   {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
00799 
00800   /* ARM V6K instructions.  */
00801   {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
00802   {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"},
00803   {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"},
00804   {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"},
00805   {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"},
00806   {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"},
00807   {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"},
00808 
00809   /* ARM V6K NOP hints.  */
00810   {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
00811   {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
00812   {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
00813   {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
00814   {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
00815 
00816   /* ARM V6 instructions. */
00817   {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
00818   {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
00819   {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
00820   {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
00821   {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
00822   {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"},
00823   {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"},
00824   {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"},
00825   {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"},
00826   {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"},
00827   {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"},
00828   {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"},
00829   {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"},
00830   {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"},
00831   {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"},
00832   {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"},
00833   {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"},
00834   {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"},
00835   {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"},
00836   {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"},
00837   {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"},
00838   {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"},
00839   {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"},
00840   {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"},
00841   {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"},
00842   {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"},
00843   {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"},
00844   {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"},
00845   {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"},
00846   {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"},
00847   {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"},
00848   {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"},
00849   {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"},
00850   {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"},
00851   {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"},
00852   {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"},
00853   {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"},
00854   {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"},
00855   {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"},
00856   {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"},
00857   {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"},
00858   {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"},
00859   {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"},
00860   {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"},
00861   {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"},
00862   {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"},
00863   {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"},
00864   {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"},
00865   {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"},
00866   {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"},
00867   {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"},
00868   {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"},
00869   {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"},
00870   {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"},
00871   {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"},
00872   {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"},
00873   {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"},
00874   {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"},
00875   {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"},
00876   {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"},
00877   {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"},
00878   {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"},
00879   {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"},
00880   {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"},
00881   {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"},
00882   {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"},
00883   {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"},
00884   {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"},
00885   {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"},
00886   {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"},
00887   {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"},
00888   {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"},
00889   {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"},
00890   {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"},
00891   {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"},
00892   {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
00893   {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
00894   {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
00895   {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"},
00896   {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
00897   {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
00898   {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
00899   {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"},
00900   {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
00901   {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
00902   {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
00903   {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"},
00904   {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
00905   {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
00906   {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
00907   {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"},
00908   {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
00909   {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
00910   {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
00911   {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"},
00912   {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"},
00913   {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"},
00914   {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"},
00915   {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"},
00916   {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
00917   {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"},
00918   {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"},
00919   {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00920   {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
00921   {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00922   {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
00923   {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"},
00924   {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00925   {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00926   {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
00927   {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"},
00928   {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"},
00929   {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"},
00930   {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
00931   {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"},
00932   {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
00933   {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"},
00934   {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00935   {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"},
00936   {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"},
00937   {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"},
00938   {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"},
00939 
00940   /* V5J instruction.  */
00941   {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"},
00942 
00943   /* V5 Instructions.  */
00944   {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
00945   {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
00946   {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"},
00947   {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"},
00948 
00949   /* V5E "El Segundo" Instructions.  */    
00950   {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldr%cd\t%12-15r, %s"},
00951   {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "str%cd\t%12-15r, %s"},
00952   {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
00953   {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00954   {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00955   {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00956   {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00957 
00958   {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00959   {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"},
00960 
00961   {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
00962   {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
00963   {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
00964   {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"},
00965 
00966   {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"},
00967   {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"},
00968   {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"},
00969   {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"},
00970 
00971   {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"},
00972   {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"},
00973 
00974   {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0,  "qadd%c\t%12-15r, %0-3r, %16-19r"},
00975   {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"},
00976   {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0,  "qsub%c\t%12-15r, %0-3r, %16-19r"},
00977   {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"},
00978 
00979   /* ARM Instructions.  */
00980   {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"},
00981   {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"},
00982   {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"},
00983   {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"},
00984   {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"},
00985   {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%c%20's\t%12-15r, %16-19r, %o"},
00986   {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%c%20's\t%12-15r, %16-19r, %o"},
00987   {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%c%20's\t%12-15r, %16-19r, %o"},
00988   {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%c%20's\t%12-15r, %16-19r, %o"},
00989   {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%c%20's\t%12-15r, %16-19r, %o"},
00990   {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"},
00991   {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"},
00992   {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%c%p\t%16-19r, %o"},
00993   {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%c%p\t%16-19r, %o"},
00994   {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%c%p\t%16-19r, %o"},
00995   {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%c%p\t%16-19r, %o"},
00996   {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%c%20's\t%12-15r, %16-19r, %o"},
00997   {ARM_EXT_V1, 0x01a00000, 0x0de00000, "mov%c%20's\t%12-15r, %o"},
00998   {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%c%20's\t%12-15r, %16-19r, %o"},
00999   {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%c%20's\t%12-15r, %o"},
01000   {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%c%22'b%t\t%12-15r, %a"},
01001   {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%c%22'b%t\t%12-15r, %a"},
01002   {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%c%22'b%t\t%12-15r, %a"},
01003   {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"},
01004   {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%c%22'b%t\t%12-15r, %a"},
01005   {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
01006   {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba\t%16-19r%21'!, %m%22'^"},
01007   {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
01008   {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
01009 
01010   /* The rest.  */
01011   {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"},
01012   {0, 0x00000000, 0x00000000, 0}
01013 };
01014 
01015 /* print_insn_thumb16 recognizes the following format control codes:
01016 
01017    %S                   print Thumb register (bits 3..5 as high number if bit 6 set)
01018    %D                   print Thumb register (bits 0..2 as high number if bit 7 set)
01019    %<bitfield>I         print bitfield as a signed decimal
01020                             (top bit of range being the sign bit)
01021    %N                   print Thumb register mask (with LR)
01022    %O                   print Thumb register mask (with PC)
01023    %M                   print Thumb register mask
01024    %b                print CZB's 6-bit unsigned branch destination
01025    %s                print Thumb right-shift immediate (6..10; 0 == 32).
01026    %c                print the condition code
01027    %C                print the condition code, or "s" if not conditional
01028    %x                print warning if conditional an not at end of IT block"
01029    %X                print "\t; unpredictable <IT:code>" if conditional
01030    %I                print IT instruction suffix and operands
01031    %<bitfield>r             print bitfield as an ARM register
01032    %<bitfield>d             print bitfield as a decimal
01033    %<bitfield>H         print (bitfield * 2) as a decimal
01034    %<bitfield>W         print (bitfield * 4) as a decimal
01035    %<bitfield>a         print (bitfield * 4) as a pc-rel offset + decoded symbol
01036    %<bitfield>B         print Thumb branch destination (signed displacement)
01037    %<bitfield>c         print bitfield as a condition code
01038    %<bitnum>'c              print specified char iff bit is one
01039    %<bitnum>?ab             print a if bit is one else print b.  */
01040 
01041 static const struct opcode16 thumb_opcodes[] =
01042 {
01043   /* Thumb instructions.  */
01044 
01045   /* ARM V6K no-argument instructions.  */
01046   {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
01047   {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
01048   {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
01049   {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
01050   {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
01051   {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
01052 
01053   /* ARM V6T2 instructions.  */
01054   {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
01055   {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
01056   {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
01057 
01058   /* ARM V6.  */
01059   {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
01060   {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
01061   {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
01062   {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
01063   {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
01064   {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
01065   {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
01066   {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
01067   {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
01068   {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
01069   {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
01070 
01071   /* ARM V5 ISA extends Thumb.  */
01072   {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional.  */
01073   /* This is BLX(2).  BLX(1) is a 32-bit instruction.  */
01074   {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"},      /* note: 4 bit register number.  */
01075   /* ARM V4T ISA (Thumb v1).  */
01076   {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"},
01077   /* Format 4.  */
01078   {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
01079   {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
01080   {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
01081   {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
01082   {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
01083   {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
01084   {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
01085   {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
01086   {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
01087   {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
01088   {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
01089   {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
01090   {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
01091   {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
01092   {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
01093   {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
01094   /* format 13 */
01095   {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
01096   {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
01097   /* format 5 */
01098   {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
01099   {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
01100   {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
01101   {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
01102   /* format 14 */
01103   {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
01104   {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
01105   /* format 2 */
01106   {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
01107   {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
01108   {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
01109   {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
01110   /* format 8 */
01111   {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
01112   {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
01113   {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
01114   /* format 7 */
01115   {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
01116   {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
01117   /* format 1 */
01118   {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
01119   {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
01120   {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
01121   /* format 3 */
01122   {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
01123   {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
01124   {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
01125   {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
01126   /* format 6 */
01127   {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"},  /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
01128   /* format 9 */
01129   {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
01130   {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
01131   {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
01132   {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
01133   /* format 10 */
01134   {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
01135   {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
01136   /* format 11 */
01137   {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
01138   {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
01139   /* format 12 */
01140   {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r,%0-7a)"},
01141   {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
01142   /* format 15 */
01143   {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
01144   {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"},
01145   /* format 17 */
01146   {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
01147   /* format 16 */
01148   {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"},
01149   {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
01150   /* format 18 */
01151   {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
01152 
01153   /* The E800 .. FFFF range is unconditionally redirected to the
01154      32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
01155      are processed via that table.  Thus, we can never encounter a
01156      bare "second half of BL/BLX(1)" instruction here.  */
01157   {ARM_EXT_V1,  0x0000, 0x0000, "undefined"},
01158   {0, 0, 0, 0}
01159 };
01160 
01161 /* Thumb32 opcodes use the same table structure as the ARM opcodes.
01162    We adopt the convention that hw1 is the high 16 bits of .value and
01163    .mask, hw2 the low 16 bits.
01164 
01165    print_insn_thumb32 recognizes the following format control codes:
01166 
01167        %%            %
01168 
01169        %I            print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
01170        %M            print a modified 12-bit immediate (same location)
01171        %J            print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
01172        %K            print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
01173        %S            print a possibly-shifted Rm
01174 
01175        %a            print the address of a plain load/store
01176        %w            print the width and signedness of a core load/store
01177        %m            print register mask for ldm/stm
01178 
01179        %E            print the lsb and width fields of a bfc/bfi instruction
01180        %F            print the lsb and width fields of a sbfx/ubfx instruction
01181        %b            print a conditional branch offset
01182        %B            print an unconditional branch offset
01183        %s            print the shift field of an SSAT instruction
01184        %R            print the rotation field of an SXT instruction
01185        %U            print barrier type.
01186        %P            print address for pli instruction.
01187        %c            print the condition code
01188        %x            print warning if conditional an not at end of IT block"
01189        %X            print "\t; unpredictable <IT:code>" if conditional
01190 
01191        %<bitfield>d  print bitfield in decimal
01192        %<bitfield>W  print bitfield*4 in decimal
01193        %<bitfield>r  print bitfield as an ARM register
01194        %<bitfield>c  print bitfield as a condition code
01195 
01196        %<bitfield>'c print specified char iff bitfield is all ones
01197        %<bitfield>`c print specified char iff bitfield is all zeroes
01198        %<bitfield>?ab... select from array of values in big endian order
01199 
01200    With one exception at the bottom (done because BL and BLX(1) need
01201    to come dead last), this table was machine-sorted first in
01202    decreasing order of number of bits set in the mask, then in
01203    increasing numeric order of mask, then in increasing numeric order
01204    of opcode.  This order is not the clearest for a human reader, but
01205    is guaranteed never to catch a special-case bit pattern with a more
01206    general mask, which is important, because this instruction encoding
01207    makes heavy use of special-case bit patterns.  */
01208 static const struct opcode32 thumb32_opcodes[] =
01209 {
01210   /* V7 instructions.  */
01211   {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
01212   {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
01213   {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
01214   {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
01215   {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
01216   {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
01217   {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
01218 
01219   /* Instructions defined in the basic V6T2 set.  */
01220   {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
01221   {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
01222   {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
01223   {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
01224   {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"},
01225   {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
01226 
01227   {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
01228   {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
01229   {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
01230   {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
01231   {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
01232   {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
01233   {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"},
01234   {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
01235   {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
01236   {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
01237   {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
01238   {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
01239   {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
01240   {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
01241   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
01242   {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
01243   {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
01244   {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
01245   {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
01246   {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
01247   {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
01248   {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
01249   {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
01250   {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
01251   {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
01252   {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
01253   {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
01254   {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
01255   {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
01256   {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
01257   {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
01258   {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
01259   {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
01260   {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
01261   {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
01262   {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
01263   {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
01264   {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
01265   {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
01266   {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
01267   {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
01268   {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
01269   {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
01270   {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
01271   {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
01272   {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
01273   {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"},
01274   {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"},
01275   {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"},
01276   {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"},
01277   {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"},
01278   {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"},
01279   {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
01280   {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
01281   {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
01282   {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
01283   {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
01284   {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
01285   {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
01286   {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
01287   {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
01288   {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
01289   {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
01290   {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
01291   {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
01292   {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
01293   {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"},
01294   {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"},
01295   {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"},
01296   {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"},
01297   {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"},
01298   {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"},
01299   {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
01300   {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
01301   {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"},
01302   {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
01303   {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"},
01304   {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
01305   {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
01306   {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
01307   {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
01308   {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
01309   {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
01310   {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
01311   {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
01312   {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
01313   {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
01314   {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
01315   {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
01316   {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
01317   {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
01318   {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
01319   {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
01320   {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
01321   {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
01322   {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
01323   {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
01324   {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
01325   {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
01326   {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
01327   {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
01328   {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
01329   {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
01330   {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
01331   {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01332   {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01333   {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01334   {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01335   {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01336   {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01337   {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01338   {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01339   {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
01340   {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
01341   {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
01342   {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
01343   {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
01344   {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01345   {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01346   {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01347   {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01348   {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01349   {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01350   {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01351   {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
01352   {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
01353   {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
01354   {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
01355   {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
01356   {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
01357   {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
01358   {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
01359   {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
01360   {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
01361   {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
01362   {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
01363   {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
01364   {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
01365   {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
01366   {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
01367   {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
01368   {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
01369   {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
01370   {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
01371   {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
01372   {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
01373   {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
01374   {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
01375   {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
01376   {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
01377   {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
01378   {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
01379   {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
01380   {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
01381   {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
01382   {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
01383   {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
01384   {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
01385   {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
01386   {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
01387   {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
01388   {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
01389   {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
01390   {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
01391   {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
01392   {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
01393   {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
01394   {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]"},
01395   {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
01396   {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
01397 
01398   /* Filter out Bcc with cond=E or F, which are used for other instructions.  */
01399   {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
01400   {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
01401   {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
01402   {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
01403 
01404   /* These have been 32-bit since the invention of Thumb.  */
01405   {ARM_EXT_V4T,  0xf000c000, 0xf800d000, "blx%c\t%B%x"},
01406   {ARM_EXT_V4T,  0xf000d000, 0xf800d000, "bl%c\t%B%x"},
01407 
01408   /* Fallback.  */
01409   {ARM_EXT_V1,   0x00000000, 0x00000000, "undefined"},
01410   {0, 0, 0, 0}
01411 };
01412    
01413 static const char *const arm_conditional[] =
01414 {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
01415  "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
01416 
01417 static const char *const arm_fp_const[] =
01418 {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
01419 
01420 static const char *const arm_shift[] =
01421 {"lsl", "lsr", "asr", "ror"};
01422 
01423 typedef struct
01424 {
01425   const char *name;
01426   const char *description;
01427   const char *reg_names[16];
01428 }
01429 arm_regname;
01430 
01431 static const arm_regname regnames[] =
01432 {
01433   { "raw" , "Select raw register names",
01434     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
01435   { "gcc",  "Select register names used by GCC",
01436     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
01437   { "std",  "Select register names used in ARM's ISA documentation",
01438     { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp",  "lr",  "pc" }},
01439   { "apcs", "Select register names used in the APCS",
01440     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl",  "fp",  "ip",  "sp",  "lr",  "pc" }},
01441   { "atpcs", "Select register names used in the ATPCS",
01442     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7",  "v8",  "IP",  "SP",  "LR",  "PC" }},
01443   { "special-atpcs", "Select special register names used in the ATPCS",
01444     { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL",  "FP",  "IP",  "SP",  "LR",  "PC" }},
01445 };
01446 
01447 static const char *const iwmmxt_wwnames[] =
01448 {"b", "h", "w", "d"};
01449 
01450 static const char *const iwmmxt_wwssnames[] =
01451 {"b", "bus", "bc", "bss",
01452  "h", "hus", "hc", "hss",
01453  "w", "wus", "wc", "wss",
01454  "d", "dus", "dc", "dss"
01455 };
01456 
01457 static const char *const iwmmxt_regnames[] =
01458 { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
01459   "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
01460 };
01461 
01462 static const char *const iwmmxt_cregnames[] =
01463 { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
01464   "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
01465 };
01466 
01467 /* Default to GCC register name set.  */
01468 static unsigned int regname_selected = 1;
01469 
01470 #define NUM_ARM_REGNAMES  NUM_ELEM (regnames)
01471 #define arm_regnames      regnames[regname_selected].reg_names
01472 
01473 static bfd_boolean force_thumb = FALSE;
01474 
01475 /* Current IT instruction state.  This contains the same state as the IT
01476    bits in the CPSR.  */
01477 static unsigned int ifthen_state;
01478 /* IT state for the next instruction.  */
01479 static unsigned int ifthen_next_state;
01480 /* The address of the insn for which the IT state is valid.  */
01481 static bfd_vma ifthen_address;
01482 #define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
01483 
01484 /* Cached mapping symbol state.  */
01485 enum map_type {
01486   MAP_ARM,
01487   MAP_THUMB,
01488   MAP_DATA
01489 };
01490 
01491 enum map_type last_type;
01492 int last_mapping_sym = -1;
01493 bfd_vma last_mapping_addr = 0;
01494 
01495 
01496 /* Functions.  */
01497 int
01498 get_arm_regname_num_options (void)
01499 {
01500   return NUM_ARM_REGNAMES;
01501 }
01502 
01503 int
01504 set_arm_regname_option (int option)
01505 {
01506   int old = regname_selected;
01507   regname_selected = option;
01508   return old;
01509 }
01510 
01511 int
01512 get_arm_regnames (int option, const char **setname, const char **setdescription,
01513                 const char *const **register_names)
01514 {
01515   *setname = regnames[option].name;
01516   *setdescription = regnames[option].description;
01517   *register_names = regnames[option].reg_names;
01518   return 16;
01519 }
01520 
01521 /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
01522    Returns pointer to following character of the format string and
01523    fills in *VALUEP and *WIDTHP with the extracted value and number of
01524    bits extracted.  WIDTHP can be NULL. */
01525 
01526 static const char *
01527 arm_decode_bitfield (const char *ptr, unsigned long insn,
01528                    unsigned long *valuep, int *widthp)
01529 {
01530   unsigned long value = 0;
01531   int width = 0;
01532   
01533   do 
01534     {
01535       int start, end;
01536       int bits;
01537 
01538       for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
01539        start = start * 10 + *ptr - '0';
01540       if (*ptr == '-')
01541        for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
01542          end = end * 10 + *ptr - '0';
01543       else
01544        end = start;
01545       bits = end - start;
01546       if (bits < 0)
01547        abort ();
01548       value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
01549       width += bits + 1;
01550     }
01551   while (*ptr++ == ',');
01552   *valuep = value;
01553   if (widthp)
01554     *widthp = width;
01555   return ptr - 1;
01556 }
01557 
01558 static void
01559 arm_decode_shift (long given, fprintf_ftype func, void *stream)
01560 {
01561   func (stream, "%s", arm_regnames[given & 0xf]);
01562 
01563   if ((given & 0xff0) != 0)
01564     {
01565       if ((given & 0x10) == 0)
01566        {
01567          int amount = (given & 0xf80) >> 7;
01568          int shift = (given & 0x60) >> 5;
01569 
01570          if (amount == 0)
01571            {
01572              if (shift == 3)
01573               {
01574                 func (stream, ", rrx");
01575                 return;
01576               }
01577 
01578              amount = 32;
01579            }
01580 
01581          func (stream, ", %s #%d", arm_shift[shift], amount);
01582        }
01583       else
01584        func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
01585              arm_regnames[(given & 0xf00) >> 8]);
01586     }
01587 }
01588 
01589 /* Print one coprocessor instruction on INFO->STREAM.
01590    Return TRUE if the instuction matched, FALSE if this is not a
01591    recognised coprocessor instruction.  */
01592 
01593 static bfd_boolean
01594 print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given,
01595                      bfd_boolean thumb)
01596 {
01597   const struct opcode32 *insn;
01598   void *stream = info->stream;
01599   fprintf_ftype func = info->fprintf_func;
01600   unsigned long mask;
01601   unsigned long value;
01602   int cond;
01603 
01604   for (insn = coprocessor_opcodes; insn->assembler; insn++)
01605     {
01606       if (insn->value == FIRST_IWMMXT_INSN
01607          && info->mach != bfd_mach_arm_XScale
01608          && info->mach != bfd_mach_arm_iWMMXt
01609          && info->mach != bfd_mach_arm_iWMMXt2)
01610        insn = insn + IWMMXT_INSN_COUNT;
01611 
01612       mask = insn->mask;
01613       value = insn->value;
01614       if (thumb)
01615        {
01616          /* The high 4 bits are 0xe for Arm conditional instructions, and
01617             0xe for arm unconditional instructions.  The rest of the
01618             encoding is the same.  */
01619          mask |= 0xf0000000;
01620          value |= 0xe0000000;
01621          if (ifthen_state)
01622            cond = IFTHEN_COND;
01623          else
01624            cond = 16;
01625        }
01626       else
01627        {
01628          /* Only match unconditional instuctions against unconditional
01629             patterns.  */
01630          if ((given & 0xf0000000) == 0xf0000000)
01631            {
01632              mask |= 0xf0000000;
01633              cond = 16;
01634            }
01635          else
01636            {
01637              cond = (given >> 28) & 0xf;
01638              if (cond == 0xe)
01639               cond = 16;
01640            }
01641        }
01642       if ((given & mask) == value)
01643        {
01644          const char *c;
01645 
01646          for (c = insn->assembler; *c; c++)
01647            {
01648              if (*c == '%')
01649               {
01650                 switch (*++c)
01651                   {
01652                   case '%':
01653                     func (stream, "%%");
01654                     break;
01655 
01656                   case 'A':
01657                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
01658 
01659                     if ((given & (1 << 24)) != 0)
01660                      {
01661                        int offset = given & 0xff;
01662 
01663                        if (offset)
01664                          func (stream, ", #%s%d]%s",
01665                               ((given & 0x00800000) == 0 ? "-" : ""),
01666                               offset * 4,
01667                               ((given & 0x00200000) != 0 ? "!" : ""));
01668                        else
01669                          func (stream, "]");
01670                      }
01671                     else
01672                      {
01673                        int offset = given & 0xff;
01674 
01675                        func (stream, "]");
01676 
01677                        if (given & (1 << 21))
01678                          {
01679                            if (offset)
01680                             func (stream, ", #%s%d",
01681                                   ((given & 0x00800000) == 0 ? "-" : ""),
01682                                   offset * 4);
01683                          }
01684                        else
01685                          func (stream, ", {%d}", offset);
01686                      }
01687                     break;
01688 
01689                   case 'B':
01690                     {
01691                      int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
01692                      int offset = (given >> 1) & 0x3f;
01693                      
01694                      if (offset == 1)
01695                        func (stream, "{d%d}", regno);
01696                      else if (regno + offset > 32)
01697                        func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
01698                      else
01699                        func (stream, "{d%d-d%d}", regno, regno + offset - 1);
01700                     }
01701                     break;
01702                     
01703                   case 'C':
01704                     {
01705                      int rn = (given >> 16) & 0xf;
01706                      int offset = (given & 0xff) * 4;
01707                      int add = (given >> 23) & 1;
01708                      
01709                      func (stream, "[%s", arm_regnames[rn]);
01710                      
01711                      if (offset)
01712                        {
01713                          if (!add)
01714                            offset = -offset;
01715                          func (stream, ", #%d", offset);
01716                        }
01717                      func (stream, "]");
01718                      if (rn == 15)
01719                        {
01720                          func (stream, "\t; ");
01721                             /* FIXME: Unsure if info->bytes_per_chunk is the
01722                                right thing to use here.  */
01723                          info->print_address_func (offset + pc
01724                               + info->bytes_per_chunk * 2, info);
01725                        }
01726                     }
01727                     break;
01728 
01729                   case 'c':
01730                     func (stream, "%s", arm_conditional[cond]);
01731                     break;
01732 
01733                   case 'I':
01734                     /* Print a Cirrus/DSP shift immediate.  */
01735                     /* Immediates are 7bit signed ints with bits 0..3 in
01736                       bits 0..3 of opcode and bits 4..6 in bits 5..7
01737                       of opcode.  */
01738                     {
01739                      int imm;
01740 
01741                      imm = (given & 0xf) | ((given & 0xe0) >> 1);
01742 
01743                      /* Is ``imm'' a negative number?  */
01744                      if (imm & 0x40)
01745                        imm |= (-1 << 7);
01746 
01747                      func (stream, "%d", imm);
01748                     }
01749 
01750                     break;
01751 
01752                   case 'F':
01753                     switch (given & 0x00408000)
01754                      {
01755                      case 0:
01756                        func (stream, "4");
01757                        break;
01758                      case 0x8000:
01759                        func (stream, "1");
01760                        break;
01761                      case 0x00400000:
01762                        func (stream, "2");
01763                        break;
01764                      default:
01765                        func (stream, "3");
01766                      }
01767                     break;
01768 
01769                   case 'P':
01770                     switch (given & 0x00080080)
01771                      {
01772                      case 0:
01773                        func (stream, "s");
01774                        break;
01775                      case 0x80:
01776                        func (stream, "d");
01777                        break;
01778                      case 0x00080000:
01779                        func (stream, "e");
01780                        break;
01781                      default:
01782                        func (stream, _("<illegal precision>"));
01783                        break;
01784                      }
01785                     break;
01786                   case 'Q':
01787                     switch (given & 0x00408000)
01788                      {
01789                      case 0:
01790                        func (stream, "s");
01791                        break;
01792                      case 0x8000:
01793                        func (stream, "d");
01794                        break;
01795                      case 0x00400000:
01796                        func (stream, "e");
01797                        break;
01798                      default:
01799                        func (stream, "p");
01800                        break;
01801                      }
01802                     break;
01803                   case 'R':
01804                     switch (given & 0x60)
01805                      {
01806                      case 0:
01807                        break;
01808                      case 0x20:
01809                        func (stream, "p");
01810                        break;
01811                      case 0x40:
01812                        func (stream, "m");
01813                        break;
01814                      default:
01815                        func (stream, "z");
01816                        break;
01817                      }
01818                     break;
01819 
01820                   case '0': case '1': case '2': case '3': case '4':
01821                   case '5': case '6': case '7': case '8': case '9':
01822                     {
01823                      int width;
01824                      unsigned long value;
01825 
01826                      c = arm_decode_bitfield (c, given, &value, &width);
01827 
01828                      switch (*c)
01829                        {
01830                        case 'r':
01831                          func (stream, "%s", arm_regnames[value]);
01832                          break;
01833                        case 'D':
01834                          func (stream, "d%ld", value);
01835                          break;
01836                        case 'Q':
01837                          if (value & 1)
01838                            func (stream, "<illegal reg q%ld.5>", value >> 1);
01839                          else
01840                            func (stream, "q%ld", value >> 1);
01841                          break;
01842                        case 'd':
01843                          func (stream, "%ld", value);
01844                          break;
01845                           case 'k':
01846                             {
01847                               int from = (given & (1 << 7)) ? 32 : 16;
01848                               func (stream, "%ld", from - value);
01849                             }
01850                             break;
01851                             
01852                        case 'f':
01853                          if (value > 7)
01854                            func (stream, "#%s", arm_fp_const[value & 7]);
01855                          else
01856                            func (stream, "f%ld", value);
01857                          break;
01858 
01859                        case 'w':
01860                          if (width == 2)
01861                            func (stream, "%s", iwmmxt_wwnames[value]);
01862                          else
01863                            func (stream, "%s", iwmmxt_wwssnames[value]);
01864                          break;
01865 
01866                        case 'g':
01867                          func (stream, "%s", iwmmxt_regnames[value]);
01868                          break;
01869                        case 'G':
01870                          func (stream, "%s", iwmmxt_cregnames[value]);
01871                          break;
01872 
01873                        case 'x':
01874                          func (stream, "0x%lx", value);
01875                          break;
01876 
01877                        case '`':
01878                          c++;
01879                          if (value == 0)
01880                            func (stream, "%c", *c);
01881                          break;
01882                        case '\'':
01883                          c++;
01884                          if (value == ((1ul << width) - 1))
01885                            func (stream, "%c", *c);
01886                          break;
01887                        case '?':
01888                          func (stream, "%c", c[(1 << width) - (int)value]);
01889                          c += 1 << width;
01890                          break;
01891                        default:
01892                          abort ();
01893                        }
01894                      break;
01895 
01896                     case 'y':
01897                     case 'z':
01898                      {
01899                        int single = *c++ == 'y';
01900                        int regno;
01901                        
01902                        switch (*c)
01903                          {
01904                          case '4': /* Sm pair */
01905                            func (stream, "{");
01906                            /* Fall through.  */
01907                          case '0': /* Sm, Dm */
01908                            regno = given & 0x0000000f;
01909                            if (single)
01910                             {
01911                               regno <<= 1;
01912                               regno += (given >> 5) & 1;
01913                             }
01914                               else
01915                                 regno += ((given >> 5) & 1) << 4;
01916                            break;
01917 
01918                          case '1': /* Sd, Dd */
01919                            regno = (given >> 12) & 0x0000000f;
01920                            if (single)
01921                             {
01922                               regno <<= 1;
01923                               regno += (given >> 22) & 1;
01924                             }
01925                               else
01926                                 regno += ((given >> 22) & 1) << 4;
01927                            break;
01928 
01929                          case '2': /* Sn, Dn */
01930                            regno = (given >> 16) & 0x0000000f;
01931                            if (single)
01932                             {
01933                               regno <<= 1;
01934                               regno += (given >> 7) & 1;
01935                             }
01936                               else
01937                                 regno += ((given >> 7) & 1) << 4;
01938                            break;
01939                            
01940                          case '3': /* List */
01941                            func (stream, "{");
01942                            regno = (given >> 12) & 0x0000000f;
01943                            if (single)
01944                             {
01945                               regno <<= 1;
01946                               regno += (given >> 22) & 1;
01947                             }
01948                               else
01949                                 regno += ((given >> 22) & 1) << 4;
01950                            break;
01951                            
01952                          default:
01953                            abort ();
01954                          }
01955 
01956                        func (stream, "%c%d", single ? 's' : 'd', regno);
01957 
01958                        if (*c == '3')
01959                          {
01960                            int count = given & 0xff;
01961                            
01962                            if (single == 0)
01963                             count >>= 1;
01964                            
01965                            if (--count)
01966                             {
01967                               func (stream, "-%c%d",
01968                                    single ? 's' : 'd',
01969                                    regno + count);
01970                             }
01971                            
01972                            func (stream, "}");
01973                          }
01974                        else if (*c == '4')
01975                          func (stream, ", %c%d}", single ? 's' : 'd',
01976                               regno + 1);
01977                      }
01978                      break;
01979                          
01980                     case 'L':
01981                      switch (given & 0x00400100)
01982                        {
01983                        case 0x00000000: func (stream, "b"); break;
01984                        case 0x00400000: func (stream, "h"); break;
01985                        case 0x00000100: func (stream, "w"); break;
01986                        case 0x00400100: func (stream, "d"); break;
01987                        default:
01988                          break;
01989                        }
01990                      break;
01991 
01992                     case 'Z':
01993                      {
01994                        int value;
01995                        /* given (20, 23) | given (0, 3) */
01996                        value = ((given >> 16) & 0xf0) | (given & 0xf);
01997                        func (stream, "%d", value);
01998                      }
01999                      break;
02000 
02001                     case 'l':
02002                      /* This is like the 'A' operator, except that if
02003                         the width field "M" is zero, then the offset is
02004                         *not* multiplied by four.  */
02005                      {
02006                        int offset = given & 0xff;
02007                        int multiplier = (given & 0x00000100) ? 4 : 1;
02008 
02009                        func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
02010 
02011                        if (offset)
02012                          {
02013                            if ((given & 0x01000000) != 0)
02014                             func (stream, ", #%s%d]%s",
02015                                   ((given & 0x00800000) == 0 ? "-" : ""),
02016                                   offset * multiplier,
02017                                   ((given & 0x00200000) != 0 ? "!" : ""));
02018                            else
02019                             func (stream, "], #%s%d",
02020                                   ((given & 0x00800000) == 0 ? "-" : ""),
02021                                   offset * multiplier);
02022                          }
02023                        else
02024                          func (stream, "]");
02025                      }
02026                      break;
02027 
02028                     case 'r':
02029                      {
02030                        int imm4 = (given >> 4) & 0xf;
02031                        int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1);
02032                        int ubit = (given >> 23) & 1;
02033                        const char *rm = arm_regnames [given & 0xf];
02034                        const char *rn = arm_regnames [(given >> 16) & 0xf];
02035 
02036                        switch (puw_bits)
02037                          {
02038                          case 1:
02039                            /* fall through */
02040                          case 3:
02041                            func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
02042                            if (imm4)
02043                             func (stream, ", lsl #%d", imm4);
02044                            break;
02045 
02046                          case 4:
02047                            /* fall through */
02048                          case 5:
02049                            /* fall through */
02050                          case 6:
02051                            /* fall through */
02052                          case 7:
02053                            func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
02054                            if (imm4 > 0)
02055                             func (stream, ", lsl #%d", imm4);
02056                            func (stream, "]");
02057                            if (puw_bits == 5 || puw_bits == 7)
02058                             func (stream, "!");
02059                            break;
02060 
02061                          default:
02062                            func (stream, "INVALID");
02063                          }
02064                      }
02065                      break;
02066 
02067                     case 'i':
02068                      {
02069                        long imm5;
02070                        imm5 = ((given & 0x100) >> 4) | (given & 0xf);
02071                        func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
02072                      }
02073                      break;
02074 
02075                     default:
02076                      abort ();
02077                     }
02078                   }
02079               }
02080              else
02081               func (stream, "%c", *c);
02082            }
02083          return TRUE;
02084        }
02085     }
02086   return FALSE;
02087 }
02088 
02089 static void
02090 print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
02091 {
02092   void *stream = info->stream;
02093   fprintf_ftype func = info->fprintf_func;
02094 
02095   if (((given & 0x000f0000) == 0x000f0000)
02096       && ((given & 0x02000000) == 0))
02097     {
02098       int offset = given & 0xfff;
02099 
02100       func (stream, "[pc");
02101 
02102       if (given & 0x01000000)
02103        {
02104          if ((given & 0x00800000) == 0)
02105            offset = - offset;
02106 
02107          /* Pre-indexed.  */
02108          func (stream, ", #%d]", offset);
02109 
02110          offset += pc + 8;
02111 
02112          /* Cope with the possibility of write-back
02113             being used.  Probably a very dangerous thing
02114             for the programmer to do, but who are we to
02115             argue ?  */
02116          if (given & 0x00200000)
02117            func (stream, "!");
02118        }
02119       else
02120        {
02121          /* Post indexed.  */
02122          func (stream, "], #%d", offset);
02123 
02124          /* ie ignore the offset.  */
02125          offset = pc + 8;
02126        }
02127 
02128       func (stream, "\t; ");
02129       info->print_address_func (offset, info);
02130     }
02131   else
02132     {
02133       func (stream, "[%s",
02134            arm_regnames[(given >> 16) & 0xf]);
02135       if ((given & 0x01000000) != 0)
02136        {
02137          if ((given & 0x02000000) == 0)
02138            {
02139              int offset = given & 0xfff;
02140              if (offset)
02141               func (stream, ", #%s%d",
02142                     (((given & 0x00800000) == 0)
02143                      ? "-" : ""), offset);
02144            }
02145          else
02146            {
02147              func (stream, ", %s",
02148                   (((given & 0x00800000) == 0)
02149                    ? "-" : ""));
02150              arm_decode_shift (given, func, stream);
02151            }
02152 
02153          func (stream, "]%s",
02154               ((given & 0x00200000) != 0) ? "!" : "");
02155        }
02156       else
02157        {
02158          if ((given & 0x02000000) == 0)
02159            {
02160              int offset = given & 0xfff;
02161              if (offset)
02162               func (stream, "], #%s%d",
02163                     (((given & 0x00800000) == 0)
02164                      ? "-" : ""), offset);
02165              else
02166               func (stream, "]");
02167            }
02168          else
02169            {
02170              func (stream, "], %s",
02171                   (((given & 0x00800000) == 0)
02172                    ? "-" : ""));
02173              arm_decode_shift (given, func, stream);
02174            }
02175        }
02176     }
02177 }
02178 
02179 /* Print one neon instruction on INFO->STREAM.
02180    Return TRUE if the instuction matched, FALSE if this is not a
02181    recognised neon instruction.  */
02182 
02183 static bfd_boolean
02184 print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
02185 {
02186   const struct opcode32 *insn;
02187   void *stream = info->stream;
02188   fprintf_ftype func = info->fprintf_func;
02189 
02190   if (thumb)
02191     {
02192       if ((given & 0xef000000) == 0xef000000)
02193        {
02194          /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding.  */
02195          unsigned long bit28 = given & (1 << 28);
02196 
02197          given &= 0x00ffffff;
02198          if (bit28)
02199             given |= 0xf3000000;
02200           else
02201            given |= 0xf2000000;
02202        }
02203       else if ((given & 0xff000000) == 0xf9000000)
02204        given ^= 0xf9000000 ^ 0xf4000000;
02205       else
02206        return FALSE;
02207     }
02208   
02209   for (insn = neon_opcodes; insn->assembler; insn++)
02210     {
02211       if ((given & insn->mask) == insn->value)
02212        {
02213          const char *c;
02214 
02215          for (c = insn->assembler; *c; c++)
02216            {
02217              if (*c == '%')
02218               {
02219                 switch (*++c)
02220                   {
02221                   case '%':
02222                     func (stream, "%%");
02223                     break;
02224 
02225                   case 'c':
02226                     if (thumb && ifthen_state)
02227                      func (stream, "%s", arm_conditional[IFTHEN_COND]);
02228                     break;
02229 
02230                   case 'A':
02231                     {
02232                      static const unsigned char enc[16] = 
02233                      {
02234                        0x4, 0x14, /* st4 0,1 */
02235                        0x4, /* st1 2 */
02236                        0x4, /* st2 3 */
02237                        0x3, /* st3 4 */
02238                        0x13, /* st3 5 */
02239                        0x3, /* st1 6 */
02240                        0x1, /* st1 7 */
02241                        0x2, /* st2 8 */
02242                        0x12, /* st2 9 */
02243                        0x2, /* st1 10 */
02244                        0, 0, 0, 0, 0
02245                      };
02246                      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
02247                      int rn = ((given >> 16) & 0xf);
02248                      int rm = ((given >> 0) & 0xf);
02249                      int align = ((given >> 4) & 0x3);
02250                      int type = ((given >> 8) & 0xf);
02251                      int n = enc[type] & 0xf;
02252                      int stride = (enc[type] >> 4) + 1;
02253                      int ix;
02254                      
02255                      func (stream, "{");
02256                      if (stride > 1)
02257                        for (ix = 0; ix != n; ix++)
02258                          func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
02259                      else if (n == 1)
02260                        func (stream, "d%d", rd);
02261                      else
02262                        func (stream, "d%d-d%d", rd, rd + n - 1);
02263                      func (stream, "}, [%s", arm_regnames[rn]);
02264                      if (align)
02265                        func (stream, ", :%d", 32 << align);
02266                      func (stream, "]");
02267                      if (rm == 0xd)
02268                        func (stream, "!");
02269                      else if (rm != 0xf)
02270                        func (stream, ", %s", arm_regnames[rm]);
02271                     }
02272                     break;
02273                     
02274                   case 'B':
02275                     {
02276                      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
02277                      int rn = ((given >> 16) & 0xf);
02278                      int rm = ((given >> 0) & 0xf);
02279                      int idx_align = ((given >> 4) & 0xf);
02280                         int align = 0;
02281                      int size = ((given >> 10) & 0x3);
02282                      int idx = idx_align >> (size + 1);
02283                         int length = ((given >> 8) & 3) + 1;
02284                         int stride = 1;
02285                         int i;
02286 
02287                         if (length > 1 && size > 0)
02288                           stride = (idx_align & (1 << size)) ? 2 : 1;
02289                      
02290                         switch (length)
02291                           {
02292                           case 1:
02293                             {
02294                               int amask = (1 << size) - 1;
02295                               if ((idx_align & (1 << size)) != 0)
02296                                 return FALSE;
02297                               if (size > 0)
02298                                 {
02299                                   if ((idx_align & amask) == amask)
02300                                     align = 8 << size;
02301                                   else if ((idx_align & amask) != 0)
02302                                     return FALSE;
02303                                 }
02304                               }
02305                             break;
02306                           
02307                           case 2:
02308                             if (size == 2 && (idx_align & 2) != 0)
02309                               return FALSE;
02310                             align = (idx_align & 1) ? 16 << size : 0;
02311                             break;
02312                           
02313                           case 3:
02314                             if ((size == 2 && (idx_align & 3) != 0)
02315                                 || (idx_align & 1) != 0)
02316                               return FALSE;
02317                             break;
02318                           
02319                           case 4:
02320                             if (size == 2)
02321                               {
02322                                 if ((idx_align & 3) == 3)
02323                                   return FALSE;
02324                                 align = (idx_align & 3) * 64;
02325                               }
02326                             else
02327                               align = (idx_align & 1) ? 32 << size : 0;
02328                             break;
02329                           
02330                           default:
02331                             abort ();
02332                           }
02333                                 
02334                      func (stream, "{");
02335                         for (i = 0; i < length; i++)
02336                           func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
02337                             rd + i * stride, idx);
02338                         func (stream, "}, [%s", arm_regnames[rn]);
02339                      if (align)
02340                        func (stream, ", :%d", align);
02341                      func (stream, "]");
02342                      if (rm == 0xd)
02343                        func (stream, "!");
02344                      else if (rm != 0xf)
02345                        func (stream, ", %s", arm_regnames[rm]);
02346                     }
02347                     break;
02348                     
02349                   case 'C':
02350                     {
02351                      int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
02352                      int rn = ((given >> 16) & 0xf);
02353                      int rm = ((given >> 0) & 0xf);
02354                      int align = ((given >> 4) & 0x1);
02355                      int size = ((given >> 6) & 0x3);
02356                      int type = ((given >> 8) & 0x3);
02357                      int n = type + 1;
02358                      int stride = ((given >> 5) & 0x1);
02359                      int ix;
02360                      
02361                      if (stride && (n == 1))
02362                        n++;
02363                      else
02364                        stride++;
02365                      
02366                      func (stream, "{");
02367                      if (stride > 1)
02368                        for (ix = 0; ix != n; ix++)
02369                          func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
02370                      else if (n == 1)
02371                        func (stream, "d%d[]", rd);
02372                      else
02373                        func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
02374                      func (stream, "}, [%s", arm_regnames[rn]);
02375                      if (align)
02376                        {
02377                             int align = (8 * (type + 1)) << size;
02378                             if (type == 3)
02379                               align = (size > 1) ? align >> 1 : align;
02380                          if (type == 2 || (type == 0 && !size))
02381                            func (stream, ", :<bad align %d>", align);
02382                          else
02383                            func (stream, ", :%d", align);
02384                        }
02385                      func (stream, "]");
02386                      if (rm == 0xd)
02387                        func (stream, "!");
02388                      else if (rm != 0xf)
02389                        func (stream, ", %s", arm_regnames[rm]);
02390                     }
02391                     break;
02392                     
02393                   case 'D':
02394                     {
02395                      int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
02396                      int size = (given >> 20) & 3;
02397                      int reg = raw_reg & ((4 << size) - 1);
02398                      int ix = raw_reg >> size >> 2;
02399                      
02400                      func (stream, "d%d[%d]", reg, ix);
02401                     }
02402                     break;
02403                     
02404                   case 'E':
02405                     /* Neon encoded constant for mov, mvn, vorr, vbic */
02406                     {
02407                      int bits = 0;
02408                      int cmode = (given >> 8) & 0xf;
02409                      int op = (given >> 5) & 0x1;
02410                      unsigned long value = 0, hival = 0;
02411                      unsigned shift;
02412                         int size = 0;
02413                         int isfloat = 0;
02414                      
02415                      bits |= ((given >> 24) & 1) << 7;
02416                      bits |= ((given >> 16) & 7) << 4;
02417                      bits |= ((given >> 0) & 15) << 0;
02418                      
02419                      if (cmode < 8)
02420                        {
02421                          shift = (cmode >> 1) & 3;
02422                          value = (unsigned long)bits << (8 * shift);
02423                             size = 32;
02424                        }
02425                      else if (cmode < 12)
02426                        {
02427                          shift = (cmode >> 1) & 1;
02428                          value = (unsigned long)bits << (8 * shift);
02429                             size = 16;
02430                        }
02431                      else if (cmode < 14)
02432                        {
02433                          shift = (cmode & 1) + 1;
02434                          value = (unsigned long)bits << (8 * shift);
02435                          value |= (1ul << (8 * shift)) - 1;
02436                             size = 32;
02437                        }
02438                      else if (cmode == 14)
02439                        {
02440                          if (op)
02441                            {
02442                             /* bit replication into bytes */
02443                             int ix;
02444                             unsigned long mask;
02445                             
02446                             value = 0;
02447                                 hival = 0;
02448                             for (ix = 7; ix >= 0; ix--)
02449                               {
02450                                 mask = ((bits >> ix) & 1) ? 0xff : 0;
02451                                     if (ix <= 3)
02452                                   value = (value << 8) | mask;
02453                                     else
02454                                       hival = (hival << 8) | mask;
02455                               }
02456                                 size = 64;
02457                            }
02458                             else
02459                               {
02460                                 /* byte replication */
02461                                 value = (unsigned long)bits;
02462                                 size = 8;
02463                               }
02464                        }
02465                      else if (!op)
02466                        {
02467                          /* floating point encoding */
02468                          int tmp;
02469                          
02470                          value = (unsigned long)(bits & 0x7f) << 19;
02471                          value |= (unsigned long)(bits & 0x80) << 24;
02472                          tmp = bits & 0x40 ? 0x3c : 0x40;
02473                          value |= (unsigned long)tmp << 24;
02474                             size = 32;
02475                             isfloat = 1;
02476                        }
02477                      else
02478                        {
02479                          func (stream, "<illegal constant %.8x:%x:%x>",
02480                                   bits, cmode, op);
02481                             size = 32;
02482                          break;
02483                        }
02484                         switch (size)
02485                           {
02486                           case 8:
02487                          func (stream, "#%ld\t; 0x%.2lx", value, value);
02488                             break;
02489                           
02490                           case 16:
02491                             func (stream, "#%ld\t; 0x%.4lx", value, value);
02492                             break;
02493 
02494                           case 32:
02495                             if (isfloat)
02496                               {
02497                                 unsigned char valbytes[4];
02498                                 double fvalue;
02499                                 
02500                                 /* Do this a byte at a time so we don't have to
02501                                    worry about the host's endianness.  */
02502                                 valbytes[0] = value & 0xff;
02503                                 valbytes[1] = (value >> 8) & 0xff;
02504                                 valbytes[2] = (value >> 16) & 0xff;
02505                                 valbytes[3] = (value >> 24) & 0xff;
02506                                 
02507                                 floatformat_to_double 
02508                                   (&floatformat_ieee_single_little, valbytes,
02509                                   &fvalue);
02510                                                                 
02511                                 func (stream, "#%.7g\t; 0x%.8lx", fvalue,
02512                                       value);
02513                               }
02514                             else
02515                               func (stream, "#%ld\t; 0x%.8lx",
02516                             (long) ((value & 0x80000000)
02517                                    ? value | ~0xffffffffl : value), value);
02518                             break;
02519 
02520                           case 64:
02521                             func (stream, "#0x%.8lx%.8lx", hival, value);
02522                             break;
02523                           
02524                           default:
02525                             abort ();
02526                           }
02527                     }
02528                     break;
02529                     
02530                   case 'F':
02531                     {
02532                      int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
02533                      int num = (given >> 8) & 0x3;
02534                      
02535                      if (!num)
02536                        func (stream, "{d%d}", regno);
02537                      else if (num + regno >= 32)
02538                        func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
02539                      else
02540                        func (stream, "{d%d-d%d}", regno, regno + num);
02541                     }
02542                     break;
02543       
02544 
02545                   case '0': case '1': case '2': case '3': case '4':
02546                   case '5': case '6': case '7': case '8': case '9':
02547                     {
02548                      int width;
02549                      unsigned long value;
02550 
02551                      c = arm_decode_bitfield (c, given, &value, &width);
02552                      
02553                      switch (*c)
02554                        {
02555                        case 'r':
02556                          func (stream, "%s", arm_regnames[value]);
02557                          break;
02558                        case 'd':
02559                          func (stream, "%ld", value);
02560                          break;
02561                        case 'e':
02562                          func (stream, "%ld", (1ul << width) - value);
02563                          break;
02564                          
02565                        case 'S':
02566                        case 'T':
02567                        case 'U':
02568                          /* various width encodings */
02569                          {
02570                            int base = 8 << (*c - 'S'); /* 8,16 or 32 */
02571                            int limit;
02572                            unsigned low, high;
02573 
02574                            c++;
02575                            if (*c >= '0' && *c <= '9')
02576                             limit = *c - '0';
02577                            else if (*c >= 'a' && *c <= 'f')
02578                             limit = *c - 'a' + 10;
02579                            else
02580                             abort ();
02581                            low = limit >> 2;
02582                            high = limit & 3;
02583 
02584                            if (value < low || value > high)
02585                             func (stream, "<illegal width %d>", base << value);
02586                            else
02587                             func (stream, "%d", base << value);
02588                          }
02589                          break;
02590                        case 'R':
02591                          if (given & (1 << 6))
02592                            goto Q;
02593                          /* FALLTHROUGH */
02594                        case 'D':
02595                          func (stream, "d%ld", value);
02596                          break;
02597                        case 'Q':
02598                        Q:
02599                          if (value & 1)
02600                            func (stream, "<illegal reg q%ld.5>", value >> 1);
02601                          else
02602                            func (stream, "q%ld", value >> 1);
02603                          break;
02604                          
02605                        case '`':
02606                          c++;
02607                          if (value == 0)
02608                            func (stream, "%c", *c);
02609                          break;
02610                        case '\'':
02611                          c++;
02612                          if (value == ((1ul << width) - 1))
02613                            func (stream, "%c", *c);
02614                          break;
02615                        case '?':
02616                          func (stream, "%c", c[(1 << width) - (int)value]);
02617                          c += 1 << width;
02618                          break;
02619                        default:
02620                          abort ();
02621                        }
02622                      break;
02623 
02624                     default:
02625                      abort ();
02626                     }
02627                   }
02628               }
02629              else
02630               func (stream, "%c", *c);
02631            }
02632          return TRUE;
02633        }
02634     }
02635   return FALSE;
02636 }
02637 
02638 /* Print one ARM instruction from PC on INFO->STREAM.  */
02639 
02640 static void
02641 print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
02642 {
02643   const struct opcode32 *insn;
02644   void *stream = info->stream;
02645   fprintf_ftype func = info->fprintf_func;
02646 
02647   if (print_insn_coprocessor (pc, info, given, FALSE))
02648     return;
02649 
02650   if (print_insn_neon (info, given, FALSE))
02651     return;
02652 
02653   for (insn = arm_opcodes; insn->assembler; insn++)
02654     {
02655       if (insn->value == FIRST_IWMMXT_INSN
02656          && info->mach != bfd_mach_arm_XScale
02657          && info->mach != bfd_mach_arm_iWMMXt)
02658        insn = insn + IWMMXT_INSN_COUNT;
02659 
02660       if ((given & insn->mask) == insn->value
02661          /* Special case: an instruction with all bits set in the condition field
02662             (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
02663             or by the catchall at the end of the table.  */
02664          && ((given & 0xF0000000) != 0xF0000000
02665              || (insn->mask & 0xF0000000) == 0xF0000000
02666              || (insn->mask == 0 && insn->value == 0)))
02667        {
02668          const char *c;
02669 
02670          for (c = insn->assembler; *c; c++)
02671            {
02672              if (*c == '%')
02673               {
02674                 switch (*++c)
02675                   {
02676                   case '%':
02677                     func (stream, "%%");
02678                     break;
02679 
02680                   case 'a':
02681                     print_arm_address (pc, info, given);
02682                     break;
02683 
02684                   case 'P':
02685                     /* Set P address bit and use normal address
02686                       printing routine.  */
02687                     print_arm_address (pc, info, given | (1 << 24));
02688                     break;
02689 
02690                   case 's':
02691                       if ((given & 0x004f0000) == 0x004f0000)
02692                      {
02693                           /* PC relative with immediate offset.  */
02694                        int offset = ((given & 0xf00) >> 4) | (given & 0xf);
02695 
02696                        if ((given & 0x00800000) == 0)
02697                          offset = -offset;
02698 
02699                        func (stream, "[pc, #%d]\t; ", offset);
02700                        info->print_address_func (offset + pc + 8, info);
02701                      }
02702                     else
02703                      {
02704                        func (stream, "[%s",
02705                             arm_regnames[(given >> 16) & 0xf]);
02706                        if ((given & 0x01000000) != 0)
02707                          {
02708                               /* Pre-indexed.  */
02709                            if ((given & 0x00400000) == 0x00400000)
02710                             {
02711                                   /* Immediate.  */
02712                                   int offset = ((given & 0xf00) >> 4) | (given & 0xf);
02713                               if (offset)
02714                                 func (stream, ", #%s%d",
02715                                      (((given & 0x00800000) == 0)
02716                                       ? "-" : ""), offset);
02717                             }
02718                            else
02719                             {
02720                                   /* Register.  */
02721                               func (stream, ", %s%s",
02722                                    (((given & 0x00800000) == 0)
02723                                     ? "-" : ""),
02724                                         arm_regnames[given & 0xf]);
02725                             }
02726 
02727                            func (stream, "]%s",
02728                                 ((given & 0x00200000) != 0) ? "!" : "");
02729                          }
02730                        else
02731                          {
02732                               /* Post-indexed.  */
02733                            if ((given & 0x00400000) == 0x00400000)
02734                             {
02735                                   /* Immediate.  */
02736                                   int offset = ((given & 0xf00) >> 4) | (given & 0xf);
02737                               if (offset)
02738                                 func (stream, "], #%s%d",
02739                                      (((given & 0x00800000) == 0)
02740                                       ? "-" : ""), offset);
02741                               else
02742                                 func (stream, "]");
02743                             }
02744                            else
02745                             {
02746                                   /* Register.  */
02747                               func (stream, "], %s%s",
02748                                    (((given & 0x00800000) == 0)
02749                                     ? "-" : ""),
02750                                         arm_regnames[given & 0xf]);
02751                             }
02752                          }
02753                      }
02754                     break;
02755 
02756                   case 'b':
02757                     {
02758                      int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
02759                      info->print_address_func (disp*4 + pc + 8, info);
02760                     }
02761                     break;
02762 
02763                   case 'c':
02764                     if (((given >> 28) & 0xf) != 0xe)
02765                      func (stream, "%s",
02766                            arm_conditional [(given >> 28) & 0xf]);
02767                     break;
02768 
02769                   case 'm':
02770                     {
02771                      int started = 0;
02772                      int reg;
02773 
02774                      func (stream, "{");
02775                      for (reg = 0; reg < 16; reg++)
02776                        if ((given & (1 << reg)) != 0)
02777                          {
02778                            if (started)
02779                             func (stream, ", ");
02780                            started = 1;
02781                            func (stream, "%s", arm_regnames[reg]);
02782                          }
02783                      func (stream, "}");
02784                     }
02785                     break;
02786 
02787                   case 'o':
02788                     if ((given & 0x02000000) != 0)
02789                      {
02790                        int rotate = (given & 0xf00) >> 7;
02791                        int immed = (given & 0xff);
02792                        immed = (((immed << (32 - rotate))
02793                                 | (immed >> rotate)) & 0xffffffff);
02794                        func (stream, "#%d\t; 0x%x", immed, immed);
02795                      }
02796                     else
02797                      arm_decode_shift (given, func, stream);
02798                     break;
02799 
02800                   case 'p':
02801                     if ((given & 0x0000f000) == 0x0000f000)
02802                      func (stream, "p");
02803                     break;
02804 
02805                   case 't':
02806                     if ((given & 0x01200000) == 0x00200000)
02807                      func (stream, "t");
02808                     break;
02809 
02810                   case 'A':
02811                     func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
02812 
02813                     if ((given & (1 << 24)) != 0)
02814                      {
02815                        int offset = given & 0xff;
02816 
02817                        if (offset)
02818                          func (stream, ", #%s%d]%s",
02819                               ((given & 0x00800000) == 0 ? "-" : ""),
02820                               offset * 4,
02821                               ((given & 0x00200000) != 0 ? "!" : ""));
02822                        else
02823                          func (stream, "]");
02824                      }
02825                     else
02826                      {
02827                        int offset = given & 0xff;
02828 
02829                        func (stream, "]");
02830 
02831                        if (given & (1 << 21))
02832                          {
02833                            if (offset)
02834                             func (stream, ", #%s%d",
02835                                   ((given & 0x00800000) == 0 ? "-" : ""),
02836                                   offset * 4);
02837                          }
02838                        else
02839                          func (stream, ", {%d}", offset);
02840                      }
02841                     break;
02842 
02843                   case 'B':
02844                     /* Print ARM V5 BLX(1) address: pc+25 bits.  */
02845                     {
02846                      bfd_vma address;
02847                      bfd_vma offset = 0;
02848 
02849                      if (given & 0x00800000)
02850                        /* Is signed, hi bits should be ones.  */
02851                        offset = (-1) ^ 0x00ffffff;
02852 
02853                      /* Offset is (SignExtend(offset field)<<2).  */
02854                      offset += given & 0x00ffffff;
02855                      offset <<= 2;
02856                      address = offset + pc + 8;
02857 
02858                      if (given & 0x01000000)
02859                        /* H bit allows addressing to 2-byte boundaries.  */
02860                        address += 2;
02861 
02862                       info->print_address_func (address, info);
02863                     }
02864                     break;
02865 
02866                   case 'C':
02867                     func (stream, "_");
02868                     if (given & 0x80000)
02869                      func (stream, "f");
02870                     if (given & 0x40000)
02871                      func (stream, "s");
02872                     if (given & 0x20000)
02873                      func (stream, "x");
02874                     if (given & 0x10000)
02875                      func (stream, "c");
02876                     break;
02877 
02878                   case 'U':
02879                     switch (given & 0xf)
02880                      {
02881                      case 0xf: func(stream, "sy"); break;
02882                      case 0x7: func(stream, "un"); break;
02883                      case 0xe: func(stream, "st"); break;
02884                      case 0x6: func(stream, "unst"); break;
02885                      default:
02886                        func(stream, "#%d", (int)given & 0xf);
02887                        break;
02888                      }
02889                     break;
02890 
02891                   case '0': case '1': case '2': case '3': case '4':
02892                   case '5': case '6': case '7': case '8': case '9':
02893                     {
02894                      int width;
02895                      unsigned long value;
02896 
02897                      c = arm_decode_bitfield (c, given, &value, &width);
02898                      
02899                      switch (*c)
02900                        {
02901                        case 'r':
02902                          func (stream, "%s", arm_regnames[value]);
02903                          break;
02904                        case 'd':
02905                          func (stream, "%ld", value);
02906                          break;
02907                        case 'b':
02908                          func (stream, "%ld", value * 8);
02909                          break;
02910                        case 'W':
02911                          func (stream, "%ld", value + 1);
02912                          break;
02913                        case 'x':
02914                          func (stream, "0x%08lx", value);
02915 
02916                          /* Some SWI instructions have special
02917                             meanings.  */
02918                          if ((given & 0x0fffffff) == 0x0FF00000)
02919                            func (stream, "\t; IMB");
02920                          else if ((given & 0x0fffffff) == 0x0FF00001)
02921                            func (stream, "\t; IMBRange");
02922                          break;
02923                        case 'X':
02924                          func (stream, "%01lx", value & 0xf);
02925                          break;
02926                        case '`':
02927                          c++;
02928                          if (value == 0)
02929                            func (stream, "%c", *c);
02930                          break;
02931                        case '\'':
02932                          c++;
02933                          if (value == ((1ul << width) - 1))
02934                            func (stream, "%c", *c);
02935                          break;
02936                        case '?':
02937                          func (stream, "%c", c[(1 << width) - (int)value]);
02938                          c += 1 << width;
02939                          break;
02940                        default:
02941                          abort ();
02942                        }
02943                      break;
02944 
02945                     case 'e':
02946                      {
02947                        int imm;
02948 
02949                        imm = (given & 0xf) | ((given & 0xfff00) >> 4);
02950                        func (stream, "%d", imm);
02951                      }
02952                      break;
02953 
02954                     case 'E':
02955                      /* LSB and WIDTH fields of BFI or BFC.  The machine-
02956                         language instruction encodes LSB and MSB.  */
02957                      {
02958                        long msb = (given & 0x001f0000) >> 16;
02959                        long lsb = (given & 0x00000f80) >> 7;
02960 
02961                        long width = msb - lsb + 1;
02962                        if (width > 0)
02963                          func (stream, "#%lu, #%lu", lsb, width);
02964                        else
02965                          func (stream, "(invalid: %lu:%lu)", lsb, msb);
02966                      }
02967                      break;
02968 
02969                     case 'V':
02970                      /* 16-bit unsigned immediate from a MOVT or MOVW
02971                         instruction, encoded in bits 0:11 and 15:19.  */
02972                      {
02973                        long hi = (given & 0x000f0000) >> 4;
02974                        long lo = (given & 0x00000fff);
02975                        long imm16 = hi | lo;
02976                        func (stream, "#%lu\t; 0x%lx", imm16, imm16);
02977                      }
02978                      break;
02979 
02980                     default:
02981                      abort ();
02982                     }
02983                   }
02984               }
02985              else
02986               func (stream, "%c", *c);
02987            }
02988          return;
02989        }
02990     }
02991   abort ();
02992 }
02993 
02994 /* Print one 16-bit Thumb instruction from PC on INFO->STREAM.  */
02995 
02996 static void
02997 print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
02998 {
02999   const struct opcode16 *insn;
03000   void *stream = info->stream;
03001   fprintf_ftype func = info->fprintf_func;
03002 
03003   for (insn = thumb_opcodes; insn->assembler; insn++)
03004     if ((given & insn->mask) == insn->value)
03005       {
03006        const char *c = insn->assembler;
03007        for (; *c; c++)
03008          {
03009            int domaskpc = 0;
03010            int domasklr = 0;
03011 
03012            if (*c != '%')
03013              {
03014               func (stream, "%c", *c);
03015               continue;
03016              }
03017 
03018            switch (*++c)
03019              {
03020              case '%':
03021               func (stream, "%%");
03022               break;
03023 
03024              case 'c':
03025               if (ifthen_state)
03026                 func (stream, "%s", arm_conditional[IFTHEN_COND]);
03027               break;
03028 
03029              case 'C':
03030               if (ifthen_state)
03031                 func (stream, "%s", arm_conditional[IFTHEN_COND]);
03032               else
03033                 func (stream, "s");
03034               break;
03035 
03036              case 'I':
03037               {
03038                 unsigned int tmp;
03039 
03040                 ifthen_next_state = given & 0xff;
03041                 for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
03042                   func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
03043                 func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
03044               }
03045               break;
03046 
03047              case 'x':
03048               if (ifthen_next_state)
03049                 func (stream, "\t; unpredictable branch in IT block\n");
03050               break;
03051 
03052              case 'X':
03053               if (ifthen_state)
03054                 func (stream, "\t; unpredictable <IT:%s>",
03055                      arm_conditional[IFTHEN_COND]);
03056               break;
03057 
03058              case 'S':
03059               {
03060                 long reg;
03061 
03062                 reg = (given >> 3) & 0x7;
03063                 if (given & (1 << 6))
03064                   reg += 8;
03065 
03066                 func (stream, "%s", arm_regnames[reg]);
03067               }
03068               break;
03069 
03070              case 'D':
03071               {
03072                 long reg;
03073 
03074                 reg = given & 0x7;
03075                 if (given & (1 << 7))
03076                   reg += 8;
03077 
03078                 func (stream, "%s", arm_regnames[reg]);
03079               }
03080               break;
03081 
03082              case 'N':
03083               if (given & (1 << 8))
03084                 domasklr = 1;
03085               /* Fall through.  */
03086              case 'O':
03087               if (*c == 'O' && (given & (1 << 8)))
03088                 domaskpc = 1;
03089               /* Fall through.  */
03090              case 'M':
03091               {
03092                 int started = 0;
03093                 int reg;
03094 
03095                 func (stream, "{");
03096 
03097                 /* It would be nice if we could spot
03098                    ranges, and generate the rS-rE format: */
03099                 for (reg = 0; (reg < 8); reg++)
03100                   if ((given & (1 << reg)) != 0)
03101                     {
03102                      if (started)
03103                        func (stream, ", ");
03104                      started = 1;
03105                      func (stream, "%s", arm_regnames[reg]);
03106                     }
03107 
03108                 if (domasklr)
03109                   {
03110                     if (started)
03111                      func (stream, ", ");
03112                     started = 1;
03113                     func (stream, arm_regnames[14] /* "lr" */);
03114                   }
03115 
03116                 if (domaskpc)
03117                   {
03118                     if (started)
03119                      func (stream, ", ");
03120                     func (stream, arm_regnames[15] /* "pc" */);
03121                   }
03122 
03123                 func (stream, "}");
03124               }
03125               break;
03126 
03127              case 'b':
03128               /* Print ARM V6T2 CZB address: pc+4+6 bits.  */
03129               {
03130                 bfd_vma address = (pc + 4
03131                                  + ((given & 0x00f8) >> 2)
03132                                  + ((given & 0x0200) >> 3));
03133                 info->print_address_func (address, info);
03134               }
03135               break;
03136 
03137              case 's':
03138               /* Right shift immediate -- bits 6..10; 1-31 print
03139                  as themselves, 0 prints as 32.  */
03140               {
03141                 long imm = (given & 0x07c0) >> 6;
03142                 if (imm == 0)
03143                   imm = 32;
03144                 func (stream, "#%ld", imm);
03145               }
03146               break;
03147 
03148              case '0': case '1': case '2': case '3': case '4':
03149              case '5': case '6': case '7': case '8': case '9':
03150               {
03151                 int bitstart = *c++ - '0';
03152                 int bitend = 0;
03153 
03154                 while (*c >= '0' && *c <= '9')
03155                   bitstart = (bitstart * 10) + *c++ - '0';
03156 
03157                 switch (*c)
03158                   {
03159                   case '-':
03160                     {
03161                      long reg;
03162 
03163                      c++;
03164                      while (*c >= '0' && *c <= '9')
03165                        bitend = (bitend * 10) + *c++ - '0';
03166                      if (!bitend)
03167                        abort ();
03168                      reg = given >> bitstart;
03169                      reg &= (2 << (bitend - bitstart)) - 1;
03170                      switch (*c)
03171                        {
03172                        case 'r':
03173                          func (stream, "%s", arm_regnames[reg]);
03174                          break;
03175 
03176                        case 'd':
03177                          func (stream, "%ld", reg);
03178                          break;
03179 
03180                        case 'H':
03181                          func (stream, "%ld", reg << 1);
03182                          break;
03183 
03184                        case 'W':
03185                          func (stream, "%ld", reg << 2);
03186                          break;
03187 
03188                        case 'a':
03189                          /* PC-relative address -- the bottom two
03190                             bits of the address are dropped
03191                             before the calculation.  */
03192                          info->print_address_func
03193                            (((pc + 4) & ~3) + (reg << 2), info);
03194                          break;
03195 
03196                        case 'x':
03197                          func (stream, "0x%04lx", reg);
03198                          break;
03199 
03200                        case 'B':
03201                          reg = ((reg ^ (1 << bitend)) - (1 << bitend));
03202                          info->print_address_func (reg * 2 + pc + 4, info);
03203                          break;
03204 
03205                        case 'c':
03206                          func (stream, "%s", arm_conditional [reg]);
03207                          break;
03208 
03209                        default:
03210                          abort ();
03211                        }
03212                     }
03213                     break;
03214 
03215                   case '\'':
03216                     c++;
03217                     if ((given & (1 << bitstart)) != 0)
03218                      func (stream, "%c", *c);
03219                     break;
03220 
03221                   case '?':
03222                     ++c;
03223                     if ((given & (1 << bitstart)) != 0)
03224                      func (stream, "%c", *c++);
03225                     else
03226                      func (stream, "%c", *++c);
03227                     break;
03228 
03229                   default:
03230                     abort ();
03231                   }
03232               }
03233               break;
03234 
03235              default:
03236               abort ();
03237              }
03238          }
03239        return;
03240       }
03241 
03242   /* No match.  */
03243   abort ();
03244 }
03245 
03246 /* Return the name of an V7M special register.  */
03247 static const char *
03248 psr_name (int regno)
03249 {
03250   switch (regno)
03251     {
03252     case 0: return "APSR";
03253     case 1: return "IAPSR";
03254     case 2: return "EAPSR";
03255     case 3: return "PSR";
03256     case 5: return "IPSR";
03257     case 6: return "EPSR";
03258     case 7: return "IEPSR";
03259     case 8: return "MSP";
03260     case 9: return "PSP";
03261     case 16: return "PRIMASK";
03262     case 17: return "BASEPRI";
03263     case 18: return "BASEPRI_MASK";
03264     case 19: return "FAULTMASK";
03265     case 20: return "CONTROL";
03266     default: return "<unknown>";
03267     }
03268 }
03269 
03270 /* Print one 32-bit Thumb instruction from PC on INFO->STREAM.  */
03271 
03272 static void
03273 print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
03274 {
03275   const struct opcode32 *insn;
03276   void *stream = info->stream;
03277   fprintf_ftype func = info->fprintf_func;
03278 
03279   if (print_insn_coprocessor (pc, info, given, TRUE))
03280     return;
03281 
03282   if (print_insn_neon (info, given, TRUE))
03283     return;
03284 
03285   for (insn = thumb32_opcodes; insn->assembler; insn++)
03286     if ((given & insn->mask) == insn->value)
03287       {
03288        const char *c = insn->assembler;
03289        for (; *c; c++)
03290          {
03291            if (*c != '%')
03292              {
03293               func (stream, "%c", *c);
03294               continue;
03295              }
03296 
03297            switch (*++c)
03298              {
03299              case '%':
03300               func (stream, "%%");
03301               break;
03302 
03303              case 'c':
03304               if (ifthen_state)
03305                 func (stream, "%s", arm_conditional[IFTHEN_COND]);
03306               break;
03307 
03308              case 'x':
03309               if (ifthen_next_state)
03310                 func (stream, "\t; unpredictable branch in IT block\n");
03311               break;
03312 
03313              case 'X':
03314               if (ifthen_state)
03315                 func (stream, "\t; unpredictable <IT:%s>",
03316                      arm_conditional[IFTHEN_COND]);
03317               break;
03318 
03319              case 'I':
03320               {
03321                 unsigned int imm12 = 0;
03322                 imm12 |= (given & 0x000000ffu);
03323                 imm12 |= (given & 0x00007000u) >> 4;
03324                 imm12 |= (given & 0x04000000u) >> 15;
03325                 func (stream, "#%u\t; 0x%x", imm12, imm12);
03326               }
03327               break;
03328 
03329              case 'M':
03330               {
03331                 unsigned int bits = 0, imm, imm8, mod;
03332                 bits |= (given & 0x000000ffu);
03333                 bits |= (given & 0x00007000u) >> 4;
03334                 bits |= (given & 0x04000000u) >> 15;
03335                 imm8 = (bits & 0x0ff);
03336                 mod = (bits & 0xf00) >> 8;
03337                 switch (mod)
03338                   {
03339                   case 0: imm = imm8; break;
03340                   case 1: imm = ((imm8<<16) | imm8); break;
03341                   case 2: imm = ((imm8<<24) | (imm8 << 8)); break;
03342                   case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
03343                   default:
03344                     mod  = (bits & 0xf80) >> 7;
03345                     imm8 = (bits & 0x07f) | 0x80;
03346                     imm  = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
03347                   }
03348                 func (stream, "#%u\t; 0x%x", imm, imm);
03349               }
03350               break;
03351                 
03352              case 'J':
03353               {
03354                 unsigned int imm = 0;
03355                 imm |= (given & 0x000000ffu);
03356                 imm |= (given & 0x00007000u) >> 4;
03357                 imm |= (given & 0x04000000u) >> 15;
03358                 imm |= (given & 0x000f0000u) >> 4;
03359                 func (stream, "#%u\t; 0x%x", imm, imm);
03360               }
03361               break;
03362 
03363              case 'K':
03364               {
03365                 unsigned int imm = 0;
03366                 imm |= (given & 0x000f0000u) >> 16;
03367                 imm |= (given & 0x00000ff0u) >> 0;
03368                 imm |= (given & 0x0000000fu) << 12;
03369                 func (stream, "#%u\t; 0x%x", imm, imm);
03370               }
03371               break;
03372 
03373              case 'S':
03374               {
03375                 unsigned int reg = (given & 0x0000000fu);
03376                 unsigned int stp = (given & 0x00000030u) >> 4;
03377                 unsigned int imm = 0;
03378                 imm |= (given & 0x000000c0u) >> 6;
03379                 imm |= (given & 0x00007000u) >> 10;
03380 
03381                 func (stream, "%s", arm_regnames[reg]);
03382                 switch (stp)
03383                   {
03384                   case 0:
03385                     if (imm > 0)
03386                      func (stream, ", lsl #%u", imm);
03387                     break;
03388 
03389                   case 1:
03390                     if (imm == 0)
03391                      imm = 32;
03392                     func (stream, ", lsr #%u", imm);
03393                     break;
03394 
03395                   case 2:
03396                     if (imm == 0)
03397                      imm = 32;
03398                     func (stream, ", asr #%u", imm);
03399                     break;
03400 
03401                   case 3:
03402                     if (imm == 0)
03403                      func (stream, ", rrx");
03404                     else
03405                      func (stream, ", ror #%u", imm);
03406                   }
03407               }
03408               break;
03409 
03410              case 'a':
03411               {
03412                 unsigned int Rn  = (given & 0x000f0000) >> 16;
03413                 unsigned int U   = (given & 0x00800000) >> 23;
03414                 unsigned int op  = (given & 0x00000f00) >> 8;
03415                 unsigned int i12 = (given & 0x00000fff);
03416                 unsigned int i8  = (given & 0x000000ff);
03417                 bfd_boolean writeback = FALSE, postind = FALSE;
03418                 int offset = 0;
03419 
03420                 func (stream, "[%s", arm_regnames[Rn]);
03421                 if (U) /* 12-bit positive immediate offset */
03422                   offset = i12;
03423                 else if (Rn == 15) /* 12-bit negative immediate offset */
03424                   offset = -(int)i12;
03425                 else if (op == 0x0) /* shifted register offset */
03426                   {
03427                     unsigned int Rm = (i8 & 0x0f);
03428                     unsigned int sh = (i8 & 0x30) >> 4;
03429                     func (stream, ", %s", arm_regnames[Rm]);
03430                     if (sh)
03431                      func (stream, ", lsl #%u", sh);
03432                     func (stream, "]");
03433                     break;
03434                   }
03435                 else switch (op)
03436                   {
03437                   case 0xE:  /* 8-bit positive immediate offset */
03438                     offset = i8;
03439                     break;
03440 
03441                   case 0xC:  /* 8-bit negative immediate offset */
03442                     offset = -i8;
03443                     break;
03444 
03445                   case 0xF:  /* 8-bit + preindex with wb */
03446                     offset = i8;
03447                     writeback = TRUE;
03448                     break;
03449 
03450                   case 0xD:  /* 8-bit - preindex with wb */
03451                     offset = -i8;
03452                     writeback = TRUE;
03453                     break;
03454 
03455                   case 0xB:  /* 8-bit + postindex */
03456                     offset = i8;
03457                     postind = TRUE;
03458                     break;
03459 
03460                   case 0x9:  /* 8-bit - postindex */
03461                     offset = -i8;
03462                     postind = TRUE;
03463                     break;
03464 
03465                   default:
03466                     func (stream, ", <undefined>]");
03467                     goto skip;
03468                   }
03469 
03470                 if (postind)
03471                   func (stream, "], #%d", offset);
03472                 else
03473                   {
03474                     if (offset)
03475                      func (stream, ", #%d", offset);
03476                     func (stream, writeback ? "]!" : "]");
03477                   }
03478 
03479                 if (Rn == 15)
03480                   {
03481                     func (stream, "\t; ");
03482                     info->print_address_func (((pc + 4) & ~3) + offset, info);
03483                   }
03484               }
03485              skip:
03486               break;
03487 
03488              case 'A':
03489               {
03490                 unsigned int P   = (given & 0x01000000) >> 24;
03491                 unsigned int U   = (given & 0x00800000) >> 23;
03492                 unsigned int W   = (given & 0x00400000) >> 21;
03493                 unsigned int Rn  = (given & 0x000f0000) >> 16;
03494                 unsigned int off = (given & 0x000000ff);
03495 
03496                 func (stream, "[%s", arm_regnames[Rn]);
03497                 if (P)
03498                   {
03499                     if (off || !U)
03500                      func (stream, ", #%c%u", U ? '+' : '-', off * 4);
03501                     func (stream, "]");
03502                     if (W)
03503                      func (stream, "!");
03504                   }
03505                 else
03506                   {
03507                     func (stream, "], ");
03508                     if (W)
03509                      func (stream, "#%c%u", U ? '+' : '-', off * 4);
03510                     else
03511                      func (stream, "{%u}", off);
03512                   }
03513               }
03514               break;
03515 
03516              case 'w':
03517               {
03518                 unsigned int Sbit = (given & 0x01000000) >> 24;
03519                 unsigned int type = (given & 0x00600000) >> 21;
03520                 switch (type)
03521                   {
03522                   case 0: func (stream, Sbit ? "sb" : "b"); break;
03523                   case 1: func (stream, Sbit ? "sh" : "h"); break;
03524                   case 2:
03525                     if (Sbit)
03526                      func (stream, "??");
03527                     break;
03528                   case 3:
03529                     func (stream, "??");
03530                     break;
03531                   }
03532               }
03533               break;
03534 
03535              case 'm':
03536               {
03537                 int started = 0;
03538                 int reg;
03539 
03540                 func (stream, "{");
03541                 for (reg = 0; reg < 16; reg++)
03542                   if ((given & (1 << reg)) != 0)
03543                     {
03544                      if (started)
03545                        func (stream, ", ");
03546                      started = 1;
03547                      func (stream, "%s", arm_regnames[reg]);
03548                     }
03549                 func (stream, "}");
03550               }
03551               break;
03552 
03553              case 'E':
03554               {
03555                 unsigned int msb = (given & 0x0000001f);
03556                 unsigned int lsb = 0;
03557                 lsb |= (given & 0x000000c0u) >> 6;
03558                 lsb |= (given & 0x00007000u) >> 10;
03559                 func (stream, "#%u, #%u", lsb, msb - lsb + 1);
03560               }
03561               break;
03562 
03563              case 'F':
03564               {
03565                 unsigned int width = (given & 0x0000001f) + 1;
03566                 unsigned int lsb = 0;
03567                 lsb |= (given & 0x000000c0u) >> 6;
03568                 lsb |= (given & 0x00007000u) >> 10;
03569                 func (stream, "#%u, #%u", lsb, width);
03570               }
03571               break;
03572 
03573              case 'b':
03574               {
03575                 unsigned int S = (given & 0x04000000u) >> 26;
03576                 unsigned int J1 = (given & 0x00002000u) >> 13;
03577                 unsigned int J2 = (given & 0x00000800u) >> 11;
03578                 int offset = 0;
03579 
03580                 offset |= !S << 20;
03581                 offset |= J2 << 19;
03582                 offset |= J1 << 18;
03583                 offset |= (given & 0x003f0000) >> 4;
03584                 offset |= (given & 0x000007ff) << 1;
03585                 offset -= (1 << 20);
03586 
03587                 info->print_address_func (pc + 4 + offset, info);
03588               }
03589               break;
03590 
03591              case 'B':
03592               {
03593                 unsigned int S = (given & 0x04000000u) >> 26;
03594                 unsigned int I1 = (given & 0x00002000u) >> 13;
03595                 unsigned int I2 = (given & 0x00000800u) >> 11;
03596                 int offset = 0;
03597 
03598                 offset |= !S << 24;
03599                 offset |= !(I1 ^ S) << 23;
03600                 offset |= !(I2 ^ S) << 22;
03601                 offset |= (given & 0x03ff0000u) >> 4;
03602                 offset |= (given & 0x000007ffu) << 1;
03603                 offset -= (1 << 24);
03604                 offset += pc + 4;
03605 
03606                 /* BLX target addresses are always word aligned.  */
03607                 if ((given & 0x00001000u) == 0)
03608                     offset &= ~2u;
03609 
03610                 info->print_address_func (offset, info);
03611               }
03612               break;
03613 
03614              case 's':
03615               {
03616                 unsigned int shift = 0;
03617                 shift |= (given & 0x000000c0u) >> 6;
03618                 shift |= (given & 0x00007000u) >> 10;
03619                 if (given & 0x00200000u)
03620                   func (stream, ", asr #%u", shift);
03621                 else if (shift)
03622                   func (stream, ", lsl #%u", shift);
03623                 /* else print nothing - lsl #0 */
03624               }
03625               break;
03626 
03627              case 'R':
03628               {
03629                 unsigned int rot = (given & 0x00000030) >> 4;
03630                 if (rot)
03631                   func (stream, ", ror #%u", rot * 8);
03632               }
03633               break;
03634 
03635              case 'U':
03636               switch (given & 0xf)
03637                 {
03638                 case 0xf: func(stream, "sy"); break;
03639                 case 0x7: func(stream, "un"); break;
03640                 case 0xe: func(stream, "st"); break;
03641                 case 0x6: func(stream, "unst"); break;
03642                 default:
03643                   func(stream, "#%d", (int)given & 0xf);
03644                   break;
03645                 }
03646               break;
03647 
03648              case 'C':
03649               if ((given & 0xff) == 0)
03650                 {
03651                   func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
03652                   if (given & 0x800)
03653                     func (stream, "f");
03654                   if (given & 0x400)
03655                     func (stream, "s");
03656                   if (given & 0x200)
03657                     func (stream, "x");
03658                   if (given & 0x100)
03659                     func (stream, "c");
03660                 }
03661               else
03662                 {
03663                   func (stream, psr_name (given & 0xff));
03664                 }
03665               break;
03666 
03667              case 'D':
03668               if ((given & 0xff) == 0)
03669                 func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C');
03670               else
03671                 func (stream, psr_name (given & 0xff));
03672               break;
03673 
03674              case '0': case '1': case '2': case '3': case '4':
03675              case '5': case '6': case '7': case '8': case '9':
03676               {
03677                 int width;
03678                 unsigned long val;
03679 
03680                 c = arm_decode_bitfield (c, given, &val, &width);
03681                      
03682                 switch (*c)
03683                   {
03684                   case 'd': func (stream, "%lu", val); break;
03685                   case 'W': func (stream, "%lu", val * 4); break;
03686                   case 'r': func (stream, "%s", arm_regnames[val]); break;
03687 
03688                   case 'c':
03689                     func (stream, "%s", arm_conditional[val]);
03690                     break;
03691 
03692                   case '\'':
03693                     c++;
03694                     if (val == ((1ul << width) - 1))
03695                      func (stream, "%c", *c);
03696                     break;
03697                     
03698                   case '`':
03699                     c++;
03700                     if (val == 0)
03701                      func (stream, "%c", *c);
03702                     break;
03703 
03704                   case '?':
03705                     func (stream, "%c", c[(1 << width) - (int)val]);
03706                     c += 1 << width;
03707                     break;
03708 
03709                   default:
03710                     abort ();
03711                   }
03712               }
03713               break;
03714 
03715              default:
03716               abort ();
03717              }
03718          }
03719        return;
03720       }
03721 
03722   /* No match.  */
03723   abort ();
03724 }
03725 
03726 /* Print data bytes on INFO->STREAM.  */
03727 
03728 static void
03729 print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info,
03730                long given)
03731 {
03732   switch (info->bytes_per_chunk)
03733     {
03734     case 1:
03735       info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
03736       break;
03737     case 2:
03738       info->fprintf_func (info->stream, ".short\t0x%04lx", given);
03739       break;
03740     case 4:
03741       info->fprintf_func (info->stream, ".word\t0x%08lx", given);
03742       break;
03743     default:
03744       abort ();
03745     }
03746 }
03747 
03748 /* Disallow mapping symbols ($a, $b, $d, $t etc) from
03749    being displayed in symbol relative addresses.  */
03750 
03751 bfd_boolean
03752 arm_symbol_is_valid (asymbol * sym,
03753                    struct disassemble_info * info ATTRIBUTE_UNUSED)
03754 {
03755   const char * name;
03756   
03757   if (sym == NULL)
03758     return FALSE;
03759 
03760   name = bfd_asymbol_name (sym);
03761 
03762   return (name && *name != '$');
03763 }
03764 
03765 /* Parse an individual disassembler option.  */
03766 
03767 void
03768 parse_arm_disassembler_option (char *option)
03769 {
03770   if (option == NULL)
03771     return;
03772 
03773   if (CONST_STRNEQ (option, "reg-names-"))
03774     {
03775       int i;
03776 
03777       option += 10;
03778 
03779       for (i = NUM_ARM_REGNAMES; i--;)
03780        if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
03781          {
03782            regname_selected = i;
03783            break;
03784          }
03785 
03786       if (i < 0)
03787        /* XXX - should break 'option' at following delimiter.  */
03788        fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
03789     }
03790   else if (CONST_STRNEQ (option, "force-thumb"))
03791     force_thumb = 1;
03792   else if (CONST_STRNEQ (option, "no-force-thumb"))
03793     force_thumb = 0;
03794   else
03795     /* XXX - should break 'option' at following delimiter.  */
03796     fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
03797 
03798   return;
03799 }
03800 
03801 /* Parse the string of disassembler options, spliting it at whitespaces
03802    or commas.  (Whitespace separators supported for backwards compatibility).  */
03803 
03804 static void
03805 parse_disassembler_options (char *options)
03806 {
03807   if (options == NULL)
03808     return;
03809 
03810   while (*options)
03811     {
03812       parse_arm_disassembler_option (options);
03813 
03814       /* Skip forward to next seperator.  */
03815       while ((*options) && (! ISSPACE (*options)) && (*options != ','))
03816        ++ options;
03817       /* Skip forward past seperators.  */
03818       while (ISSPACE (*options) || (*options == ','))
03819        ++ options;      
03820     }
03821 }
03822 
03823 /* Search back through the insn stream to determine if this instruction is
03824    conditionally executed.  */
03825 static void
03826 find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
03827                  bfd_boolean little)
03828 {
03829   unsigned char b[2];
03830   unsigned int insn;
03831   int status;
03832   /* COUNT is twice the number of instructions seen.  It will be odd if we
03833      just crossed an instruction boundary.  */
03834   int count;
03835   int it_count;
03836   unsigned int seen_it;
03837   bfd_vma addr;
03838 
03839   ifthen_address = pc;
03840   ifthen_state = 0;
03841 
03842   addr = pc;
03843   count = 1;
03844   it_count = 0;
03845   seen_it = 0;
03846   /* Scan backwards looking for IT instructions, keeping track of where
03847      instruction boundaries are.  We don't know if something is actually an
03848      IT instruction until we find a definite instruction boundary.  */
03849   for (;;)
03850     {
03851       if (addr == 0 || info->symbol_at_address_func(addr, info))
03852        {
03853          /* A symbol must be on an instruction boundary, and will not
03854             be within an IT block.  */
03855          if (seen_it && (count & 1))
03856            break;
03857 
03858          return;
03859        }
03860       addr -= 2;
03861       status = info->read_memory_func (addr, (bfd_byte *)b, 2, info);
03862       if (status)
03863        return;
03864 
03865       if (little)
03866        insn = (b[0]) | (b[1] << 8);
03867       else
03868        insn = (b[1]) | (b[0] << 8);
03869       if (seen_it)
03870        {
03871          if ((insn & 0xf800) < 0xe800)
03872            {
03873              /* Addr + 2 is an instruction boundary.  See if this matches
03874                 the expected boundary based on the position of the last
03875                IT candidate.  */
03876              if (count & 1)
03877               break;
03878              seen_it = 0;
03879            }
03880        }
03881       if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
03882        {
03883          /* This could be an IT instruction.  */
03884          seen_it = insn;
03885          it_count = count >> 1;
03886        }
03887       if ((insn & 0xf800) >= 0xe800)
03888        count++;
03889       else
03890        count = (count + 2) | 1;
03891       /* IT blocks contain at most 4 instructions.  */
03892       if (count >= 8 && !seen_it)
03893        return;
03894     }
03895   /* We found an IT instruction.  */
03896   ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
03897   if ((ifthen_state & 0xf) == 0)
03898     ifthen_state = 0;
03899 }
03900 
03901 /* Try to infer the code type (Arm or Thumb) from a symbol.
03902    Returns nonzero if *MAP_TYPE was set.  */
03903 
03904 static int
03905 get_sym_code_type (struct disassemble_info *info, int n,
03906                  enum map_type *map_type)
03907 {
03908   elf_symbol_type *es;
03909   unsigned int type;
03910   const char *name;
03911 
03912   es = *(elf_symbol_type **)(info->symtab + n);
03913   type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
03914 
03915   /* If the symbol has function type then use that.  */
03916   if (type == STT_FUNC || type == STT_ARM_TFUNC)
03917     {
03918       *map_type = (type == STT_ARM_TFUNC) ? MAP_THUMB : MAP_ARM;
03919       return TRUE;
03920     }
03921 
03922   /* Check for mapping symbols.  */
03923   name = bfd_asymbol_name(info->symtab[n]);
03924   if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
03925       && (name[2] == 0 || name[2] == '.'))
03926     {
03927       *map_type = ((name[1] == 'a') ? MAP_ARM
03928                  : (name[1] == 't') ? MAP_THUMB
03929                  : MAP_DATA);
03930       return TRUE;
03931     }
03932 
03933   return FALSE;
03934 }
03935 
03936 /* NOTE: There are no checks in these routines that
03937    the relevant number of data bytes exist.  */
03938 
03939 static int
03940 print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
03941 {
03942   unsigned char b[4];
03943   long        given;
03944   int           status;
03945   int           is_thumb = FALSE;
03946   int           is_data = FALSE;
03947   unsigned int       size = 4;
03948   void        (*printer) (bfd_vma, struct disassemble_info *, long);
03949   bfd_boolean   found = FALSE;
03950 
03951   if (info->disassembler_options)
03952     {
03953       parse_disassembler_options (info->disassembler_options);
03954 
03955       /* To avoid repeated parsing of these options, we remove them here.  */
03956       info->disassembler_options = NULL;
03957     }
03958 
03959   /* First check the full symtab for a mapping symbol, even if there
03960      are no usable non-mapping symbols for this address.  */
03961   if (info->symtab != NULL
03962       && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
03963     {
03964       bfd_vma addr;
03965       int n;
03966       int last_sym = -1;
03967       enum map_type type;
03968 
03969       if (pc <= last_mapping_addr)
03970        last_mapping_sym = -1;
03971       is_thumb = (last_type == MAP_THUMB);
03972       found = FALSE;
03973       /* Start scanning at the start of the function, or wherever
03974         we finished last time.  */
03975       n = info->symtab_pos + 1;
03976       if (n < last_mapping_sym)
03977        n = last_mapping_sym;
03978 
03979       /* Scan up to the location being disassembled.  */
03980       for (; n < info->symtab_size; n++)
03981        {
03982          addr = bfd_asymbol_value (info->symtab[n]);
03983          if (addr > pc)
03984            break;
03985          if (get_sym_code_type (info, n, &type))
03986            {
03987              last_sym = n;
03988              found = TRUE;
03989            }
03990        }
03991 
03992       if (!found)
03993        {
03994          n = info->symtab_pos;
03995          if (n < last_mapping_sym - 1)
03996            n = last_mapping_sym - 1;
03997 
03998          /* No mapping symbol found at this address.  Look backwards
03999             for a preceeding one.  */
04000          for (; n >= 0; n--)
04001            {
04002              if (get_sym_code_type (info, n, &type))
04003               {
04004                 last_sym = n;
04005                 found = TRUE;
04006                 break;
04007               }
04008            }
04009        }
04010 
04011       last_mapping_sym = last_sym;
04012       last_type = type;
04013       is_thumb = (last_type == MAP_THUMB);
04014       is_data = (last_type == MAP_DATA);
04015 
04016       /* Look a little bit ahead to see if we should print out
04017         two or four bytes of data.  If there's a symbol,
04018         mapping or otherwise, after two bytes then don't
04019         print more.  */
04020       if (is_data)
04021        {
04022          size = 4 - (pc & 3);
04023          for (n = last_sym + 1; n < info->symtab_size; n++)
04024            {
04025              addr = bfd_asymbol_value (info->symtab[n]);
04026              if (addr > pc)
04027               {
04028                 if (addr - pc < size)
04029                   size = addr - pc;
04030                 break;
04031               }
04032            }
04033          /* If the next symbol is after three bytes, we need to
04034             print only part of the data, so that we can use either
04035             .byte or .short.  */
04036          if (size == 3)
04037            size = (pc & 1) ? 1 : 2;
04038        }
04039     }
04040 
04041   if (info->symbols != NULL)
04042     {
04043       if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
04044        {
04045          coff_symbol_type * cs;
04046 
04047          cs = coffsymbol (*info->symbols);
04048          is_thumb = (   cs->native->u.syment.n_sclass == C_THUMBEXT
04049                     || cs->native->u.syment.n_sclass == C_THUMBSTAT
04050                     || cs->native->u.syment.n_sclass == C_THUMBLABEL
04051                     || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
04052                     || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
04053        }
04054       else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
04055               && !found)
04056        {
04057          /* If no mapping symbol has been found then fall back to the type
04058             of the function symbol.  */
04059          elf_symbol_type *  es;
04060          unsigned int       type;
04061 
04062          es = *(elf_symbol_type **)(info->symbols);
04063          type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
04064 
04065          is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
04066        }
04067     }
04068 
04069   if (force_thumb)
04070     is_thumb = TRUE;
04071 
04072   info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
04073   info->bytes_per_line = 4;
04074 
04075   if (is_data)
04076     {
04077       int i;
04078 
04079       /* size was already set above.  */
04080       info->bytes_per_chunk = size;
04081       printer = print_insn_data;
04082 
04083       status = info->read_memory_func (pc, (bfd_byte *)b, size, info);
04084       given = 0;
04085       if (little)
04086        for (i = size - 1; i >= 0; i--)
04087          given = b[i] | (given << 8);
04088       else
04089        for (i = 0; i < (int) size; i++)
04090          given = b[i] | (given << 8);
04091     }
04092   else if (!is_thumb)
04093     {
04094       /* In ARM mode endianness is a straightforward issue: the instruction
04095         is four bytes long and is either ordered 0123 or 3210.  */
04096       printer = print_insn_arm;
04097       info->bytes_per_chunk = 4;
04098       size = 4;
04099 
04100       status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
04101       if (little)
04102        given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
04103       else
04104        given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
04105     }
04106   else
04107     {
04108       /* In Thumb mode we have the additional wrinkle of two
04109         instruction lengths.  Fortunately, the bits that determine
04110         the length of the current instruction are always to be found
04111         in the first two bytes.  */
04112       printer = print_insn_thumb16;
04113       info->bytes_per_chunk = 2;
04114       size = 2;
04115 
04116       status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
04117       if (little)
04118        given = (b[0]) | (b[1] << 8);
04119       else
04120        given = (b[1]) | (b[0] << 8);
04121 
04122       if (!status)
04123        {
04124          /* These bit patterns signal a four-byte Thumb
04125             instruction.  */
04126          if ((given & 0xF800) == 0xF800
04127              || (given & 0xF800) == 0xF000
04128              || (given & 0xF800) == 0xE800)
04129            {
04130              status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info);
04131              if (little)
04132               given = (b[0]) | (b[1] << 8) | (given << 16);
04133              else
04134               given = (b[1]) | (b[0] << 8) | (given << 16);
04135 
04136              printer = print_insn_thumb32;
04137              size = 4;
04138            }
04139        }
04140 
04141       if (ifthen_address != pc)
04142        find_ifthen_state(pc, info, little);
04143 
04144       if (ifthen_state)
04145        {
04146          if ((ifthen_state & 0xf) == 0x8)
04147            ifthen_next_state = 0;
04148          else
04149            ifthen_next_state = (ifthen_state & 0xe0)
04150                             | ((ifthen_state & 0xf) << 1);
04151        }
04152     }
04153 
04154   if (status)
04155     {
04156       info->memory_error_func (status, pc, info);
04157       return -1;
04158     }
04159   if (info->flags & INSN_HAS_RELOC)
04160     /* If the instruction has a reloc associated with it, then
04161        the offset field in the instruction will actually be the
04162        addend for the reloc.  (We are using REL type relocs).
04163        In such cases, we can ignore the pc when computing
04164        addresses, since the addend is not currently pc-relative.  */
04165     pc = 0;
04166 
04167   printer (pc, info, given);
04168 
04169   if (is_thumb)
04170     {
04171       ifthen_state = ifthen_next_state;
04172       ifthen_address += size;
04173     }
04174   return size;
04175 }
04176 
04177 int
04178 print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
04179 {
04180   return print_insn (pc, info, FALSE);
04181 }
04182 
04183 int
04184 print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
04185 {
04186   return print_insn (pc, info, TRUE);
04187 }
04188 
04189 void
04190 print_arm_disassembler_options (FILE *stream)
04191 {
04192   int i;
04193 
04194   fprintf (stream, _("\n\
04195 The following ARM specific disassembler options are supported for use with\n\
04196 the -M switch:\n"));
04197 
04198   for (i = NUM_ARM_REGNAMES; i--;)
04199     fprintf (stream, "  reg-names-%s %*c%s\n",
04200             regnames[i].name,
04201             (int)(14 - strlen (regnames[i].name)), ' ',
04202             regnames[i].description);
04203 
04204   fprintf (stream, "  force-thumb              Assume all insns are Thumb insns\n");
04205   fprintf (stream, "  no-force-thumb           Examine preceeding label to determine an insn's type\n\n");
04206 }