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cell-binutils  2.17cvs20070401
arch6zk.d
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00001 #name: ARM V6 instructions
00002 #as: -march=armv6zk
00003 #objdump: -dr --prefix-addresses --show-raw-insn
00004 
00005 .*: +file format .*arm.*
00006 
00007 Disassembly of section .text:
00008 0+000 <[^>]*> f57ff01f ?    clrex
00009 0+004 <[^>]*> e1dc4f9f ?    ldrexb r4, \[ip\]
00010 0+008 <[^>]*> 11d4cf9f ?    ldrexbne      ip, \[r4\]
00011 0+00c <[^>]*> e1bc4f9f ?    ldrexd r4, \[ip\]
00012 0+010 <[^>]*> 11b4cf9f ?    ldrexdne      ip, \[r4\]
00013 0+014 <[^>]*> e1fc4f9f ?    ldrexh r4, \[ip\]
00014 0+018 <[^>]*> 11f4cf9f ?    ldrexhne      ip, \[r4\]
00015 0+01c <[^>]*> e320f080 ?    nop    \{128\}
00016 0+020 <[^>]*> 1320f07f ?    nopne  \{127\}
00017 0+024 <[^>]*> e320f004 ?    sev
00018 0+028 <[^>]*> e1c74f9c ?    strexb r4, ip, \[r7\]
00019 0+02c <[^>]*> 11c8cf94 ?    strexbne      ip, r4, \[r8\]
00020 0+030 <[^>]*> e1a74f9c ?    strexd r4, ip, \[r7\]
00021 0+034 <[^>]*> 11a8cf94 ?    strexdne      ip, r4, \[r8\]
00022 0+038 <[^>]*> e1e74f9c ?    strexh r4, ip, \[r7\]
00023 0+03c <[^>]*> 11e8cf94 ?    strexhne      ip, r4, \[r8\]
00024 0+040 <[^>]*> e320f002 ?    wfe
00025 0+044 <[^>]*> e320f003 ?    wfi
00026 0+048 <[^>]*> e320f001 ?    yield
00027 0+04c <[^>]*> e16ec371 ?    smc    60465
00028 0+050 <[^>]*> 11613c7e ?    smcne  5070
00029 0+054 <[^>]*> e1a00000 ?    nop[   ]+\(mov r0,r0\)
00030 0+058 <[^>]*> e1a00000 ?    nop[   ]+\(mov r0,r0\)
00031 0+05c <[^>]*> e1a00000 ?    nop[   ]+\(mov r0,r0\)
00032