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cell-binutils  2.17cvs20070401
arch4t.d
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00001 # name: ARM architecture 4t instructions
00002 # as: -march=armv4t
00003 # objdump: -dr --prefix-addresses --show-raw-insn
00004 
00005 .*: +file format .*arm.*
00006 
00007 Disassembly of section .text:
00008 0+00 <[^>]+> e12fff10 ?     bx     r0
00009 0+04 <[^>]+> 012fff11 ?     bxeq   r1
00010 0+08 <[^>]+> e15f30b8 ?     ldrh   r3, \[pc, #-8\]      ; 0+08 <[^>]+>
00011 0+0c <[^>]+> e1d540f0 ?     ldrsh  r4, \[r5\]
00012 0+10 <[^>]+> e19140d3 ?     ldrsb  r4, \[r1, r3\]
00013 0+14 <[^>]+> e1b410f4 ?     ldrsh  r1, \[r4, r4\]!
00014 0+18 <[^>]+> 011510d3 ?     ldreqsb       r1, \[r5, -r3\]
00015 0+1c <[^>]+> 109620b7 ?     ldrneh r2, \[r6\], r7
00016 0+20 <[^>]+> 309720f8 ?     ldrccsh       r2, \[r7\], r8
00017 0+24 <[^>]+> e1d32fdf ?     ldrsb  r2, \[r3, #255\]
00018 0+28 <[^>]+> e1541ffa ?     ldrsh  r1, \[r4, #-250\]
00019 0+2c <[^>]+> e1d51fd0 ?     ldrsb  r1, \[r5, #240\]
00020 0+30 <[^>]+> e1cf23b0 ?     strh   r2, \[pc, #48\]      ; 0+68 <[^>]+>
00021 0+34 <[^>]+> 11c330b0 ?     strneh r3, \[r3\]
00022 0+38 <[^>]+> e328f002 ?     msr    CPSR_f, #2    ; 0x2
00023 0+3c <[^>]+> e121f003 ?     msr    CPSR_c, r3
00024 0+40 <[^>]+> e122f004 ?     msr    CPSR_x, r4
00025 0+44 <[^>]+> e124f005 ?     msr    CPSR_s, r5
00026 0+48 <[^>]+> e128f006 ?     msr    CPSR_f, r6
00027 0+4c <[^>]+> e129f007 ?     msr    CPSR_fc, r7
00028 0+50 <[^>]+> e368f004 ?     msr    SPSR_f, #4    ; 0x4
00029 0+54 <[^>]+> e161f008 ?     msr    SPSR_c, r8
00030 0+58 <[^>]+> e162f009 ?     msr    SPSR_x, r9
00031 0+5c <[^>]+> e164f00a ?     msr    SPSR_s, sl
00032 0+60 <[^>]+> e168f00b ?     msr    SPSR_f, fp
00033 0+64 <[^>]+> e169f00c ?     msr    SPSR_fc, ip
00034 0+68 <[^>]+> e1a00000 ?     nop                  \(mov r0,r0\)
00035 0+6c <[^>]+> e1a00000 ?     nop                  \(mov r0,r0\)
00036