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cell-binutils  2.17cvs20070401
am33-2.c
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00001 /* Copyright (C) 2000, 2002 Free Software Foundation
00002  * Contributed by Alexandre Oliva <aoliva@redhat.com>
00003  *
00004  * This file is free software; you can redistribute it and/or modify it
00005  * under the terms of the GNU General Public License as published by
00006  * the Free Software Foundation; either version 2 of the License, or
00007  * (at your option) any later version.
00008  *
00009  * This program is distributed in the hope that it will be useful, but
00010  * WITHOUT ANY WARRANTY; without even the implied warranty of
00011  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
00012  * General Public License for more details.
00013  *
00014  * You should have received a copy of the GNU General Public License
00015  * along with this program; if not, write to the Free Software
00016  * Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
00017  */
00018 
00019 /* Generator of tests for insns introduced in AM33 2.0.  */
00020 
00021 #define INSN_REPEAT 11
00022 
00023 /* See the following file for usage and documentation.  */
00024 #include "../all/test-gen.c"
00025 
00026 /* These are the AM33 registers.  */
00027 const char *am33_regs[] = {
00028   /* These are the canonical names, i.e., those printed by the
00029    * disassembler.  */
00030   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
00031   "a0", "a1", "a2", "a3", "d0", "d1", "d2", "d3",
00032   /* These are aliases that the assembler should also recognize.  */
00033   "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7",
00034   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
00035 };
00036 
00037 /* Signed constants of the given sizes.  */
00038 #define  d8(shift) signed_constant( 8, shift, 1)
00039 #define d16(shift) signed_constant(16, shift, 1)
00040 #define d24(shift) signed_constant(24, shift, 1)
00041 #define d32(shift) signed_constant(32, shift, 1)
00042 #define  u8(shift) unsigned_constant( 8, shift, 1)
00043 #define u24(shift) unsigned_constant(24, shift, 1)
00044 #define a16(shift) absolute_address(16, shift, 1)
00045 
00046 /* Emit an AM33 register shifted by these many words. */
00047 #define amreg(shift) reg_r (am33_regs, shift, 15, mk_get_bits (5u))
00048 #define spreg literal ("sp")
00049 #define fcreg literal ("fpcr")
00050 
00051 /* Emit an AM33-2 FP single-precision register, with the 4 least
00052  * significant bits shifted by shiftlow and the most significant bit
00053  * shifted by shifthigh.  */
00054 int
00055 freg (func_arg *arg, insn_data *data)
00056 #define freg(shiftlow, shifthigh) { freg, { i1: shiftlow, i2: shifthigh } }
00057 {
00058   unsigned val = get_bits (5u);
00059 
00060   data->as_in = data->dis_out = (char*)malloc (3 + ulen (val, 10));
00061   sprintf (data->as_in, "fs%u", val);
00062   data->bits = val;
00063   data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);
00064 
00065   return 0;
00066 }
00067 
00068 /* Emit an AM33-2 FP single-precision register in the ``accumulator''
00069  * range, with the 2 least significant bits shifted by shiftlow and
00070  * the most significant bit shifted by shifthigh. */
00071 int
00072 areg (func_arg *arg, insn_data *data)
00073 #define areg(shiftlow, shifthigh) { areg, { i1: shiftlow, i2: shifthigh } }
00074 {
00075   unsigned val = get_bits (3u);
00076 
00077   data->as_in = data->dis_out = (char*)malloc (4);
00078   sprintf (data->as_in, "fs%u", val);
00079   data->bits = val;
00080   data->bits = ((data->bits & 3) << arg->i1) | ((data->bits >> 2) << arg->i2);
00081 
00082   return 0;
00083 }
00084 
00085 /* Emit an AM33-2 FP double-precision register, with the 4 least
00086  * significant bits shifted by shiftlow and the most significant bit
00087  * shifted by shifthigh. */
00088 int
00089 dreg (func_arg *arg, insn_data *data)
00090 #define dreg(shiftlow, shifthigh) { dreg, { i1: shiftlow, i2: shifthigh } }
00091 {
00092   unsigned val = 2 * get_bits (4u);
00093 
00094   data->as_in = data->dis_out = (char*)malloc (3 + ulen (val, 10));
00095   sprintf (data->as_in, "fd%u", val);
00096   data->bits = val;
00097   data->bits = ((data->bits & 15) << arg->i1) | ((data->bits >> 4) << arg->i2);
00098 
00099   return 0;
00100 }
00101 
00102 /* Emit a signed 8-bit PC-relative offset from the current insn to the
00103  * last emitted label.  */
00104 int
00105 d8pcoff (func_arg *arg, insn_data *data)
00106 #define  d8pcoff(shift) { d8pcoff, { p1: shift } }
00107 {
00108   int diff = insn_size - arg->i1/8 - 1;
00109   int displacement = current_offset - last_label_offset;
00110   char *current_address = malloc (strlen (last_label_name) + 4
00111                               + ulen (displacement, 16) + 1);
00112 
00113   /* Make sure we're not too far from the target.  */
00114   if (displacement > 128)
00115     abort ();
00116 
00117   data->as_in = strdup (last_label_name);
00118 
00119   /* Calculate the address that will be printed by the disassembler as
00120      the target of the jump.  Since it won't take relocations into
00121      account, it will be the insn's own address.  */
00122   if (current_offset == last_label_offset)
00123     strcpy (current_address, last_label_name);
00124   else
00125     sprintf (current_address, "%s\\+0x%x", last_label_name, displacement);
00126 
00127   /* Compute the complete label, including the relocation message
00128      printed as an additional message.  The relocation will point us
00129      to the intended target label plus an offset equal to the offset
00130      of the displacement within the current insn.  We do not account
00131      for the case in which this displacement is zero, since it doesn't
00132      come up on this platform. */
00133   data->dis_out = malloc (8 + 2 + strlen (current_address) + 2
00134                        + 3 + ulen (current_offset + diff, 16) + 19
00135                        + strlen (last_label_name) + 4
00136                        + ulen (diff, 16) + 1);
00137   sprintf (data->dis_out, "0*%x <%s>\n"
00138           "\t\t\t%x: R_MN10300_PCREL8\t%s\\+0x%x",
00139           current_offset, current_address,
00140           current_offset + diff, last_label_name, diff);
00141 
00142   free (current_address);
00143 
00144   return 0;
00145 }
00146 
00147 /* Emit a signed 8-bit PC-relative offset from the current insn to the
00148  * current section.  */
00149 int
00150 d8pcsec (func_arg *arg, insn_data *data)
00151 #define  d8pcsec(shift) { d8pcsec, { p1: shift } }
00152 {
00153   int diff = insn_size - arg->i1/8 - 1;
00154   int displacement = current_offset - last_label_offset;
00155   char *current_address = malloc (strlen (last_label_name) + 4
00156                               + ulen (displacement, 16) + 1);
00157 
00158   /* Make sure we're not too far from the target.  */
00159   if (displacement > 128)
00160     abort ();
00161 
00162   data->as_in = strdup (last_label_name);
00163 
00164   /* Calculate the address that will be printed by the disassembler as
00165      the target of the jump.  Since it won't take relocations into
00166      account, it will be the insn's own address.  */
00167 
00168   if (current_offset == last_label_offset)
00169     strcpy (current_address, last_label_name);
00170   else
00171     sprintf (current_address, "%s\\+0x%x", last_label_name, displacement);
00172 
00173 
00174   /* Compute the complete label, including the relocation message
00175      printed as an additional message.  The relocation will point us
00176      to the intended target label plus an offset equal to the offset
00177      of the displacement within the current insn.  We do not account
00178      for the case in which this displacement is zero, since it doesn't
00179      come up on this platform. */
00180   data->dis_out = malloc (8 + 2 + strlen (current_address) + 2
00181                        + 3 + ulen (current_offset + diff, 16) + 33);
00182   sprintf (data->dis_out, "0*%x <%s>\n"
00183           "\t\t\t%x: R_MN10300_PCREL8\tcondjmp\\+0x2",
00184           current_offset, current_address,
00185           current_offset + diff);
00186 
00187   free (current_address);
00188 
00189   return 0;
00190 }
00191 
00192 /* Convenience wrapper to define_insn.  */
00193 #define def_am_insn(insname, variant, size, word, funcs...) \
00194   define_insn(insname ## _ ## variant, \
00195              insn_size_bits (insname, size, \
00196                            ((unsigned long long)word) << 8*(size-2)), \
00197              tab, \
00198              ## funcs)
00199 #define am_insn(insname, variant) insn (insname ## _ ## variant)
00200 
00201 #define def_bit_insn(insname, word) \
00202   def_am_insn (insname, i8a16, 5, word, \
00203               u8(0), comma, lparen, a16 (8), rparen, tick_random);
00204 #define bit_insn(insname) insn (insname ## _ ## i8a16)
00205 
00206 /* Data cache pre-fetch insns.  */
00207 def_am_insn (dcpf, r,    3, 0xf9a6, lparen, amreg (4), rparen);
00208 def_am_insn (dcpf, sp,   3, 0xf9a7, lparen, spreg, rparen);
00209 def_am_insn (dcpf, rr,   4, 0xfba6,
00210             lparen, amreg(12), comma, amreg (8), rparen, tick_random);
00211 def_am_insn (dcpf, d8r,  4, 0xfba7,
00212             lparen, d8 (0), comma, amreg (12), rparen, tick_random);
00213 def_am_insn (dcpf, d24r, 6, 0xfda7,
00214             lparen, d24(0), comma, amreg (28), rparen, tick_random);
00215 def_am_insn (dcpf, d32r, 7, 0xfe46,
00216             lparen, d32(0), comma, amreg (36), rparen, tick_random);
00217 
00218 /* Define the group of data cache pre-fetch insns.  */
00219 func *dcpf_insns[] = {
00220   am_insn (dcpf, r),
00221   am_insn (dcpf, sp),
00222   am_insn (dcpf, rr),
00223   am_insn (dcpf, d8r),
00224   am_insn (dcpf, d24r),
00225   am_insn (dcpf, d32r),
00226   0
00227 };
00228 
00229 /* Bit operations.  */
00230 def_bit_insn (bset, 0xfe80);
00231 def_bit_insn (bclr, 0xfe81);
00232 def_bit_insn (btst, 0xfe82);
00233 
00234 /* Define the group of bit insns.  */
00235 func *bit_insns[] = {
00236   bit_insn (bset),
00237   bit_insn (bclr),
00238   bit_insn (btst),
00239   0
00240 };
00241 
00242 /* Define the single-precision FP move insns.  */
00243 def_am_insn (fmov, irfs, 3, 0xf920,
00244             lparen, amreg (4), rparen, comma,
00245             freg (0, 8), tick_random);
00246 def_am_insn (fmov, rpfs, 3, 0xf922,
00247             lparen, amreg (4), plus, rparen, comma,
00248             freg (0, 8), tick_random);
00249 def_am_insn (fmov, spfs, 3, 0xf924,
00250             lparen, spreg, rparen, comma, freg (0, 8));
00251 def_am_insn (fmov, vrfs, 3, 0xf926,
00252             amreg (4), comma, freg (0, 8), tick_random);
00253 def_am_insn (fmov, fsir, 3, 0xf930,
00254             freg (4, 9), comma, lparen, amreg (0), rparen, tick_random);
00255 def_am_insn (fmov, fsrp, 3, 0xf931,
00256             freg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random);
00257 def_am_insn (fmov, fssp, 3, 0xf934,
00258             freg (4, 9), comma, lparen, spreg, rparen);
00259 def_am_insn (fmov, fsvr, 3, 0xf935,
00260             freg (4, 9), comma, amreg (0), tick_random);
00261 def_am_insn (fmov, fsfs, 3, 0xf940,
00262             freg (4, 9), comma, freg (0, 8), tick_random);
00263 def_am_insn (fmov, d8rfs, 4, 0xfb20,
00264             lparen, d8 (0), comma, amreg (12), rparen, comma,
00265             freg (8, 16));
00266 def_am_insn (fmov, rpi8fs, 4, 0xfb22,
00267             lparen, amreg (12), plus, comma, d8 (0), rparen, comma,
00268             freg (8, 16));
00269 def_am_insn (fmov, d8spfs, 4, 0xfb24,
00270             lparen, u8 (0), comma, spreg, rparen, comma, freg (8, 16),
00271             tick_random);
00272 def_am_insn (fmov, irrfs, 4, 0xfb27,
00273             lparen, amreg (12), comma, amreg (8), rparen, comma,
00274             freg (4, 1));
00275 def_am_insn (fmov, fsd8r, 4, 0xfb30,
00276             freg (12, 17), comma, lparen, d8 (0), comma, amreg (8), rparen);
00277 def_am_insn (fmov, fsrpi8, 4, 0xfb31,
00278             freg (12, 17), comma,
00279             lparen, amreg (8), plus, comma, d8 (0), rparen);
00280 def_am_insn (fmov, fsd8sp, 4, 0xfb34,
00281             freg (12, 17), comma,
00282             lparen, u8 (0), comma, spreg, rparen, tick_random);
00283 def_am_insn (fmov, fsirr, 4, 0xfb37,
00284             freg (4, 1), comma,
00285             lparen, amreg (12), comma, amreg (8), rparen);
00286 def_am_insn (fmov, d24rfs, 6, 0xfd20,
00287             lparen, d24 (0), comma, amreg (28), rparen, comma, freg (24, 32));
00288 def_am_insn (fmov, rpi24fs, 6, 0xfd22,
00289             lparen, amreg (28), plus, comma, d24 (0), rparen, comma,
00290             freg (24, 32));
00291 def_am_insn (fmov, d24spfs, 6, 0xfd24,
00292             lparen, u24 (0), comma, spreg, rparen, comma,
00293             freg (24, 32), tick_random);
00294 def_am_insn (fmov, fsd24r, 6, 0xfd30,
00295             freg (28, 33), comma, lparen, d24 (0), comma, amreg (24), rparen);
00296 def_am_insn (fmov, fsrpi24, 6, 0xfd31,
00297             freg (28, 33), comma,
00298             lparen, amreg (24), plus, comma, d24 (0), rparen);
00299 def_am_insn (fmov, fsd24sp, 6, 0xfd34,
00300             freg (28, 33), comma,
00301             lparen, u24 (0), comma, spreg, rparen, tick_random);
00302 def_am_insn (fmov, d32rfs, 7, 0xfe20,
00303             lparen, d32 (0), comma, amreg (36), rparen, comma, freg (32, 40));
00304 def_am_insn (fmov, rpi32fs, 7, 0xfe22,
00305             lparen, amreg (36), plus, comma, d32 (0), rparen, comma,
00306             freg (32, 40));
00307 def_am_insn (fmov, d32spfs, 7, 0xfe24,
00308             lparen, d32 (0), comma, spreg, rparen, comma,
00309             freg (32, 40), tick_random);
00310 def_am_insn (fmov, i32fs, 7, 0xfe26,
00311             d32 (0), comma, freg (32, 40), tick_random);
00312 def_am_insn (fmov, fsd32r, 7, 0xfe30,
00313             freg (36, 41), comma, lparen, d32 (0), comma, amreg (32), rparen);
00314 def_am_insn (fmov, fsrpi32, 7, 0xfe31,
00315             freg (36, 41), comma,
00316             lparen, amreg (32), plus, comma, d32 (0), rparen);
00317 def_am_insn (fmov, fsd32sp, 7, 0xfe34,
00318             freg (36, 41), comma,
00319             lparen, d32 (0), comma, spreg, rparen, tick_random);
00320 
00321 /* Define the group of single-precision FP move insns.  */
00322 func *fmovs_insns[] = {
00323   am_insn (fmov, irfs),
00324   am_insn (fmov, rpfs),
00325   am_insn (fmov, spfs),
00326   am_insn (fmov, vrfs),
00327   am_insn (fmov, fsir),
00328   am_insn (fmov, fsrp),
00329   am_insn (fmov, fssp),
00330   am_insn (fmov, fsvr),
00331   am_insn (fmov, fsfs),
00332   am_insn (fmov, d8rfs),
00333   am_insn (fmov, rpi8fs),
00334   am_insn (fmov, d8spfs),
00335   am_insn (fmov, irrfs),
00336   am_insn (fmov, fsd8r),
00337   am_insn (fmov, fsrpi8),
00338   am_insn (fmov, fsd8sp),
00339   am_insn (fmov, fsirr),
00340   am_insn (fmov, d24rfs),
00341   am_insn (fmov, rpi24fs),
00342   am_insn (fmov, d24spfs),
00343   am_insn (fmov, fsd24r),
00344   am_insn (fmov, fsrpi24),
00345   am_insn (fmov, fsd24sp),
00346   am_insn (fmov, d32rfs),
00347   am_insn (fmov, rpi32fs),
00348   am_insn (fmov, d32spfs),
00349   am_insn (fmov, i32fs),
00350   am_insn (fmov, fsd32r),
00351   am_insn (fmov, fsrpi32),
00352   am_insn (fmov, fsd32sp),
00353   0
00354 };
00355 
00356 /* Define the double-precision FP move insns.  */
00357 def_am_insn (fmov, irfd, 3, 0xf9a0,
00358             lparen, amreg (4), rparen, comma, dreg (0, 8), tick_random);
00359 def_am_insn (fmov, rpfd, 3, 0xf9a2,
00360             lparen, amreg (4), plus, rparen, comma, dreg (0, 8), tick_random);
00361 def_am_insn (fmov, spfd, 3, 0xf9a4,
00362             lparen, spreg, rparen, comma, dreg (0, 8));
00363 def_am_insn (fmov, fdir, 3, 0xf9b0,
00364             dreg (4, 9), comma, lparen, amreg (0), rparen, tick_random);
00365 def_am_insn (fmov, fdrp, 3, 0xf9b1,
00366             dreg (4, 9), comma, lparen, amreg (0), plus, rparen, tick_random);
00367 def_am_insn (fmov, fdsp, 3, 0xf9b4,
00368             dreg (4, 9), comma, lparen, spreg, rparen);
00369 def_am_insn (fmov, fdfd, 3, 0xf9c0,
00370             dreg (4, 9), comma, dreg (0, 8), tick_random);
00371 def_am_insn (fmov, irrfd, 4, 0xfb47,
00372             lparen, amreg (12), comma, amreg (8), rparen, comma, dreg (4, 1));
00373 def_am_insn (fmov, fdirr, 4, 0xfb57,
00374             dreg (4, 1), comma, lparen, amreg (12), comma, amreg (8), rparen);
00375 def_am_insn (fmov, d8rfd, 4, 0xfba0,
00376             lparen, d8 (0), comma, amreg (12), rparen, comma, dreg (8, 16));
00377 def_am_insn (fmov, rpi8fd, 4, 0xfba2,
00378             lparen, amreg (12), plus, comma, d8 (0), rparen, comma,
00379             dreg (8, 16));
00380 def_am_insn (fmov, d8spfd, 4, 0xfba4,
00381             lparen, u8 (0), comma, spreg, rparen, comma,
00382             dreg (8, 16), tick_random);
00383 def_am_insn (fmov, fdd8r, 4, 0xfbb0,
00384             dreg (12, 17), comma, lparen, d8 (0), comma, amreg (8), rparen);
00385 def_am_insn (fmov, fdrpi8, 4, 0xfbb1,
00386             dreg (12, 17), comma,
00387             lparen, amreg (8), plus, comma, d8 (0), rparen);
00388 def_am_insn (fmov, fdi8sp, 4, 0xfbb4,
00389             dreg (12, 17), comma,
00390             lparen, u8 (0), comma, spreg, rparen, tick_random);
00391 def_am_insn (fmov, d24rfd, 6, 0xfda0,
00392             lparen, d24 (0), comma, amreg (28), rparen, comma, dreg (24, 32));
00393 def_am_insn (fmov, rpi24fd, 6, 0xfda2,
00394             lparen, amreg (28), plus, comma, d24 (0), rparen, comma,
00395             dreg (24, 32));
00396 def_am_insn (fmov, d24spfd, 6, 0xfda4,
00397             lparen, u24 (0), comma, spreg, rparen, comma,
00398             dreg (24, 32), tick_random);
00399 def_am_insn (fmov, fdd24r, 6, 0xfdb0,
00400             dreg (28, 33), comma,
00401             lparen, d24 (0), comma, amreg (24), rparen);
00402 def_am_insn (fmov, fdrpi24, 6, 0xfdb1,
00403             dreg (28, 33), comma,
00404             lparen, amreg (24), plus, comma, d24 (0), rparen);
00405 def_am_insn (fmov, fdd24sp, 6, 0xfdb4,
00406             dreg (28, 33), comma,
00407             lparen, u24 (0), comma, spreg, rparen, tick_random);
00408 def_am_insn (fmov, d32rfd, 7, 0xfe40,
00409             lparen, d32 (0), comma, amreg (36), rparen, comma, dreg (32, 40));
00410 def_am_insn (fmov, rpi32fd, 7, 0xfe42,
00411             lparen, amreg (36), plus, comma, d32 (0), rparen, comma,
00412             dreg (32, 40));
00413 def_am_insn (fmov, d32spfd, 7, 0xfe44,
00414             lparen, d32 (0), comma, spreg, rparen, comma,
00415             dreg (32, 40), tick_random);
00416 def_am_insn (fmov, fdd32r, 7, 0xfe50,
00417             dreg (36, 41), comma,
00418             lparen, d32 (0), comma, amreg (32), rparen);
00419 def_am_insn (fmov, fdrpi32, 7, 0xfe51,
00420             dreg (36, 41), comma,
00421             lparen, amreg (32), plus, comma, d32 (0), rparen);
00422 def_am_insn (fmov, fdd32sp, 7, 0xfe54,
00423             dreg (36, 41), comma,
00424             lparen, d32 (0), comma, spreg, rparen, tick_random);
00425 
00426 /* Define the group of double-precision FP move insns.  */
00427 func *fmovd_insns[] = {
00428   am_insn (fmov, irfd),
00429   am_insn (fmov, rpfd),
00430   am_insn (fmov, spfd),
00431   am_insn (fmov, fdir),
00432   am_insn (fmov, fdrp),
00433   am_insn (fmov, fdsp),
00434   am_insn (fmov, fdfd),
00435   am_insn (fmov, irrfd),
00436   am_insn (fmov, fdirr),
00437   am_insn (fmov, d8rfd),
00438   am_insn (fmov, rpi8fd),
00439   am_insn (fmov, d8spfd),
00440   am_insn (fmov, fdd8r),
00441   am_insn (fmov, fdrpi8),
00442   am_insn (fmov, fdi8sp),
00443   am_insn (fmov, d24rfd),
00444   am_insn (fmov, rpi24fd),
00445   am_insn (fmov, d24spfd),
00446   am_insn (fmov, fdd24r),
00447   am_insn (fmov, fdrpi24),
00448   am_insn (fmov, fdd24sp),
00449   am_insn (fmov, d32rfd),
00450   am_insn (fmov, rpi32fd),
00451   am_insn (fmov, d32spfd),
00452   am_insn (fmov, fdd32r),
00453   am_insn (fmov, fdrpi32),
00454   am_insn (fmov, fdd32sp),
00455   0
00456 };
00457 
00458 /* Define fmov FPCR insns.  */
00459 def_am_insn (fmov, vrfc, 3, 0xf9b5,
00460             amreg (4), comma, fcreg);
00461 def_am_insn (fmov, fcvr, 3, 0xf9b7,
00462             fcreg, comma, amreg (0));
00463 def_am_insn (fmov, i32fc, 6, 0xfdb5,
00464             d32 (0), comma, fcreg);
00465 
00466 /* Define the group of FPCR move insns.  */
00467 func *fmovc_insns[] = {
00468   am_insn (fmov, vrfc),
00469   am_insn (fmov, fcvr),
00470   am_insn (fmov, i32fc),
00471   0
00472 };
00473 
00474 /* Define single-precision floating-point arithmetic insns.  */
00475 def_am_insn (fabs, fs, 3, 0xf944, freg (0, 8));
00476 def_am_insn (fabs, fsfs, 4, 0xfb44,
00477             freg (12, 3), comma, freg (4, 1), tick_random);
00478 def_am_insn (fneg, fs, 3, 0xf946, freg (0, 8));
00479 def_am_insn (fneg, fsfs, 4, 0xfb46,
00480             freg (12, 3), comma, freg (4, 1), tick_random);
00481 def_am_insn (frsqrt, fs, 3, 0xf950, freg (0, 8));
00482 def_am_insn (frsqrt, fsfs, 4, 0xfb50,
00483             freg (12, 3), comma, freg (4, 1), tick_random);
00484 def_am_insn (fsqrt, fs, 3, 0xf952, freg (0, 8));
00485 def_am_insn (fsqrt, fsfs, 4, 0xfb54,
00486             freg (12, 3), comma, freg (4, 1), tick_random);
00487 def_am_insn (fcmp, fsfs, 3, 0xf954,
00488             freg (4, 9), comma, freg (0, 8), tick_random);
00489 def_am_insn (fcmp, i32fs, 7, 0xfe35,
00490             d32 (0), comma, freg (36, 41), tick_random);
00491 def_am_insn (fadd, fsfs, 3, 0xf960,
00492             freg (4, 9), comma, freg (0, 8), tick_random);
00493 def_am_insn (fadd, fsfsfs, 4, 0xfb60,
00494             freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));
00495 def_am_insn (fadd, i32fsfs, 7, 0xfe60,
00496             d32 (0), comma, freg (36, 41), comma, freg (32, 40));
00497 def_am_insn (fsub, fsfs, 3, 0xf964,
00498             freg (4, 9), comma, freg (0, 8), tick_random);
00499 def_am_insn (fsub, fsfsfs, 4, 0xfb64,
00500             freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));
00501 def_am_insn (fsub, i32fsfs, 7, 0xfe64,
00502             d32 (0), comma, freg (36, 41), comma, freg (32, 40));
00503 def_am_insn (fmul, fsfs, 3, 0xf970,
00504             freg (4, 9), comma, freg (0, 8), tick_random);
00505 def_am_insn (fmul, fsfsfs, 4, 0xfb70,
00506             freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));
00507 def_am_insn (fmul, i32fsfs, 7, 0xfe70,
00508             d32 (0), comma, freg (36, 41), comma, freg (32, 40));
00509 def_am_insn (fdiv, fsfs, 3, 0xf974,
00510             freg (4, 9), comma, freg (0, 8), tick_random);
00511 def_am_insn (fdiv, fsfsfs, 4, 0xfb74,
00512             freg (12, 3), comma, freg (8, 2), comma, freg (4, 1));
00513 def_am_insn (fdiv, i32fsfs, 7, 0xfe74,
00514             d32 (0), comma, freg (36, 41), comma, freg (32, 40));
00515 
00516 /* Define the group of single-precision floating-point arithmetic insns.  */
00517 func *sfparith_insns[] = {
00518   am_insn (fabs, fs),
00519   am_insn (fabs, fsfs),
00520   am_insn (fneg, fs),
00521   am_insn (fneg, fsfs),
00522   am_insn (frsqrt, fs),
00523   am_insn (frsqrt, fsfs),
00524   am_insn (fsqrt, fs),
00525   am_insn (fsqrt, fsfs),
00526   am_insn (fcmp, fsfs),
00527   am_insn (fcmp, i32fs),
00528   am_insn (fadd, fsfs),
00529   am_insn (fadd, fsfsfs),
00530   am_insn (fadd, i32fsfs),
00531   am_insn (fsub, fsfs),
00532   am_insn (fsub, fsfsfs),
00533   am_insn (fsub, i32fsfs),
00534   am_insn (fmul, fsfs),
00535   am_insn (fmul, fsfsfs),
00536   am_insn (fmul, i32fsfs),
00537   am_insn (fdiv, fsfs),
00538   am_insn (fdiv, fsfsfs),
00539   am_insn (fdiv, i32fsfs),
00540   0
00541 };
00542 
00543 /* Define floating-point accumulator arithmetic insns.  */
00544 def_am_insn (fmadd, , 4, 0xfb80,
00545             freg (12, 3), comma, freg (8, 2), comma,
00546             freg (4, 1), comma, areg (16, 0), tick_random);
00547 def_am_insn (fmsub, , 4, 0xfb84,
00548             freg (12, 3), comma, freg (8, 2), comma,
00549             freg (4, 1), comma, areg (16, 0), tick_random);
00550 def_am_insn (fnmadd, , 4, 0xfb90,
00551             freg (12, 3), comma, freg (8, 2), comma,
00552             freg (4, 1), comma, areg (16, 0), tick_random);
00553 def_am_insn (fnmsub, , 4, 0xfb94,
00554             freg (12, 3), comma, freg (8, 2), comma,
00555             freg (4, 1), comma, areg (16, 0), tick_random);
00556 
00557 /* Define the group of floating-point accumulator arithmetic insns.  */
00558 func *fpacc_insns[] = {
00559   am_insn (fmadd, ),
00560   am_insn (fmsub, ),
00561   am_insn (fnmadd, ),
00562   am_insn (fnmsub, ),
00563   0
00564 };
00565 
00566 /* Define double-precision floating-point arithmetic insns.  */
00567 def_am_insn (fabs, fd, 3, 0xf9c4, dreg (0, 8));
00568 def_am_insn (fabs, fdfd, 4, 0xfbc4,
00569             dreg (12, 3), comma, dreg (4, 1), tick_random);
00570 def_am_insn (fneg, fd, 3, 0xf9c6, dreg (0, 8));
00571 def_am_insn (fneg, fdfd, 4, 0xfbc6,
00572             dreg (12, 3), comma, dreg (4, 1), tick_random);
00573 def_am_insn (frsqrt, fd, 3, 0xf9d0, dreg (0, 8));
00574 def_am_insn (frsqrt, fdfd, 4, 0xfbd0,
00575             dreg (12, 3), comma, dreg (4, 1), tick_random);
00576 def_am_insn (fsqrt, fd, 3, 0xf9d2, dreg (0, 8));
00577 def_am_insn (fsqrt, fdfd, 4, 0xfbd4,
00578             dreg (12, 3), comma, dreg (4, 1), tick_random);
00579 def_am_insn (fcmp, fdfd, 3, 0xf9d4,
00580             dreg (4, 9), comma, dreg (0, 8), tick_random);
00581 def_am_insn (fadd, fdfd, 3, 0xf9e0,
00582             dreg (4, 9), comma, dreg (0, 8), tick_random);
00583 def_am_insn (fadd, fdfdfd, 4, 0xfbe0,
00584             dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));
00585 def_am_insn (fsub, fdfd, 3, 0xf9e4,
00586             dreg (4, 9), comma, dreg (0, 8), tick_random);
00587 def_am_insn (fsub, fdfdfd, 4, 0xfbe4,
00588             dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));
00589 def_am_insn (fmul, fdfd, 3, 0xf9f0,
00590             dreg (4, 9), comma, dreg (0, 8), tick_random);
00591 def_am_insn (fmul, fdfdfd, 4, 0xfbf0,
00592             dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));
00593 def_am_insn (fdiv, fdfd, 3, 0xf9f4,
00594             dreg (4, 9), comma, dreg (0, 8), tick_random);
00595 def_am_insn (fdiv, fdfdfd, 4, 0xfbf4,
00596             dreg (12, 3), comma, dreg (8, 2), comma, dreg (4, 1));
00597 
00598 /* Define the group of double-precision floating-point arithmetic insns.  */
00599 func *dfparith_insns[] = {
00600   am_insn (fabs, fd),
00601   am_insn (fabs, fdfd),
00602   am_insn (fneg, fd),
00603   am_insn (fneg, fdfd),
00604   am_insn (frsqrt, fd),
00605   am_insn (frsqrt, fdfd),
00606   am_insn (fsqrt, fd),
00607   am_insn (fsqrt, fdfd),
00608   am_insn (fcmp, fdfd),
00609   am_insn (fadd, fdfd),
00610   am_insn (fadd, fdfdfd),
00611   am_insn (fsub, fdfd),
00612   am_insn (fsub, fdfdfd),
00613   am_insn (fmul, fdfd),
00614   am_insn (fmul, fdfdfd),
00615   am_insn (fdiv, fdfd),
00616   am_insn (fdiv, fdfdfd),
00617   0
00618 };
00619 
00620 /* Define floating-point conversion insns.  */
00621 def_am_insn (ftoi, fsfs, 4, 0xfb40,
00622             freg (12, 3), comma, freg (4, 1), tick_random);
00623 def_am_insn (itof, fsfs, 4, 0xfb42,
00624             freg (12, 3), comma, freg (4, 1), tick_random);
00625 def_am_insn (ftod, fsfd, 4, 0xfb52,
00626             freg (12, 3), comma, dreg (4, 1), tick_random);
00627 def_am_insn (dtof, fdfs, 4, 0xfb56,
00628             dreg (12, 3), comma, freg (4, 1), tick_random);
00629 
00630 /* Define the group of floating-point conversion insns.  */
00631 func *fpconv_insns[] = {
00632   am_insn (ftoi, fsfs),
00633   am_insn (itof, fsfs),
00634   am_insn (ftod, fsfd),
00635   am_insn (dtof, fdfs),
00636   0
00637 };
00638 
00639 /* Define conditional jump insns.  */
00640 def_am_insn (fbeq, , 3, 0xf8d0, d8pcsec (0));
00641 def_am_insn (fbne, , 3, 0xf8d1, d8pcsec (0));
00642 def_am_insn (fbgt, , 3, 0xf8d2, d8pcsec (0));
00643 def_am_insn (fbge, , 3, 0xf8d3, d8pcsec (0));
00644 def_am_insn (fblt, , 3, 0xf8d4, d8pcsec (0));
00645 def_am_insn (fble, , 3, 0xf8d5, d8pcsec (0));
00646 def_am_insn (fbuo, , 3, 0xf8d6, d8pcsec (0));
00647 def_am_insn (fblg, , 3, 0xf8d7, d8pcsec (0));
00648 def_am_insn (fbleg,, 3, 0xf8d8, d8pcsec (0));
00649 def_am_insn (fbug, , 3, 0xf8d9, d8pcsec (0));
00650 def_am_insn (fbuge,, 3, 0xf8da, d8pcsec (0));
00651 def_am_insn (fbul, , 3, 0xf8db, d8pcsec (0));
00652 def_am_insn (fbule,, 3, 0xf8dc, d8pcsec (0));
00653 def_am_insn (fbue, , 3, 0xf8dd, d8pcsec (0));
00654 def_am_insn (fleq, , 2, 0xf0d0, nothing);
00655 def_am_insn (flne, , 2, 0xf0d1, nothing);
00656 def_am_insn (flgt, , 2, 0xf0d2, nothing);
00657 def_am_insn (flge, , 2, 0xf0d3, nothing);
00658 def_am_insn (fllt, , 2, 0xf0d4, nothing);
00659 def_am_insn (flle, , 2, 0xf0d5, nothing);
00660 def_am_insn (fluo, , 2, 0xf0d6, nothing);
00661 def_am_insn (fllg, , 2, 0xf0d7, nothing);
00662 def_am_insn (flleg,, 2, 0xf0d8, nothing);
00663 def_am_insn (flug, , 2, 0xf0d9, nothing);
00664 def_am_insn (fluge,, 2, 0xf0da, nothing);
00665 def_am_insn (flul, , 2, 0xf0db, nothing);
00666 def_am_insn (flule,, 2, 0xf0dc, nothing);
00667 def_am_insn (flue, , 2, 0xf0dd, nothing);
00668 
00669 /* Define the group of conditional jump insns.  */
00670 func *condjmp_insns[] = {
00671   am_insn (fbeq, ),
00672   am_insn (fbne, ),
00673   am_insn (fbgt, ),
00674   am_insn (fbge, ),
00675   am_insn (fblt, ),
00676   am_insn (fble, ),
00677   am_insn (fbuo, ),
00678   am_insn (fblg, ),
00679   am_insn (fbleg, ),
00680   am_insn (fbug, ),
00681   am_insn (fbuge, ),
00682   am_insn (fbul, ),
00683   am_insn (fbule, ),
00684   am_insn (fbue, ),
00685   am_insn (fleq, ),
00686   am_insn (flne, ),
00687   am_insn (flgt, ),
00688   am_insn (flge, ),
00689   am_insn (fllt, ),
00690   am_insn (flle, ),
00691   am_insn (fluo, ),
00692   am_insn (fllg, ),
00693   am_insn (flleg, ),
00694   am_insn (flug, ),
00695   am_insn (fluge, ),
00696   am_insn (flul, ),
00697   am_insn (flule, ),
00698   am_insn (flue, ),
00699   0
00700 };
00701 
00702 /* Define the set of all groups.  */
00703 group_t
00704 groups[] = {
00705   { "dcpf", dcpf_insns },
00706   { "bit", bit_insns },
00707   { "fmovs", fmovs_insns },
00708   { "fmovd", fmovd_insns },
00709   { "fmovc", fmovc_insns },
00710   { "sfparith", sfparith_insns },
00711   { "fpacc", fpacc_insns },
00712   { "dfparith", dfparith_insns },
00713   { "fpconv", fpconv_insns },
00714   { "condjmp", condjmp_insns },
00715   { 0 }
00716 };
00717 
00718 int
00719 main(int argc, char *argv[])
00720 {
00721   FILE *as_in = stdout, *dis_out = stderr;
00722 
00723   /* Check whether we're filtering insns.  */
00724   if (argc > 1)
00725     skip_list = argv + 1;
00726 
00727   /* Output assembler header.  */
00728   fputs ("\t.text\n"
00729         "\t.am33_2\n",
00730         as_in);
00731   /* Output comments for the testsuite-driver and the initial
00732    * disassembler output. */
00733   fputs ("#objdump: -dr --prefix-address --show-raw-insn\n"
00734         "#name: AM33/2.0\n"
00735         "\n"
00736         ".*: +file format.*elf32-mn10300.*\n"
00737         "\n"
00738         "Disassembly of section .text:\n",
00739         dis_out);
00740 
00741   /* Now emit all (selected) insns.  */
00742   output_groups (groups, as_in, dis_out);
00743 
00744   exit (0);
00745 }