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alpha-opc.c
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00001 /* alpha-opc.c -- Alpha AXP opcode list
00002    Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
00003    Free Software Foundation, Inc.
00004    Contributed by Richard Henderson <rth@cygnus.com>,
00005    patterned after the PPC opcode handling written by Ian Lance Taylor.
00006 
00007    This file is part of GDB, GAS, and the GNU binutils.
00008 
00009    GDB, GAS, and the GNU binutils are free software; you can redistribute
00010    them and/or modify them under the terms of the GNU General Public
00011    License as published by the Free Software Foundation; either version
00012    2, or (at your option) any later version.
00013 
00014    GDB, GAS, and the GNU binutils are distributed in the hope that they
00015    will be useful, but WITHOUT ANY WARRANTY; without even the implied
00016    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00017    the GNU General Public License for more details.
00018 
00019    You should have received a copy of the GNU General Public License
00020    along with this file; see the file COPYING.  If not, write to the
00021    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
00022    02110-1301, USA.  */
00023 
00024 #include <stdio.h>
00025 #include "sysdep.h"
00026 #include "opcode/alpha.h"
00027 #include "bfd.h"
00028 #include "opintl.h"
00029 
00030 /* This file holds the Alpha AXP opcode table.  The opcode table includes
00031    almost all of the extended instruction mnemonics.  This permits the
00032    disassembler to use them, and simplifies the assembler logic, at the
00033    cost of increasing the table size.  The table is strictly constant
00034    data, so the compiler should be able to put it in the text segment.
00035 
00036    This file also holds the operand table.  All knowledge about inserting
00037    and extracting operands from instructions is kept in this file.
00038 
00039    The information for the base instruction set was compiled from the
00040    _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE,
00041    version 2.
00042 
00043    The information for the post-ev5 architecture extensions BWX, CIX and
00044    MAX came from version 3 of this same document, which is also available
00045    on-line at http://ftp.digital.com/pub/Digital/info/semiconductor
00046    /literature/alphahb2.pdf
00047 
00048    The information for the EV4 PALcode instructions was compiled from
00049    _DECchip 21064 and DECchip 21064A Alpha AXP Microprocessors Hardware
00050    Reference Manual_, Digital Order Number EC-Q9ZUA-TE, preliminary
00051    revision dated June 1994.
00052 
00053    The information for the EV5 PALcode instructions was compiled from
00054    _Alpha 21164 Microprocessor Hardware Reference Manual_, Digital
00055    Order Number EC-QAEQB-TE, preliminary revision dated April 1995.  */
00056 
00057 /* The RB field when it is the same as the RA field in the same insn.
00058    This operand is marked fake.  The insertion function just copies
00059    the RA field into the RB field, and the extraction function just
00060    checks that the fields are the same. */
00061 
00062 static unsigned
00063 insert_rba (unsigned insn,
00064            int value ATTRIBUTE_UNUSED,
00065            const char **errmsg ATTRIBUTE_UNUSED)
00066 {
00067   return insn | (((insn >> 21) & 0x1f) << 16);
00068 }
00069 
00070 static int
00071 extract_rba (unsigned insn, int *invalid)
00072 {
00073   if (invalid != (int *) NULL
00074       && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
00075     *invalid = 1;
00076   return 0;
00077 }
00078 
00079 /* The same for the RC field.  */
00080 
00081 static unsigned
00082 insert_rca (unsigned insn,
00083            int value ATTRIBUTE_UNUSED,
00084            const char **errmsg ATTRIBUTE_UNUSED)
00085 {
00086   return insn | ((insn >> 21) & 0x1f);
00087 }
00088 
00089 static int
00090 extract_rca (unsigned insn, int *invalid)
00091 {
00092   if (invalid != (int *) NULL
00093       && ((insn >> 21) & 0x1f) != (insn & 0x1f))
00094     *invalid = 1;
00095   return 0;
00096 }
00097 
00098 /* Fake arguments in which the registers must be set to ZERO.  */
00099 
00100 static unsigned
00101 insert_za (unsigned insn,
00102           int value ATTRIBUTE_UNUSED,
00103           const char **errmsg ATTRIBUTE_UNUSED)
00104 {
00105   return insn | (31 << 21);
00106 }
00107 
00108 static int
00109 extract_za (unsigned insn, int *invalid)
00110 {
00111   if (invalid != (int *) NULL && ((insn >> 21) & 0x1f) != 31)
00112     *invalid = 1;
00113   return 0;
00114 }
00115 
00116 static unsigned
00117 insert_zb (unsigned insn,
00118           int value ATTRIBUTE_UNUSED,
00119           const char **errmsg ATTRIBUTE_UNUSED)
00120 {
00121   return insn | (31 << 16);
00122 }
00123 
00124 static int
00125 extract_zb (unsigned insn, int *invalid)
00126 {
00127   if (invalid != (int *) NULL && ((insn >> 16) & 0x1f) != 31)
00128     *invalid = 1;
00129   return 0;
00130 }
00131 
00132 static unsigned
00133 insert_zc (unsigned insn,
00134           int value ATTRIBUTE_UNUSED,
00135           const char **errmsg ATTRIBUTE_UNUSED)
00136 {
00137   return insn | 31;
00138 }
00139 
00140 static int
00141 extract_zc (unsigned insn, int *invalid)
00142 {
00143   if (invalid != (int *) NULL && (insn & 0x1f) != 31)
00144     *invalid = 1;
00145   return 0;
00146 }
00147 
00148 
00149 /* The displacement field of a Branch format insn.  */
00150 
00151 static unsigned
00152 insert_bdisp (unsigned insn, int value, const char **errmsg)
00153 {
00154   if (errmsg != (const char **)NULL && (value & 3))
00155     *errmsg = _("branch operand unaligned");
00156   return insn | ((value / 4) & 0x1FFFFF);
00157 }
00158 
00159 static int
00160 extract_bdisp (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
00161 {
00162   return 4 * (((insn & 0x1FFFFF) ^ 0x100000) - 0x100000);
00163 }
00164 
00165 /* The hint field of a JMP/JSR insn.  */
00166 
00167 static unsigned
00168 insert_jhint (unsigned insn, int value, const char **errmsg)
00169 {
00170   if (errmsg != (const char **)NULL && (value & 3))
00171     *errmsg = _("jump hint unaligned");
00172   return insn | ((value / 4) & 0x3FFF);
00173 }
00174 
00175 static int
00176 extract_jhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
00177 {
00178   return 4 * (((insn & 0x3FFF) ^ 0x2000) - 0x2000);
00179 }
00180 
00181 /* The hint field of an EV6 HW_JMP/JSR insn.  */
00182 
00183 static unsigned
00184 insert_ev6hwjhint (unsigned insn, int value, const char **errmsg)
00185 {
00186   if (errmsg != (const char **)NULL && (value & 3))
00187     *errmsg = _("jump hint unaligned");
00188   return insn | ((value / 4) & 0x1FFF);
00189 }
00190 
00191 static int
00192 extract_ev6hwjhint (unsigned insn, int *invalid ATTRIBUTE_UNUSED)
00193 {
00194   return 4 * (((insn & 0x1FFF) ^ 0x1000) - 0x1000);
00195 }
00196 
00197 /* The operands table.   */
00198 
00199 const struct alpha_operand alpha_operands[] =
00200 {
00201   /* The fields are bits, shift, insert, extract, flags */
00202   /* The zero index is used to indicate end-of-list */
00203 #define UNUSED              0
00204   { 0, 0, 0, 0, 0, 0 },
00205 
00206   /* The plain integer register fields.  */
00207 #define RA           (UNUSED + 1)
00208   { 5, 21, 0, AXP_OPERAND_IR, 0, 0 },
00209 #define RB           (RA + 1)
00210   { 5, 16, 0, AXP_OPERAND_IR, 0, 0 },
00211 #define RC           (RB + 1)
00212   { 5, 0, 0, AXP_OPERAND_IR, 0, 0 },
00213 
00214   /* The plain fp register fields.  */
00215 #define FA           (RC + 1)
00216   { 5, 21, 0, AXP_OPERAND_FPR, 0, 0 },
00217 #define FB           (FA + 1)
00218   { 5, 16, 0, AXP_OPERAND_FPR, 0, 0 },
00219 #define FC           (FB + 1)
00220   { 5, 0, 0, AXP_OPERAND_FPR, 0, 0 },
00221 
00222   /* The integer registers when they are ZERO.  */
00223 #define ZA           (FC + 1)
00224   { 5, 21, 0, AXP_OPERAND_FAKE, insert_za, extract_za },
00225 #define ZB           (ZA + 1)
00226   { 5, 16, 0, AXP_OPERAND_FAKE, insert_zb, extract_zb },
00227 #define ZC           (ZB + 1)
00228   { 5, 0, 0, AXP_OPERAND_FAKE, insert_zc, extract_zc },
00229 
00230   /* The RB field when it needs parentheses.  */
00231 #define PRB          (ZC + 1)
00232   { 5, 16, 0, AXP_OPERAND_IR|AXP_OPERAND_PARENS, 0, 0 },
00233 
00234   /* The RB field when it needs parentheses _and_ a preceding comma.  */
00235 #define CPRB         (PRB + 1)
00236   { 5, 16, 0,
00237     AXP_OPERAND_IR|AXP_OPERAND_PARENS|AXP_OPERAND_COMMA, 0, 0 },
00238 
00239   /* The RB field when it must be the same as the RA field.  */
00240 #define RBA          (CPRB + 1)
00241   { 5, 16, 0, AXP_OPERAND_FAKE, insert_rba, extract_rba },
00242 
00243   /* The RC field when it must be the same as the RB field.  */
00244 #define RCA          (RBA + 1)
00245   { 5, 0, 0, AXP_OPERAND_FAKE, insert_rca, extract_rca },
00246 
00247   /* The RC field when it can *default* to RA.  */
00248 #define DRC1         (RCA + 1)
00249   { 5, 0, 0,
00250     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
00251 
00252   /* The RC field when it can *default* to RB.  */
00253 #define DRC2         (DRC1 + 1)
00254   { 5, 0, 0,
00255     AXP_OPERAND_IR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
00256 
00257   /* The FC field when it can *default* to RA.  */
00258 #define DFC1         (DRC2 + 1)
00259   { 5, 0, 0,
00260     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_FIRST, 0, 0 },
00261 
00262   /* The FC field when it can *default* to RB.  */
00263 #define DFC2         (DFC1 + 1)
00264   { 5, 0, 0,
00265     AXP_OPERAND_FPR|AXP_OPERAND_DEFAULT_SECOND, 0, 0 },
00266 
00267   /* The unsigned 8-bit literal of Operate format insns.  */
00268 #define LIT          (DFC2 + 1)
00269   { 8, 13, -LIT, AXP_OPERAND_UNSIGNED, 0, 0 },
00270 
00271   /* The signed 16-bit displacement of Memory format insns.  From here
00272      we can't tell what relocation should be used, so don't use a default.  */
00273 #define MDISP        (LIT + 1)
00274   { 16, 0, -MDISP, AXP_OPERAND_SIGNED, 0, 0 },
00275 
00276   /* The signed "23-bit" aligned displacement of Branch format insns.  */
00277 #define BDISP        (MDISP + 1)
00278   { 21, 0, BFD_RELOC_23_PCREL_S2, 
00279     AXP_OPERAND_RELATIVE, insert_bdisp, extract_bdisp },
00280 
00281   /* The 26-bit PALcode function */
00282 #define PALFN        (BDISP + 1)
00283   { 26, 0, -PALFN, AXP_OPERAND_UNSIGNED, 0, 0 },
00284 
00285   /* The optional signed "16-bit" aligned displacement of the JMP/JSR hint.  */
00286 #define JMPHINT             (PALFN + 1)
00287   { 14, 0, BFD_RELOC_ALPHA_HINT,
00288     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
00289     insert_jhint, extract_jhint },
00290 
00291   /* The optional hint to RET/JSR_COROUTINE.  */
00292 #define RETHINT             (JMPHINT + 1)
00293   { 14, 0, -RETHINT,
00294     AXP_OPERAND_UNSIGNED|AXP_OPERAND_DEFAULT_ZERO, 0, 0 },
00295 
00296   /* The 12-bit displacement for the ev[46] hw_{ld,st} (pal1b/pal1f) insns.  */
00297 #define EV4HWDISP    (RETHINT + 1)
00298 #define EV6HWDISP    (EV4HWDISP)
00299   { 12, 0, -EV4HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
00300 
00301   /* The 5-bit index for the ev4 hw_m[ft]pr (pal19/pal1d) insns.  */
00302 #define EV4HWINDEX   (EV4HWDISP + 1)
00303   { 5, 0, -EV4HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
00304 
00305   /* The 8-bit index for the oddly unqualified hw_m[tf]pr insns
00306      that occur in DEC PALcode.  */
00307 #define EV4EXTHWINDEX       (EV4HWINDEX + 1)
00308   { 8, 0, -EV4EXTHWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
00309 
00310   /* The 10-bit displacement for the ev5 hw_{ld,st} (pal1b/pal1f) insns.  */
00311 #define EV5HWDISP    (EV4EXTHWINDEX + 1)
00312   { 10, 0, -EV5HWDISP, AXP_OPERAND_SIGNED, 0, 0 },
00313 
00314   /* The 16-bit index for the ev5 hw_m[ft]pr (pal19/pal1d) insns.  */
00315 #define EV5HWINDEX   (EV5HWDISP + 1)
00316   { 16, 0, -EV5HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
00317 
00318   /* The 16-bit combined index/scoreboard mask for the ev6
00319      hw_m[ft]pr (pal19/pal1d) insns.  */
00320 #define EV6HWINDEX   (EV5HWINDEX + 1)
00321   { 16, 0, -EV6HWINDEX, AXP_OPERAND_UNSIGNED, 0, 0 },
00322 
00323   /* The 13-bit branch hint for the ev6 hw_jmp/jsr (pal1e) insn.  */
00324 #define EV6HWJMPHINT (EV6HWINDEX+ 1)
00325   { 8, 0, -EV6HWJMPHINT,
00326     AXP_OPERAND_RELATIVE|AXP_OPERAND_DEFAULT_ZERO|AXP_OPERAND_NOOVERFLOW,
00327     insert_ev6hwjhint, extract_ev6hwjhint }
00328 };
00329 
00330 const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operands);
00331 
00332 
00333 /* Macros used to form opcodes.  */
00334 
00335 /* The main opcode.  */
00336 #define OP(x)        (((x) & 0x3F) << 26)
00337 #define OP_MASK             0xFC000000
00338 
00339 /* Branch format instructions.  */
00340 #define BRA_(oo)     OP(oo)
00341 #define BRA_MASK     OP_MASK
00342 #define BRA(oo)             BRA_(oo), BRA_MASK
00343 
00344 /* Floating point format instructions.  */
00345 #define FP_(oo,fff)  (OP(oo) | (((fff) & 0x7FF) << 5))
00346 #define FP_MASK             (OP_MASK | 0xFFE0)
00347 #define FP(oo,fff)   FP_(oo,fff), FP_MASK
00348 
00349 /* Memory format instructions.  */
00350 #define MEM_(oo)     OP(oo)
00351 #define MEM_MASK     OP_MASK
00352 #define MEM(oo)             MEM_(oo), MEM_MASK
00353 
00354 /* Memory/Func Code format instructions.  */
00355 #define MFC_(oo,ffff)       (OP(oo) | ((ffff) & 0xFFFF))
00356 #define MFC_MASK     (OP_MASK | 0xFFFF)
00357 #define MFC(oo,ffff) MFC_(oo,ffff), MFC_MASK
00358 
00359 /* Memory/Branch format instructions.  */
00360 #define MBR_(oo,h)   (OP(oo) | (((h) & 3) << 14))
00361 #define MBR_MASK     (OP_MASK | 0xC000)
00362 #define MBR(oo,h)    MBR_(oo,h), MBR_MASK
00363 
00364 /* Operate format instructions.  The OPRL variant specifies a
00365    literal second argument.  */
00366 #define OPR_(oo,ff)  (OP(oo) | (((ff) & 0x7F) << 5))
00367 #define OPRL_(oo,ff) (OPR_((oo),(ff)) | 0x1000)
00368 #define OPR_MASK     (OP_MASK | 0x1FE0)
00369 #define OPR(oo,ff)   OPR_(oo,ff), OPR_MASK
00370 #define OPRL(oo,ff)  OPRL_(oo,ff), OPR_MASK
00371 
00372 /* Generic PALcode format instructions.  */
00373 #define PCD_(oo)     OP(oo)
00374 #define PCD_MASK     OP_MASK
00375 #define PCD(oo)             PCD_(oo), PCD_MASK
00376 
00377 /* Specific PALcode instructions.  */
00378 #define SPCD_(oo,ffff)      (OP(oo) | ((ffff) & 0x3FFFFFF))
00379 #define SPCD_MASK    0xFFFFFFFF
00380 #define SPCD(oo,ffff)       SPCD_(oo,ffff), SPCD_MASK
00381 
00382 /* Hardware memory (hw_{ld,st}) instructions.  */
00383 #define EV4HWMEM_(oo,f)     (OP(oo) | (((f) & 0xF) << 12))
00384 #define EV4HWMEM_MASK       (OP_MASK | 0xF000)
00385 #define EV4HWMEM(oo,f)      EV4HWMEM_(oo,f), EV4HWMEM_MASK
00386 
00387 #define EV5HWMEM_(oo,f)     (OP(oo) | (((f) & 0x3F) << 10))
00388 #define EV5HWMEM_MASK       (OP_MASK | 0xF800)
00389 #define EV5HWMEM(oo,f)      EV5HWMEM_(oo,f), EV5HWMEM_MASK
00390 
00391 #define EV6HWMEM_(oo,f)     (OP(oo) | (((f) & 0xF) << 12))
00392 #define EV6HWMEM_MASK       (OP_MASK | 0xF000)
00393 #define EV6HWMEM(oo,f)      EV6HWMEM_(oo,f), EV6HWMEM_MASK
00394 
00395 #define EV6HWMBR_(oo,h)     (OP(oo) | (((h) & 7) << 13))
00396 #define EV6HWMBR_MASK       (OP_MASK | 0xE000)
00397 #define EV6HWMBR(oo,h)      EV6HWMBR_(oo,h), EV6HWMBR_MASK
00398 
00399 /* Abbreviations for instruction subsets.  */
00400 #define BASE                AXP_OPCODE_BASE
00401 #define EV4                 AXP_OPCODE_EV4
00402 #define EV5                 AXP_OPCODE_EV5
00403 #define EV6                 AXP_OPCODE_EV6
00404 #define BWX                 AXP_OPCODE_BWX
00405 #define CIX                 AXP_OPCODE_CIX
00406 #define MAX                 AXP_OPCODE_MAX
00407 
00408 /* Common combinations of arguments.  */
00409 #define ARG_NONE            { 0 }
00410 #define ARG_BRA                    { RA, BDISP }
00411 #define ARG_FBRA            { FA, BDISP }
00412 #define ARG_FP                     { FA, FB, DFC1 }
00413 #define ARG_FPZ1            { ZA, FB, DFC1 }
00414 #define ARG_MEM                    { RA, MDISP, PRB }
00415 #define ARG_FMEM            { FA, MDISP, PRB }
00416 #define ARG_OPR                    { RA, RB, DRC1 }
00417 #define ARG_OPRL            { RA, LIT, DRC1 }
00418 #define ARG_OPRZ1           { ZA, RB, DRC1 }
00419 #define ARG_OPRLZ1          { ZA, LIT, RC }
00420 #define ARG_PCD                    { PALFN }
00421 #define ARG_EV4HWMEM        { RA, EV4HWDISP, PRB }
00422 #define ARG_EV4HWMPR        { RA, RBA, EV4HWINDEX }
00423 #define ARG_EV5HWMEM        { RA, EV5HWDISP, PRB }
00424 #define ARG_EV6HWMEM        { RA, EV6HWDISP, PRB }
00425 
00426 /* The opcode table.
00427 
00428    The format of the opcode table is:
00429 
00430    NAME OPCODE MASK { OPERANDS }
00431 
00432    NAME              is the name of the instruction.
00433 
00434    OPCODE     is the instruction opcode.
00435 
00436    MASK              is the opcode mask; this is used to tell the disassembler
00437               which bits in the actual opcode must match OPCODE.
00438 
00439    OPERANDS   is the list of operands.
00440 
00441    The preceding macros merge the text of the OPCODE and MASK fields.
00442 
00443    The disassembler reads the table in order and prints the first
00444    instruction which matches, so this table is sorted to put more
00445    specific instructions before more general instructions.
00446 
00447    Otherwise, it is sorted by major opcode and minor function code.
00448 
00449    There are three classes of not-really-instructions in this table:
00450 
00451    ALIAS      is another name for another instruction.  Some of
00452               these come from the Architecture Handbook, some
00453               come from the original gas opcode tables.  In all
00454               cases, the functionality of the opcode is unchanged.
00455 
00456    PSEUDO     a stylized code form endorsed by Chapter A.4 of the
00457               Architecture Handbook.
00458 
00459    EXTRA      a stylized code form found in the original gas tables.
00460 
00461    And two annotations:
00462 
00463    EV56 BUT   opcodes that are officially introduced as of the ev56,
00464               but with defined results on previous implementations.
00465 
00466    EV56 UNA   opcodes that were introduced as of the ev56 with
00467               presumably undefined results on previous implementations
00468               that were not assigned to a particular extension.  */
00469 
00470 const struct alpha_opcode alpha_opcodes[] =
00471 {
00472   { "halt",          SPCD(0x00,0x0000), BASE, ARG_NONE },
00473   { "draina",        SPCD(0x00,0x0002), BASE, ARG_NONE },
00474   { "bpt",           SPCD(0x00,0x0080), BASE, ARG_NONE },
00475   { "bugchk",        SPCD(0x00,0x0081), BASE, ARG_NONE },
00476   { "callsys",              SPCD(0x00,0x0083), BASE, ARG_NONE },
00477   { "chmk",          SPCD(0x00,0x0083), BASE, ARG_NONE },
00478   { "imb",           SPCD(0x00,0x0086), BASE, ARG_NONE },
00479   { "rduniq",        SPCD(0x00,0x009e), BASE, ARG_NONE },
00480   { "wruniq",        SPCD(0x00,0x009f), BASE, ARG_NONE },
00481   { "gentrap",              SPCD(0x00,0x00aa), BASE, ARG_NONE },
00482   { "call_pal",             PCD(0x00), BASE, ARG_PCD },
00483   { "pal",           PCD(0x00), BASE, ARG_PCD },        /* alias */
00484 
00485   { "lda",           MEM(0x08), BASE, { RA, MDISP, ZB } },     /* pseudo */
00486   { "lda",           MEM(0x08), BASE, ARG_MEM },
00487   { "ldah",          MEM(0x09), BASE, { RA, MDISP, ZB } },     /* pseudo */
00488   { "ldah",          MEM(0x09), BASE, ARG_MEM },
00489   { "ldbu",          MEM(0x0A), BWX, ARG_MEM },
00490   { "unop",          MEM_(0x0B) | (30 << 16),
00491                      MEM_MASK, BASE, { ZA } },          /* pseudo */
00492   { "ldq_u",         MEM(0x0B), BASE, ARG_MEM },
00493   { "ldwu",          MEM(0x0C), BWX, ARG_MEM },
00494   { "stw",           MEM(0x0D), BWX, ARG_MEM },
00495   { "stb",           MEM(0x0E), BWX, ARG_MEM },
00496   { "stq_u",         MEM(0x0F), BASE, ARG_MEM },
00497 
00498   { "sextl",         OPR(0x10,0x00), BASE, ARG_OPRZ1 }, /* pseudo */
00499   { "sextl",         OPRL(0x10,0x00), BASE, ARG_OPRLZ1 },      /* pseudo */
00500   { "addl",          OPR(0x10,0x00), BASE, ARG_OPR },
00501   { "addl",          OPRL(0x10,0x00), BASE, ARG_OPRL },
00502   { "s4addl",        OPR(0x10,0x02), BASE, ARG_OPR },
00503   { "s4addl",        OPRL(0x10,0x02), BASE, ARG_OPRL },
00504   { "negl",          OPR(0x10,0x09), BASE, ARG_OPRZ1 }, /* pseudo */
00505   { "negl",          OPRL(0x10,0x09), BASE, ARG_OPRLZ1 },      /* pseudo */
00506   { "subl",          OPR(0x10,0x09), BASE, ARG_OPR },
00507   { "subl",          OPRL(0x10,0x09), BASE, ARG_OPRL },
00508   { "s4subl",        OPR(0x10,0x0B), BASE, ARG_OPR },
00509   { "s4subl",        OPRL(0x10,0x0B), BASE, ARG_OPRL },
00510   { "cmpbge",        OPR(0x10,0x0F), BASE, ARG_OPR },
00511   { "cmpbge",        OPRL(0x10,0x0F), BASE, ARG_OPRL },
00512   { "s8addl",        OPR(0x10,0x12), BASE, ARG_OPR },
00513   { "s8addl",        OPRL(0x10,0x12), BASE, ARG_OPRL },
00514   { "s8subl",        OPR(0x10,0x1B), BASE, ARG_OPR },
00515   { "s8subl",        OPRL(0x10,0x1B), BASE, ARG_OPRL },
00516   { "cmpult",        OPR(0x10,0x1D), BASE, ARG_OPR },
00517   { "cmpult",        OPRL(0x10,0x1D), BASE, ARG_OPRL },
00518   { "addq",          OPR(0x10,0x20), BASE, ARG_OPR },
00519   { "addq",          OPRL(0x10,0x20), BASE, ARG_OPRL },
00520   { "s4addq",        OPR(0x10,0x22), BASE, ARG_OPR },
00521   { "s4addq",        OPRL(0x10,0x22), BASE, ARG_OPRL },
00522   { "negq",          OPR(0x10,0x29), BASE, ARG_OPRZ1 }, /* pseudo */
00523   { "negq",          OPRL(0x10,0x29), BASE, ARG_OPRLZ1 },      /* pseudo */
00524   { "subq",          OPR(0x10,0x29), BASE, ARG_OPR },
00525   { "subq",          OPRL(0x10,0x29), BASE, ARG_OPRL },
00526   { "s4subq",        OPR(0x10,0x2B), BASE, ARG_OPR },
00527   { "s4subq",        OPRL(0x10,0x2B), BASE, ARG_OPRL },
00528   { "cmpeq",         OPR(0x10,0x2D), BASE, ARG_OPR },
00529   { "cmpeq",         OPRL(0x10,0x2D), BASE, ARG_OPRL },
00530   { "s8addq",        OPR(0x10,0x32), BASE, ARG_OPR },
00531   { "s8addq",        OPRL(0x10,0x32), BASE, ARG_OPRL },
00532   { "s8subq",        OPR(0x10,0x3B), BASE, ARG_OPR },
00533   { "s8subq",        OPRL(0x10,0x3B), BASE, ARG_OPRL },
00534   { "cmpule",        OPR(0x10,0x3D), BASE, ARG_OPR },
00535   { "cmpule",        OPRL(0x10,0x3D), BASE, ARG_OPRL },
00536   { "addl/v",        OPR(0x10,0x40), BASE, ARG_OPR },
00537   { "addl/v",        OPRL(0x10,0x40), BASE, ARG_OPRL },
00538   { "negl/v",        OPR(0x10,0x49), BASE, ARG_OPRZ1 }, /* pseudo */
00539   { "negl/v",        OPRL(0x10,0x49), BASE, ARG_OPRLZ1 },      /* pseudo */
00540   { "subl/v",        OPR(0x10,0x49), BASE, ARG_OPR },
00541   { "subl/v",        OPRL(0x10,0x49), BASE, ARG_OPRL },
00542   { "cmplt",         OPR(0x10,0x4D), BASE, ARG_OPR },
00543   { "cmplt",         OPRL(0x10,0x4D), BASE, ARG_OPRL },
00544   { "addq/v",        OPR(0x10,0x60), BASE, ARG_OPR },
00545   { "addq/v",        OPRL(0x10,0x60), BASE, ARG_OPRL },
00546   { "negq/v",        OPR(0x10,0x69), BASE, ARG_OPRZ1 }, /* pseudo */
00547   { "negq/v",        OPRL(0x10,0x69), BASE, ARG_OPRLZ1 },      /* pseudo */
00548   { "subq/v",        OPR(0x10,0x69), BASE, ARG_OPR },
00549   { "subq/v",        OPRL(0x10,0x69), BASE, ARG_OPRL },
00550   { "cmple",         OPR(0x10,0x6D), BASE, ARG_OPR },
00551   { "cmple",         OPRL(0x10,0x6D), BASE, ARG_OPRL },
00552 
00553   { "and",           OPR(0x11,0x00), BASE, ARG_OPR },
00554   { "and",           OPRL(0x11,0x00), BASE, ARG_OPRL },
00555   { "andnot",        OPR(0x11,0x08), BASE, ARG_OPR },   /* alias */
00556   { "andnot",        OPRL(0x11,0x08), BASE, ARG_OPRL }, /* alias */
00557   { "bic",           OPR(0x11,0x08), BASE, ARG_OPR },
00558   { "bic",           OPRL(0x11,0x08), BASE, ARG_OPRL },
00559   { "cmovlbs",              OPR(0x11,0x14), BASE, ARG_OPR },
00560   { "cmovlbs",              OPRL(0x11,0x14), BASE, ARG_OPRL },
00561   { "cmovlbc",              OPR(0x11,0x16), BASE, ARG_OPR },
00562   { "cmovlbc",              OPRL(0x11,0x16), BASE, ARG_OPRL },
00563   { "nop",           OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
00564   { "clr",           OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
00565   { "mov",           OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
00566   { "mov",           OPR(0x11,0x20), BASE, { RA, RBA, RC } }, /* pseudo */
00567   { "mov",           OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
00568   { "or",            OPR(0x11,0x20), BASE, ARG_OPR },   /* alias */
00569   { "or",            OPRL(0x11,0x20), BASE, ARG_OPRL }, /* alias */
00570   { "bis",           OPR(0x11,0x20), BASE, ARG_OPR },
00571   { "bis",           OPRL(0x11,0x20), BASE, ARG_OPRL },
00572   { "cmoveq",        OPR(0x11,0x24), BASE, ARG_OPR },
00573   { "cmoveq",        OPRL(0x11,0x24), BASE, ARG_OPRL },
00574   { "cmovne",        OPR(0x11,0x26), BASE, ARG_OPR },
00575   { "cmovne",        OPRL(0x11,0x26), BASE, ARG_OPRL },
00576   { "not",           OPR(0x11,0x28), BASE, ARG_OPRZ1 }, /* pseudo */
00577   { "not",           OPRL(0x11,0x28), BASE, ARG_OPRLZ1 },      /* pseudo */
00578   { "ornot",         OPR(0x11,0x28), BASE, ARG_OPR },
00579   { "ornot",         OPRL(0x11,0x28), BASE, ARG_OPRL },
00580   { "xor",           OPR(0x11,0x40), BASE, ARG_OPR },
00581   { "xor",           OPRL(0x11,0x40), BASE, ARG_OPRL },
00582   { "cmovlt",        OPR(0x11,0x44), BASE, ARG_OPR },
00583   { "cmovlt",        OPRL(0x11,0x44), BASE, ARG_OPRL },
00584   { "cmovge",        OPR(0x11,0x46), BASE, ARG_OPR },
00585   { "cmovge",        OPRL(0x11,0x46), BASE, ARG_OPRL },
00586   { "eqv",           OPR(0x11,0x48), BASE, ARG_OPR },
00587   { "eqv",           OPRL(0x11,0x48), BASE, ARG_OPRL },
00588   { "xornot",        OPR(0x11,0x48), BASE, ARG_OPR },   /* alias */
00589   { "xornot",        OPRL(0x11,0x48), BASE, ARG_OPRL }, /* alias */
00590   { "amask",         OPR(0x11,0x61), BASE, ARG_OPRZ1 }, /* ev56 but */
00591   { "amask",         OPRL(0x11,0x61), BASE, ARG_OPRLZ1 },      /* ev56 but */
00592   { "cmovle",        OPR(0x11,0x64), BASE, ARG_OPR },
00593   { "cmovle",        OPRL(0x11,0x64), BASE, ARG_OPRL },
00594   { "cmovgt",        OPR(0x11,0x66), BASE, ARG_OPR },
00595   { "cmovgt",        OPRL(0x11,0x66), BASE, ARG_OPRL },
00596   { "implver",              OPRL_(0x11,0x6C)|(31<<21)|(1<<13),
00597                      0xFFFFFFE0, BASE, { RC } },        /* ev56 but */
00598 
00599   { "mskbl",         OPR(0x12,0x02), BASE, ARG_OPR },
00600   { "mskbl",         OPRL(0x12,0x02), BASE, ARG_OPRL },
00601   { "extbl",         OPR(0x12,0x06), BASE, ARG_OPR },
00602   { "extbl",         OPRL(0x12,0x06), BASE, ARG_OPRL },
00603   { "insbl",         OPR(0x12,0x0B), BASE, ARG_OPR },
00604   { "insbl",         OPRL(0x12,0x0B), BASE, ARG_OPRL },
00605   { "mskwl",         OPR(0x12,0x12), BASE, ARG_OPR },
00606   { "mskwl",         OPRL(0x12,0x12), BASE, ARG_OPRL },
00607   { "extwl",         OPR(0x12,0x16), BASE, ARG_OPR },
00608   { "extwl",         OPRL(0x12,0x16), BASE, ARG_OPRL },
00609   { "inswl",         OPR(0x12,0x1B), BASE, ARG_OPR },
00610   { "inswl",         OPRL(0x12,0x1B), BASE, ARG_OPRL },
00611   { "mskll",         OPR(0x12,0x22), BASE, ARG_OPR },
00612   { "mskll",         OPRL(0x12,0x22), BASE, ARG_OPRL },
00613   { "extll",         OPR(0x12,0x26), BASE, ARG_OPR },
00614   { "extll",         OPRL(0x12,0x26), BASE, ARG_OPRL },
00615   { "insll",         OPR(0x12,0x2B), BASE, ARG_OPR },
00616   { "insll",         OPRL(0x12,0x2B), BASE, ARG_OPRL },
00617   { "zap",           OPR(0x12,0x30), BASE, ARG_OPR },
00618   { "zap",           OPRL(0x12,0x30), BASE, ARG_OPRL },
00619   { "zapnot",        OPR(0x12,0x31), BASE, ARG_OPR },
00620   { "zapnot",        OPRL(0x12,0x31), BASE, ARG_OPRL },
00621   { "mskql",         OPR(0x12,0x32), BASE, ARG_OPR },
00622   { "mskql",         OPRL(0x12,0x32), BASE, ARG_OPRL },
00623   { "srl",           OPR(0x12,0x34), BASE, ARG_OPR },
00624   { "srl",           OPRL(0x12,0x34), BASE, ARG_OPRL },
00625   { "extql",         OPR(0x12,0x36), BASE, ARG_OPR },
00626   { "extql",         OPRL(0x12,0x36), BASE, ARG_OPRL },
00627   { "sll",           OPR(0x12,0x39), BASE, ARG_OPR },
00628   { "sll",           OPRL(0x12,0x39), BASE, ARG_OPRL },
00629   { "insql",         OPR(0x12,0x3B), BASE, ARG_OPR },
00630   { "insql",         OPRL(0x12,0x3B), BASE, ARG_OPRL },
00631   { "sra",           OPR(0x12,0x3C), BASE, ARG_OPR },
00632   { "sra",           OPRL(0x12,0x3C), BASE, ARG_OPRL },
00633   { "mskwh",         OPR(0x12,0x52), BASE, ARG_OPR },
00634   { "mskwh",         OPRL(0x12,0x52), BASE, ARG_OPRL },
00635   { "inswh",         OPR(0x12,0x57), BASE, ARG_OPR },
00636   { "inswh",         OPRL(0x12,0x57), BASE, ARG_OPRL },
00637   { "extwh",         OPR(0x12,0x5A), BASE, ARG_OPR },
00638   { "extwh",         OPRL(0x12,0x5A), BASE, ARG_OPRL },
00639   { "msklh",         OPR(0x12,0x62), BASE, ARG_OPR },
00640   { "msklh",         OPRL(0x12,0x62), BASE, ARG_OPRL },
00641   { "inslh",         OPR(0x12,0x67), BASE, ARG_OPR },
00642   { "inslh",         OPRL(0x12,0x67), BASE, ARG_OPRL },
00643   { "extlh",         OPR(0x12,0x6A), BASE, ARG_OPR },
00644   { "extlh",         OPRL(0x12,0x6A), BASE, ARG_OPRL },
00645   { "mskqh",         OPR(0x12,0x72), BASE, ARG_OPR },
00646   { "mskqh",         OPRL(0x12,0x72), BASE, ARG_OPRL },
00647   { "insqh",         OPR(0x12,0x77), BASE, ARG_OPR },
00648   { "insqh",         OPRL(0x12,0x77), BASE, ARG_OPRL },
00649   { "extqh",         OPR(0x12,0x7A), BASE, ARG_OPR },
00650   { "extqh",         OPRL(0x12,0x7A), BASE, ARG_OPRL },
00651 
00652   { "mull",          OPR(0x13,0x00), BASE, ARG_OPR },
00653   { "mull",          OPRL(0x13,0x00), BASE, ARG_OPRL },
00654   { "mulq",          OPR(0x13,0x20), BASE, ARG_OPR },
00655   { "mulq",          OPRL(0x13,0x20), BASE, ARG_OPRL },
00656   { "umulh",         OPR(0x13,0x30), BASE, ARG_OPR },
00657   { "umulh",         OPRL(0x13,0x30), BASE, ARG_OPRL },
00658   { "mull/v",        OPR(0x13,0x40), BASE, ARG_OPR },
00659   { "mull/v",        OPRL(0x13,0x40), BASE, ARG_OPRL },
00660   { "mulq/v",        OPR(0x13,0x60), BASE, ARG_OPR },
00661   { "mulq/v",        OPRL(0x13,0x60), BASE, ARG_OPRL },
00662 
00663   { "itofs",         FP(0x14,0x004), CIX, { RA, ZB, FC } },
00664   { "sqrtf/c",              FP(0x14,0x00A), CIX, ARG_FPZ1 },
00665   { "sqrts/c",              FP(0x14,0x00B), CIX, ARG_FPZ1 },
00666   { "itoff",         FP(0x14,0x014), CIX, { RA, ZB, FC } },
00667   { "itoft",         FP(0x14,0x024), CIX, { RA, ZB, FC } },
00668   { "sqrtg/c",              FP(0x14,0x02A), CIX, ARG_FPZ1 },
00669   { "sqrtt/c",              FP(0x14,0x02B), CIX, ARG_FPZ1 },
00670   { "sqrts/m",              FP(0x14,0x04B), CIX, ARG_FPZ1 },
00671   { "sqrtt/m",              FP(0x14,0x06B), CIX, ARG_FPZ1 },
00672   { "sqrtf",         FP(0x14,0x08A), CIX, ARG_FPZ1 },
00673   { "sqrts",         FP(0x14,0x08B), CIX, ARG_FPZ1 },
00674   { "sqrtg",         FP(0x14,0x0AA), CIX, ARG_FPZ1 },
00675   { "sqrtt",         FP(0x14,0x0AB), CIX, ARG_FPZ1 },
00676   { "sqrts/d",              FP(0x14,0x0CB), CIX, ARG_FPZ1 },
00677   { "sqrtt/d",              FP(0x14,0x0EB), CIX, ARG_FPZ1 },
00678   { "sqrtf/uc",             FP(0x14,0x10A), CIX, ARG_FPZ1 },
00679   { "sqrts/uc",             FP(0x14,0x10B), CIX, ARG_FPZ1 },
00680   { "sqrtg/uc",             FP(0x14,0x12A), CIX, ARG_FPZ1 },
00681   { "sqrtt/uc",             FP(0x14,0x12B), CIX, ARG_FPZ1 },
00682   { "sqrts/um",             FP(0x14,0x14B), CIX, ARG_FPZ1 },
00683   { "sqrtt/um",             FP(0x14,0x16B), CIX, ARG_FPZ1 },
00684   { "sqrtf/u",              FP(0x14,0x18A), CIX, ARG_FPZ1 },
00685   { "sqrts/u",              FP(0x14,0x18B), CIX, ARG_FPZ1 },
00686   { "sqrtg/u",              FP(0x14,0x1AA), CIX, ARG_FPZ1 },
00687   { "sqrtt/u",              FP(0x14,0x1AB), CIX, ARG_FPZ1 },
00688   { "sqrts/ud",             FP(0x14,0x1CB), CIX, ARG_FPZ1 },
00689   { "sqrtt/ud",             FP(0x14,0x1EB), CIX, ARG_FPZ1 },
00690   { "sqrtf/sc",             FP(0x14,0x40A), CIX, ARG_FPZ1 },
00691   { "sqrtg/sc",             FP(0x14,0x42A), CIX, ARG_FPZ1 },
00692   { "sqrtf/s",              FP(0x14,0x48A), CIX, ARG_FPZ1 },
00693   { "sqrtg/s",              FP(0x14,0x4AA), CIX, ARG_FPZ1 },
00694   { "sqrtf/suc",     FP(0x14,0x50A), CIX, ARG_FPZ1 },
00695   { "sqrts/suc",     FP(0x14,0x50B), CIX, ARG_FPZ1 },
00696   { "sqrtg/suc",     FP(0x14,0x52A), CIX, ARG_FPZ1 },
00697   { "sqrtt/suc",     FP(0x14,0x52B), CIX, ARG_FPZ1 },
00698   { "sqrts/sum",     FP(0x14,0x54B), CIX, ARG_FPZ1 },
00699   { "sqrtt/sum",     FP(0x14,0x56B), CIX, ARG_FPZ1 },
00700   { "sqrtf/su",             FP(0x14,0x58A), CIX, ARG_FPZ1 },
00701   { "sqrts/su",             FP(0x14,0x58B), CIX, ARG_FPZ1 },
00702   { "sqrtg/su",             FP(0x14,0x5AA), CIX, ARG_FPZ1 },
00703   { "sqrtt/su",             FP(0x14,0x5AB), CIX, ARG_FPZ1 },
00704   { "sqrts/sud",     FP(0x14,0x5CB), CIX, ARG_FPZ1 },
00705   { "sqrtt/sud",     FP(0x14,0x5EB), CIX, ARG_FPZ1 },
00706   { "sqrts/suic",    FP(0x14,0x70B), CIX, ARG_FPZ1 },
00707   { "sqrtt/suic",    FP(0x14,0x72B), CIX, ARG_FPZ1 },
00708   { "sqrts/suim",    FP(0x14,0x74B), CIX, ARG_FPZ1 },
00709   { "sqrtt/suim",    FP(0x14,0x76B), CIX, ARG_FPZ1 },
00710   { "sqrts/sui",     FP(0x14,0x78B), CIX, ARG_FPZ1 },
00711   { "sqrtt/sui",     FP(0x14,0x7AB), CIX, ARG_FPZ1 },
00712   { "sqrts/suid",    FP(0x14,0x7CB), CIX, ARG_FPZ1 },
00713   { "sqrtt/suid",    FP(0x14,0x7EB), CIX, ARG_FPZ1 },
00714 
00715   { "addf/c",        FP(0x15,0x000), BASE, ARG_FP },
00716   { "subf/c",        FP(0x15,0x001), BASE, ARG_FP },
00717   { "mulf/c",        FP(0x15,0x002), BASE, ARG_FP },
00718   { "divf/c",        FP(0x15,0x003), BASE, ARG_FP },
00719   { "cvtdg/c",              FP(0x15,0x01E), BASE, ARG_FPZ1 },
00720   { "addg/c",        FP(0x15,0x020), BASE, ARG_FP },
00721   { "subg/c",        FP(0x15,0x021), BASE, ARG_FP },
00722   { "mulg/c",        FP(0x15,0x022), BASE, ARG_FP },
00723   { "divg/c",        FP(0x15,0x023), BASE, ARG_FP },
00724   { "cvtgf/c",              FP(0x15,0x02C), BASE, ARG_FPZ1 },
00725   { "cvtgd/c",              FP(0x15,0x02D), BASE, ARG_FPZ1 },
00726   { "cvtgq/c",              FP(0x15,0x02F), BASE, ARG_FPZ1 },
00727   { "cvtqf/c",              FP(0x15,0x03C), BASE, ARG_FPZ1 },
00728   { "cvtqg/c",              FP(0x15,0x03E), BASE, ARG_FPZ1 },
00729   { "addf",          FP(0x15,0x080), BASE, ARG_FP },
00730   { "negf",          FP(0x15,0x081), BASE, ARG_FPZ1 },  /* pseudo */
00731   { "subf",          FP(0x15,0x081), BASE, ARG_FP },
00732   { "mulf",          FP(0x15,0x082), BASE, ARG_FP },
00733   { "divf",          FP(0x15,0x083), BASE, ARG_FP },
00734   { "cvtdg",         FP(0x15,0x09E), BASE, ARG_FPZ1 },
00735   { "addg",          FP(0x15,0x0A0), BASE, ARG_FP },
00736   { "negg",          FP(0x15,0x0A1), BASE, ARG_FPZ1 },  /* pseudo */
00737   { "subg",          FP(0x15,0x0A1), BASE, ARG_FP },
00738   { "mulg",          FP(0x15,0x0A2), BASE, ARG_FP },
00739   { "divg",          FP(0x15,0x0A3), BASE, ARG_FP },
00740   { "cmpgeq",        FP(0x15,0x0A5), BASE, ARG_FP },
00741   { "cmpglt",        FP(0x15,0x0A6), BASE, ARG_FP },
00742   { "cmpgle",        FP(0x15,0x0A7), BASE, ARG_FP },
00743   { "cvtgf",         FP(0x15,0x0AC), BASE, ARG_FPZ1 },
00744   { "cvtgd",         FP(0x15,0x0AD), BASE, ARG_FPZ1 },
00745   { "cvtgq",         FP(0x15,0x0AF), BASE, ARG_FPZ1 },
00746   { "cvtqf",         FP(0x15,0x0BC), BASE, ARG_FPZ1 },
00747   { "cvtqg",         FP(0x15,0x0BE), BASE, ARG_FPZ1 },
00748   { "addf/uc",              FP(0x15,0x100), BASE, ARG_FP },
00749   { "subf/uc",              FP(0x15,0x101), BASE, ARG_FP },
00750   { "mulf/uc",              FP(0x15,0x102), BASE, ARG_FP },
00751   { "divf/uc",              FP(0x15,0x103), BASE, ARG_FP },
00752   { "cvtdg/uc",             FP(0x15,0x11E), BASE, ARG_FPZ1 },
00753   { "addg/uc",              FP(0x15,0x120), BASE, ARG_FP },
00754   { "subg/uc",              FP(0x15,0x121), BASE, ARG_FP },
00755   { "mulg/uc",              FP(0x15,0x122), BASE, ARG_FP },
00756   { "divg/uc",              FP(0x15,0x123), BASE, ARG_FP },
00757   { "cvtgf/uc",             FP(0x15,0x12C), BASE, ARG_FPZ1 },
00758   { "cvtgd/uc",             FP(0x15,0x12D), BASE, ARG_FPZ1 },
00759   { "cvtgq/vc",             FP(0x15,0x12F), BASE, ARG_FPZ1 },
00760   { "addf/u",        FP(0x15,0x180), BASE, ARG_FP },
00761   { "subf/u",        FP(0x15,0x181), BASE, ARG_FP },
00762   { "mulf/u",        FP(0x15,0x182), BASE, ARG_FP },
00763   { "divf/u",        FP(0x15,0x183), BASE, ARG_FP },
00764   { "cvtdg/u",              FP(0x15,0x19E), BASE, ARG_FPZ1 },
00765   { "addg/u",        FP(0x15,0x1A0), BASE, ARG_FP },
00766   { "subg/u",        FP(0x15,0x1A1), BASE, ARG_FP },
00767   { "mulg/u",        FP(0x15,0x1A2), BASE, ARG_FP },
00768   { "divg/u",        FP(0x15,0x1A3), BASE, ARG_FP },
00769   { "cvtgf/u",              FP(0x15,0x1AC), BASE, ARG_FPZ1 },
00770   { "cvtgd/u",              FP(0x15,0x1AD), BASE, ARG_FPZ1 },
00771   { "cvtgq/v",              FP(0x15,0x1AF), BASE, ARG_FPZ1 },
00772   { "addf/sc",              FP(0x15,0x400), BASE, ARG_FP },
00773   { "subf/sc",              FP(0x15,0x401), BASE, ARG_FP },
00774   { "mulf/sc",              FP(0x15,0x402), BASE, ARG_FP },
00775   { "divf/sc",              FP(0x15,0x403), BASE, ARG_FP },
00776   { "cvtdg/sc",             FP(0x15,0x41E), BASE, ARG_FPZ1 },
00777   { "addg/sc",              FP(0x15,0x420), BASE, ARG_FP },
00778   { "subg/sc",              FP(0x15,0x421), BASE, ARG_FP },
00779   { "mulg/sc",              FP(0x15,0x422), BASE, ARG_FP },
00780   { "divg/sc",              FP(0x15,0x423), BASE, ARG_FP },
00781   { "cvtgf/sc",             FP(0x15,0x42C), BASE, ARG_FPZ1 },
00782   { "cvtgd/sc",             FP(0x15,0x42D), BASE, ARG_FPZ1 },
00783   { "cvtgq/sc",             FP(0x15,0x42F), BASE, ARG_FPZ1 },
00784   { "addf/s",        FP(0x15,0x480), BASE, ARG_FP },
00785   { "negf/s",        FP(0x15,0x481), BASE, ARG_FPZ1 },  /* pseudo */
00786   { "subf/s",        FP(0x15,0x481), BASE, ARG_FP },
00787   { "mulf/s",        FP(0x15,0x482), BASE, ARG_FP },
00788   { "divf/s",        FP(0x15,0x483), BASE, ARG_FP },
00789   { "cvtdg/s",              FP(0x15,0x49E), BASE, ARG_FPZ1 },
00790   { "addg/s",        FP(0x15,0x4A0), BASE, ARG_FP },
00791   { "negg/s",        FP(0x15,0x4A1), BASE, ARG_FPZ1 },  /* pseudo */
00792   { "subg/s",        FP(0x15,0x4A1), BASE, ARG_FP },
00793   { "mulg/s",        FP(0x15,0x4A2), BASE, ARG_FP },
00794   { "divg/s",        FP(0x15,0x4A3), BASE, ARG_FP },
00795   { "cmpgeq/s",             FP(0x15,0x4A5), BASE, ARG_FP },
00796   { "cmpglt/s",             FP(0x15,0x4A6), BASE, ARG_FP },
00797   { "cmpgle/s",             FP(0x15,0x4A7), BASE, ARG_FP },
00798   { "cvtgf/s",              FP(0x15,0x4AC), BASE, ARG_FPZ1 },
00799   { "cvtgd/s",              FP(0x15,0x4AD), BASE, ARG_FPZ1 },
00800   { "cvtgq/s",              FP(0x15,0x4AF), BASE, ARG_FPZ1 },
00801   { "addf/suc",             FP(0x15,0x500), BASE, ARG_FP },
00802   { "subf/suc",             FP(0x15,0x501), BASE, ARG_FP },
00803   { "mulf/suc",             FP(0x15,0x502), BASE, ARG_FP },
00804   { "divf/suc",             FP(0x15,0x503), BASE, ARG_FP },
00805   { "cvtdg/suc",     FP(0x15,0x51E), BASE, ARG_FPZ1 },
00806   { "addg/suc",             FP(0x15,0x520), BASE, ARG_FP },
00807   { "subg/suc",             FP(0x15,0x521), BASE, ARG_FP },
00808   { "mulg/suc",             FP(0x15,0x522), BASE, ARG_FP },
00809   { "divg/suc",             FP(0x15,0x523), BASE, ARG_FP },
00810   { "cvtgf/suc",     FP(0x15,0x52C), BASE, ARG_FPZ1 },
00811   { "cvtgd/suc",     FP(0x15,0x52D), BASE, ARG_FPZ1 },
00812   { "cvtgq/svc",     FP(0x15,0x52F), BASE, ARG_FPZ1 },
00813   { "addf/su",              FP(0x15,0x580), BASE, ARG_FP },
00814   { "subf/su",              FP(0x15,0x581), BASE, ARG_FP },
00815   { "mulf/su",              FP(0x15,0x582), BASE, ARG_FP },
00816   { "divf/su",              FP(0x15,0x583), BASE, ARG_FP },
00817   { "cvtdg/su",             FP(0x15,0x59E), BASE, ARG_FPZ1 },
00818   { "addg/su",              FP(0x15,0x5A0), BASE, ARG_FP },
00819   { "subg/su",              FP(0x15,0x5A1), BASE, ARG_FP },
00820   { "mulg/su",              FP(0x15,0x5A2), BASE, ARG_FP },
00821   { "divg/su",              FP(0x15,0x5A3), BASE, ARG_FP },
00822   { "cvtgf/su",             FP(0x15,0x5AC), BASE, ARG_FPZ1 },
00823   { "cvtgd/su",             FP(0x15,0x5AD), BASE, ARG_FPZ1 },
00824   { "cvtgq/sv",             FP(0x15,0x5AF), BASE, ARG_FPZ1 },
00825 
00826   { "adds/c",        FP(0x16,0x000), BASE, ARG_FP },
00827   { "subs/c",        FP(0x16,0x001), BASE, ARG_FP },
00828   { "muls/c",        FP(0x16,0x002), BASE, ARG_FP },
00829   { "divs/c",        FP(0x16,0x003), BASE, ARG_FP },
00830   { "addt/c",        FP(0x16,0x020), BASE, ARG_FP },
00831   { "subt/c",        FP(0x16,0x021), BASE, ARG_FP },
00832   { "mult/c",        FP(0x16,0x022), BASE, ARG_FP },
00833   { "divt/c",        FP(0x16,0x023), BASE, ARG_FP },
00834   { "cvtts/c",              FP(0x16,0x02C), BASE, ARG_FPZ1 },
00835   { "cvttq/c",              FP(0x16,0x02F), BASE, ARG_FPZ1 },
00836   { "cvtqs/c",              FP(0x16,0x03C), BASE, ARG_FPZ1 },
00837   { "cvtqt/c",              FP(0x16,0x03E), BASE, ARG_FPZ1 },
00838   { "adds/m",        FP(0x16,0x040), BASE, ARG_FP },
00839   { "subs/m",        FP(0x16,0x041), BASE, ARG_FP },
00840   { "muls/m",        FP(0x16,0x042), BASE, ARG_FP },
00841   { "divs/m",        FP(0x16,0x043), BASE, ARG_FP },
00842   { "addt/m",        FP(0x16,0x060), BASE, ARG_FP },
00843   { "subt/m",        FP(0x16,0x061), BASE, ARG_FP },
00844   { "mult/m",        FP(0x16,0x062), BASE, ARG_FP },
00845   { "divt/m",        FP(0x16,0x063), BASE, ARG_FP },
00846   { "cvtts/m",              FP(0x16,0x06C), BASE, ARG_FPZ1 },
00847   { "cvttq/m",              FP(0x16,0x06F), BASE, ARG_FPZ1 },
00848   { "cvtqs/m",              FP(0x16,0x07C), BASE, ARG_FPZ1 },
00849   { "cvtqt/m",              FP(0x16,0x07E), BASE, ARG_FPZ1 },
00850   { "adds",          FP(0x16,0x080), BASE, ARG_FP },
00851   { "negs",          FP(0x16,0x081), BASE, ARG_FPZ1 },  /* pseudo */
00852   { "subs",          FP(0x16,0x081), BASE, ARG_FP },
00853   { "muls",          FP(0x16,0x082), BASE, ARG_FP },
00854   { "divs",          FP(0x16,0x083), BASE, ARG_FP },
00855   { "addt",          FP(0x16,0x0A0), BASE, ARG_FP },
00856   { "negt",          FP(0x16,0x0A1), BASE, ARG_FPZ1 },  /* pseudo */
00857   { "subt",          FP(0x16,0x0A1), BASE, ARG_FP },
00858   { "mult",          FP(0x16,0x0A2), BASE, ARG_FP },
00859   { "divt",          FP(0x16,0x0A3), BASE, ARG_FP },
00860   { "cmptun",        FP(0x16,0x0A4), BASE, ARG_FP },
00861   { "cmpteq",        FP(0x16,0x0A5), BASE, ARG_FP },
00862   { "cmptlt",        FP(0x16,0x0A6), BASE, ARG_FP },
00863   { "cmptle",        FP(0x16,0x0A7), BASE, ARG_FP },
00864   { "cvtts",         FP(0x16,0x0AC), BASE, ARG_FPZ1 },
00865   { "cvttq",         FP(0x16,0x0AF), BASE, ARG_FPZ1 },
00866   { "cvtqs",         FP(0x16,0x0BC), BASE, ARG_FPZ1 },
00867   { "cvtqt",         FP(0x16,0x0BE), BASE, ARG_FPZ1 },
00868   { "adds/d",        FP(0x16,0x0C0), BASE, ARG_FP },
00869   { "subs/d",        FP(0x16,0x0C1), BASE, ARG_FP },
00870   { "muls/d",        FP(0x16,0x0C2), BASE, ARG_FP },
00871   { "divs/d",        FP(0x16,0x0C3), BASE, ARG_FP },
00872   { "addt/d",        FP(0x16,0x0E0), BASE, ARG_FP },
00873   { "subt/d",        FP(0x16,0x0E1), BASE, ARG_FP },
00874   { "mult/d",        FP(0x16,0x0E2), BASE, ARG_FP },
00875   { "divt/d",        FP(0x16,0x0E3), BASE, ARG_FP },
00876   { "cvtts/d",              FP(0x16,0x0EC), BASE, ARG_FPZ1 },
00877   { "cvttq/d",              FP(0x16,0x0EF), BASE, ARG_FPZ1 },
00878   { "cvtqs/d",              FP(0x16,0x0FC), BASE, ARG_FPZ1 },
00879   { "cvtqt/d",              FP(0x16,0x0FE), BASE, ARG_FPZ1 },
00880   { "adds/uc",              FP(0x16,0x100), BASE, ARG_FP },
00881   { "subs/uc",              FP(0x16,0x101), BASE, ARG_FP },
00882   { "muls/uc",              FP(0x16,0x102), BASE, ARG_FP },
00883   { "divs/uc",              FP(0x16,0x103), BASE, ARG_FP },
00884   { "addt/uc",              FP(0x16,0x120), BASE, ARG_FP },
00885   { "subt/uc",              FP(0x16,0x121), BASE, ARG_FP },
00886   { "mult/uc",              FP(0x16,0x122), BASE, ARG_FP },
00887   { "divt/uc",              FP(0x16,0x123), BASE, ARG_FP },
00888   { "cvtts/uc",             FP(0x16,0x12C), BASE, ARG_FPZ1 },
00889   { "cvttq/vc",             FP(0x16,0x12F), BASE, ARG_FPZ1 },
00890   { "adds/um",              FP(0x16,0x140), BASE, ARG_FP },
00891   { "subs/um",              FP(0x16,0x141), BASE, ARG_FP },
00892   { "muls/um",              FP(0x16,0x142), BASE, ARG_FP },
00893   { "divs/um",              FP(0x16,0x143), BASE, ARG_FP },
00894   { "addt/um",              FP(0x16,0x160), BASE, ARG_FP },
00895   { "subt/um",              FP(0x16,0x161), BASE, ARG_FP },
00896   { "mult/um",              FP(0x16,0x162), BASE, ARG_FP },
00897   { "divt/um",              FP(0x16,0x163), BASE, ARG_FP },
00898   { "cvtts/um",             FP(0x16,0x16C), BASE, ARG_FPZ1 },
00899   { "cvttq/vm",             FP(0x16,0x16F), BASE, ARG_FPZ1 },
00900   { "adds/u",        FP(0x16,0x180), BASE, ARG_FP },
00901   { "subs/u",        FP(0x16,0x181), BASE, ARG_FP },
00902   { "muls/u",        FP(0x16,0x182), BASE, ARG_FP },
00903   { "divs/u",        FP(0x16,0x183), BASE, ARG_FP },
00904   { "addt/u",        FP(0x16,0x1A0), BASE, ARG_FP },
00905   { "subt/u",        FP(0x16,0x1A1), BASE, ARG_FP },
00906   { "mult/u",        FP(0x16,0x1A2), BASE, ARG_FP },
00907   { "divt/u",        FP(0x16,0x1A3), BASE, ARG_FP },
00908   { "cvtts/u",              FP(0x16,0x1AC), BASE, ARG_FPZ1 },
00909   { "cvttq/v",              FP(0x16,0x1AF), BASE, ARG_FPZ1 },
00910   { "adds/ud",              FP(0x16,0x1C0), BASE, ARG_FP },
00911   { "subs/ud",              FP(0x16,0x1C1), BASE, ARG_FP },
00912   { "muls/ud",              FP(0x16,0x1C2), BASE, ARG_FP },
00913   { "divs/ud",              FP(0x16,0x1C3), BASE, ARG_FP },
00914   { "addt/ud",              FP(0x16,0x1E0), BASE, ARG_FP },
00915   { "subt/ud",              FP(0x16,0x1E1), BASE, ARG_FP },
00916   { "mult/ud",              FP(0x16,0x1E2), BASE, ARG_FP },
00917   { "divt/ud",              FP(0x16,0x1E3), BASE, ARG_FP },
00918   { "cvtts/ud",             FP(0x16,0x1EC), BASE, ARG_FPZ1 },
00919   { "cvttq/vd",             FP(0x16,0x1EF), BASE, ARG_FPZ1 },
00920   { "cvtst",         FP(0x16,0x2AC), BASE, ARG_FPZ1 },
00921   { "adds/suc",             FP(0x16,0x500), BASE, ARG_FP },
00922   { "subs/suc",             FP(0x16,0x501), BASE, ARG_FP },
00923   { "muls/suc",             FP(0x16,0x502), BASE, ARG_FP },
00924   { "divs/suc",             FP(0x16,0x503), BASE, ARG_FP },
00925   { "addt/suc",             FP(0x16,0x520), BASE, ARG_FP },
00926   { "subt/suc",             FP(0x16,0x521), BASE, ARG_FP },
00927   { "mult/suc",             FP(0x16,0x522), BASE, ARG_FP },
00928   { "divt/suc",             FP(0x16,0x523), BASE, ARG_FP },
00929   { "cvtts/suc",     FP(0x16,0x52C), BASE, ARG_FPZ1 },
00930   { "cvttq/svc",     FP(0x16,0x52F), BASE, ARG_FPZ1 },
00931   { "adds/sum",             FP(0x16,0x540), BASE, ARG_FP },
00932   { "subs/sum",             FP(0x16,0x541), BASE, ARG_FP },
00933   { "muls/sum",             FP(0x16,0x542), BASE, ARG_FP },
00934   { "divs/sum",             FP(0x16,0x543), BASE, ARG_FP },
00935   { "addt/sum",             FP(0x16,0x560), BASE, ARG_FP },
00936   { "subt/sum",             FP(0x16,0x561), BASE, ARG_FP },
00937   { "mult/sum",             FP(0x16,0x562), BASE, ARG_FP },
00938   { "divt/sum",             FP(0x16,0x563), BASE, ARG_FP },
00939   { "cvtts/sum",     FP(0x16,0x56C), BASE, ARG_FPZ1 },
00940   { "cvttq/svm",     FP(0x16,0x56F), BASE, ARG_FPZ1 },
00941   { "adds/su",              FP(0x16,0x580), BASE, ARG_FP },
00942   { "negs/su",              FP(0x16,0x581), BASE, ARG_FPZ1 },  /* pseudo */
00943   { "subs/su",              FP(0x16,0x581), BASE, ARG_FP },
00944   { "muls/su",              FP(0x16,0x582), BASE, ARG_FP },
00945   { "divs/su",              FP(0x16,0x583), BASE, ARG_FP },
00946   { "addt/su",              FP(0x16,0x5A0), BASE, ARG_FP },
00947   { "negt/su",              FP(0x16,0x5A1), BASE, ARG_FPZ1 },  /* pseudo */
00948   { "subt/su",              FP(0x16,0x5A1), BASE, ARG_FP },
00949   { "mult/su",              FP(0x16,0x5A2), BASE, ARG_FP },
00950   { "divt/su",              FP(0x16,0x5A3), BASE, ARG_FP },
00951   { "cmptun/su",     FP(0x16,0x5A4), BASE, ARG_FP },
00952   { "cmpteq/su",     FP(0x16,0x5A5), BASE, ARG_FP },
00953   { "cmptlt/su",     FP(0x16,0x5A6), BASE, ARG_FP },
00954   { "cmptle/su",     FP(0x16,0x5A7), BASE, ARG_FP },
00955   { "cvtts/su",             FP(0x16,0x5AC), BASE, ARG_FPZ1 },
00956   { "cvttq/sv",             FP(0x16,0x5AF), BASE, ARG_FPZ1 },
00957   { "adds/sud",             FP(0x16,0x5C0), BASE, ARG_FP },
00958   { "subs/sud",             FP(0x16,0x5C1), BASE, ARG_FP },
00959   { "muls/sud",             FP(0x16,0x5C2), BASE, ARG_FP },
00960   { "divs/sud",             FP(0x16,0x5C3), BASE, ARG_FP },
00961   { "addt/sud",             FP(0x16,0x5E0), BASE, ARG_FP },
00962   { "subt/sud",             FP(0x16,0x5E1), BASE, ARG_FP },
00963   { "mult/sud",             FP(0x16,0x5E2), BASE, ARG_FP },
00964   { "divt/sud",             FP(0x16,0x5E3), BASE, ARG_FP },
00965   { "cvtts/sud",     FP(0x16,0x5EC), BASE, ARG_FPZ1 },
00966   { "cvttq/svd",     FP(0x16,0x5EF), BASE, ARG_FPZ1 },
00967   { "cvtst/s",              FP(0x16,0x6AC), BASE, ARG_FPZ1 },
00968   { "adds/suic",     FP(0x16,0x700), BASE, ARG_FP },
00969   { "subs/suic",     FP(0x16,0x701), BASE, ARG_FP },
00970   { "muls/suic",     FP(0x16,0x702), BASE, ARG_FP },
00971   { "divs/suic",     FP(0x16,0x703), BASE, ARG_FP },
00972   { "addt/suic",     FP(0x16,0x720), BASE, ARG_FP },
00973   { "subt/suic",     FP(0x16,0x721), BASE, ARG_FP },
00974   { "mult/suic",     FP(0x16,0x722), BASE, ARG_FP },
00975   { "divt/suic",     FP(0x16,0x723), BASE, ARG_FP },
00976   { "cvtts/suic",    FP(0x16,0x72C), BASE, ARG_FPZ1 },
00977   { "cvttq/svic",    FP(0x16,0x72F), BASE, ARG_FPZ1 },
00978   { "cvtqs/suic",    FP(0x16,0x73C), BASE, ARG_FPZ1 },
00979   { "cvtqt/suic",    FP(0x16,0x73E), BASE, ARG_FPZ1 },
00980   { "adds/suim",     FP(0x16,0x740), BASE, ARG_FP },
00981   { "subs/suim",     FP(0x16,0x741), BASE, ARG_FP },
00982   { "muls/suim",     FP(0x16,0x742), BASE, ARG_FP },
00983   { "divs/suim",     FP(0x16,0x743), BASE, ARG_FP },
00984   { "addt/suim",     FP(0x16,0x760), BASE, ARG_FP },
00985   { "subt/suim",     FP(0x16,0x761), BASE, ARG_FP },
00986   { "mult/suim",     FP(0x16,0x762), BASE, ARG_FP },
00987   { "divt/suim",     FP(0x16,0x763), BASE, ARG_FP },
00988   { "cvtts/suim",    FP(0x16,0x76C), BASE, ARG_FPZ1 },
00989   { "cvttq/svim",    FP(0x16,0x76F), BASE, ARG_FPZ1 },
00990   { "cvtqs/suim",    FP(0x16,0x77C), BASE, ARG_FPZ1 },
00991   { "cvtqt/suim",    FP(0x16,0x77E), BASE, ARG_FPZ1 },
00992   { "adds/sui",             FP(0x16,0x780), BASE, ARG_FP },
00993   { "negs/sui",      FP(0x16,0x781), BASE, ARG_FPZ1 },  /* pseudo */
00994   { "subs/sui",             FP(0x16,0x781), BASE, ARG_FP },
00995   { "muls/sui",             FP(0x16,0x782), BASE, ARG_FP },
00996   { "divs/sui",             FP(0x16,0x783), BASE, ARG_FP },
00997   { "addt/sui",             FP(0x16,0x7A0), BASE, ARG_FP },
00998   { "negt/sui",      FP(0x16,0x7A1), BASE, ARG_FPZ1 },  /* pseudo */
00999   { "subt/sui",             FP(0x16,0x7A1), BASE, ARG_FP },
01000   { "mult/sui",             FP(0x16,0x7A2), BASE, ARG_FP },
01001   { "divt/sui",             FP(0x16,0x7A3), BASE, ARG_FP },
01002   { "cvtts/sui",     FP(0x16,0x7AC), BASE, ARG_FPZ1 },
01003   { "cvttq/svi",     FP(0x16,0x7AF), BASE, ARG_FPZ1 },
01004   { "cvtqs/sui",     FP(0x16,0x7BC), BASE, ARG_FPZ1 },
01005   { "cvtqt/sui",     FP(0x16,0x7BE), BASE, ARG_FPZ1 },
01006   { "adds/suid",     FP(0x16,0x7C0), BASE, ARG_FP },
01007   { "subs/suid",     FP(0x16,0x7C1), BASE, ARG_FP },
01008   { "muls/suid",     FP(0x16,0x7C2), BASE, ARG_FP },
01009   { "divs/suid",     FP(0x16,0x7C3), BASE, ARG_FP },
01010   { "addt/suid",     FP(0x16,0x7E0), BASE, ARG_FP },
01011   { "subt/suid",     FP(0x16,0x7E1), BASE, ARG_FP },
01012   { "mult/suid",     FP(0x16,0x7E2), BASE, ARG_FP },
01013   { "divt/suid",     FP(0x16,0x7E3), BASE, ARG_FP },
01014   { "cvtts/suid",    FP(0x16,0x7EC), BASE, ARG_FPZ1 },
01015   { "cvttq/svid",    FP(0x16,0x7EF), BASE, ARG_FPZ1 },
01016   { "cvtqs/suid",    FP(0x16,0x7FC), BASE, ARG_FPZ1 },
01017   { "cvtqt/suid",    FP(0x16,0x7FE), BASE, ARG_FPZ1 },
01018 
01019   { "cvtlq",         FP(0x17,0x010), BASE, ARG_FPZ1 },
01020   { "fnop",          FP(0x17,0x020), BASE, { ZA, ZB, ZC } },   /* pseudo */
01021   { "fclr",          FP(0x17,0x020), BASE, { ZA, ZB, FC } },   /* pseudo */
01022   { "fabs",          FP(0x17,0x020), BASE, ARG_FPZ1 },  /* pseudo */
01023   { "fmov",          FP(0x17,0x020), BASE, { FA, RBA, FC } }, /* pseudo */
01024   { "cpys",          FP(0x17,0x020), BASE, ARG_FP },
01025   { "fneg",          FP(0x17,0x021), BASE, { FA, RBA, FC } }, /* pseudo */
01026   { "cpysn",         FP(0x17,0x021), BASE, ARG_FP },
01027   { "cpyse",         FP(0x17,0x022), BASE, ARG_FP },
01028   { "mt_fpcr",              FP(0x17,0x024), BASE, { FA, RBA, RCA } },
01029   { "mf_fpcr",              FP(0x17,0x025), BASE, { FA, RBA, RCA } },
01030   { "fcmoveq",              FP(0x17,0x02A), BASE, ARG_FP },
01031   { "fcmovne",              FP(0x17,0x02B), BASE, ARG_FP },
01032   { "fcmovlt",              FP(0x17,0x02C), BASE, ARG_FP },
01033   { "fcmovge",              FP(0x17,0x02D), BASE, ARG_FP },
01034   { "fcmovle",              FP(0x17,0x02E), BASE, ARG_FP },
01035   { "fcmovgt",              FP(0x17,0x02F), BASE, ARG_FP },
01036   { "cvtql",         FP(0x17,0x030), BASE, ARG_FPZ1 },
01037   { "cvtql/v",              FP(0x17,0x130), BASE, ARG_FPZ1 },
01038   { "cvtql/sv",             FP(0x17,0x530), BASE, ARG_FPZ1 },
01039 
01040   { "trapb",         MFC(0x18,0x0000), BASE, ARG_NONE },
01041   { "draint",        MFC(0x18,0x0000), BASE, ARG_NONE },       /* alias */
01042   { "excb",          MFC(0x18,0x0400), BASE, ARG_NONE },
01043   { "mb",            MFC(0x18,0x4000), BASE, ARG_NONE },
01044   { "wmb",           MFC(0x18,0x4400), BASE, ARG_NONE },
01045   { "fetch",         MFC(0x18,0x8000), BASE, { ZA, PRB } },
01046   { "fetch_m",              MFC(0x18,0xA000), BASE, { ZA, PRB } },
01047   { "rpcc",          MFC(0x18,0xC000), BASE, { RA, ZB } },
01048   { "rpcc",          MFC(0x18,0xC000), BASE, { RA, RB } },     /* ev6 una */
01049   { "rc",            MFC(0x18,0xE000), BASE, { RA } },
01050   { "ecb",           MFC(0x18,0xE800), BASE, { ZA, PRB } },    /* ev56 una */
01051   { "rs",            MFC(0x18,0xF000), BASE, { RA } },
01052   { "wh64",          MFC(0x18,0xF800), BASE, { ZA, PRB } },    /* ev56 una */
01053   { "wh64en",        MFC(0x18,0xFC00), BASE, { ZA, PRB } },    /* ev7 una */
01054 
01055   { "hw_mfpr",              OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
01056   { "hw_mfpr",              OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
01057   { "hw_mfpr",              OP(0x19), OP_MASK, EV6, { RA, ZB, EV6HWINDEX } },
01058   { "hw_mfpr/i",     OPR(0x19,0x01), EV4, ARG_EV4HWMPR },
01059   { "hw_mfpr/a",     OPR(0x19,0x02), EV4, ARG_EV4HWMPR },
01060   { "hw_mfpr/ai",    OPR(0x19,0x03), EV4, ARG_EV4HWMPR },
01061   { "hw_mfpr/p",     OPR(0x19,0x04), EV4, ARG_EV4HWMPR },
01062   { "hw_mfpr/pi",    OPR(0x19,0x05), EV4, ARG_EV4HWMPR },
01063   { "hw_mfpr/pa",    OPR(0x19,0x06), EV4, ARG_EV4HWMPR },
01064   { "hw_mfpr/pai",   OPR(0x19,0x07), EV4, ARG_EV4HWMPR },
01065   { "pal19",         PCD(0x19), BASE, ARG_PCD },
01066 
01067   { "jmp",           MBR_(0x1A,0), MBR_MASK | 0x3FFF,   /* pseudo */
01068                      BASE, { ZA, CPRB } },
01069   { "jmp",           MBR(0x1A,0), BASE, { RA, CPRB, JMPHINT } },
01070   { "jsr",           MBR(0x1A,1), BASE, { RA, CPRB, JMPHINT } },
01071   { "ret",           MBR_(0x1A,2) | (31 << 21) | (26 << 16) | 1,/* pseudo */
01072                      0xFFFFFFFF, BASE, { 0 } },
01073   { "ret",           MBR(0x1A,2), BASE, { RA, CPRB, RETHINT } },
01074   { "jcr",           MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } }, /* alias */
01075   { "jsr_coroutine", MBR(0x1A,3), BASE, { RA, CPRB, RETHINT } },
01076 
01077   { "hw_ldl",        EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
01078   { "hw_ldl",        EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
01079   { "hw_ldl",        EV6HWMEM(0x1B,0x8), EV6, ARG_EV6HWMEM },
01080   { "hw_ldl/a",             EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
01081   { "hw_ldl/a",             EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
01082   { "hw_ldl/a",             EV6HWMEM(0x1B,0xC), EV6, ARG_EV6HWMEM },
01083   { "hw_ldl/al",     EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
01084   { "hw_ldl/ar",     EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
01085   { "hw_ldl/av",     EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
01086   { "hw_ldl/avl",    EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
01087   { "hw_ldl/aw",     EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
01088   { "hw_ldl/awl",    EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
01089   { "hw_ldl/awv",    EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
01090   { "hw_ldl/awvl",   EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
01091   { "hw_ldl/l",             EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
01092   { "hw_ldl/p",             EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
01093   { "hw_ldl/p",             EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
01094   { "hw_ldl/p",             EV6HWMEM(0x1B,0x0), EV6, ARG_EV6HWMEM },
01095   { "hw_ldl/pa",     EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
01096   { "hw_ldl/pa",     EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
01097   { "hw_ldl/pal",    EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
01098   { "hw_ldl/par",    EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
01099   { "hw_ldl/pav",    EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
01100   { "hw_ldl/pavl",   EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
01101   { "hw_ldl/paw",    EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
01102   { "hw_ldl/pawl",   EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
01103   { "hw_ldl/pawv",   EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
01104   { "hw_ldl/pawvl",  EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
01105   { "hw_ldl/pl",     EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
01106   { "hw_ldl/pr",     EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
01107   { "hw_ldl/pv",     EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
01108   { "hw_ldl/pvl",    EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
01109   { "hw_ldl/pw",     EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
01110   { "hw_ldl/pwl",    EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
01111   { "hw_ldl/pwv",    EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
01112   { "hw_ldl/pwvl",   EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
01113   { "hw_ldl/r",             EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
01114   { "hw_ldl/v",             EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
01115   { "hw_ldl/v",             EV6HWMEM(0x1B,0x4), EV6, ARG_EV6HWMEM },
01116   { "hw_ldl/vl",     EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
01117   { "hw_ldl/w",             EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
01118   { "hw_ldl/w",             EV6HWMEM(0x1B,0xA), EV6, ARG_EV6HWMEM },
01119   { "hw_ldl/wa",     EV6HWMEM(0x1B,0xE), EV6, ARG_EV6HWMEM },
01120   { "hw_ldl/wl",     EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
01121   { "hw_ldl/wv",     EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
01122   { "hw_ldl/wvl",    EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
01123   { "hw_ldl_l",             EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
01124   { "hw_ldl_l/a",    EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
01125   { "hw_ldl_l/av",   EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
01126   { "hw_ldl_l/aw",   EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
01127   { "hw_ldl_l/awv",  EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
01128   { "hw_ldl_l/p",    EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
01129   { "hw_ldl_l/p",    EV6HWMEM(0x1B,0x2), EV6, ARG_EV6HWMEM },
01130   { "hw_ldl_l/pa",   EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
01131   { "hw_ldl_l/pav",  EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
01132   { "hw_ldl_l/paw",  EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
01133   { "hw_ldl_l/pawv", EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
01134   { "hw_ldl_l/pv",   EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
01135   { "hw_ldl_l/pw",   EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
01136   { "hw_ldl_l/pwv",  EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
01137   { "hw_ldl_l/v",    EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
01138   { "hw_ldl_l/w",    EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
01139   { "hw_ldl_l/wv",   EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
01140   { "hw_ldq",        EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
01141   { "hw_ldq",        EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
01142   { "hw_ldq",        EV6HWMEM(0x1B,0x9), EV6, ARG_EV6HWMEM },
01143   { "hw_ldq/a",             EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
01144   { "hw_ldq/a",             EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
01145   { "hw_ldq/a",             EV6HWMEM(0x1B,0xD), EV6, ARG_EV6HWMEM },
01146   { "hw_ldq/al",     EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
01147   { "hw_ldq/ar",     EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
01148   { "hw_ldq/av",     EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
01149   { "hw_ldq/avl",    EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
01150   { "hw_ldq/aw",     EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
01151   { "hw_ldq/awl",    EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
01152   { "hw_ldq/awv",    EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
01153   { "hw_ldq/awvl",   EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
01154   { "hw_ldq/l",             EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
01155   { "hw_ldq/p",             EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
01156   { "hw_ldq/p",             EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
01157   { "hw_ldq/p",             EV6HWMEM(0x1B,0x1), EV6, ARG_EV6HWMEM },
01158   { "hw_ldq/pa",     EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
01159   { "hw_ldq/pa",     EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
01160   { "hw_ldq/pal",    EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
01161   { "hw_ldq/par",    EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
01162   { "hw_ldq/pav",    EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
01163   { "hw_ldq/pavl",   EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
01164   { "hw_ldq/paw",    EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
01165   { "hw_ldq/pawl",   EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
01166   { "hw_ldq/pawv",   EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
01167   { "hw_ldq/pawvl",  EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
01168   { "hw_ldq/pl",     EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
01169   { "hw_ldq/pr",     EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
01170   { "hw_ldq/pv",     EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
01171   { "hw_ldq/pvl",    EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
01172   { "hw_ldq/pw",     EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
01173   { "hw_ldq/pwl",    EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
01174   { "hw_ldq/pwv",    EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
01175   { "hw_ldq/pwvl",   EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
01176   { "hw_ldq/r",             EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
01177   { "hw_ldq/v",             EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
01178   { "hw_ldq/v",             EV6HWMEM(0x1B,0x5), EV6, ARG_EV6HWMEM },
01179   { "hw_ldq/vl",     EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
01180   { "hw_ldq/w",             EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
01181   { "hw_ldq/w",             EV6HWMEM(0x1B,0xB), EV6, ARG_EV6HWMEM },
01182   { "hw_ldq/wa",     EV6HWMEM(0x1B,0xF), EV6, ARG_EV6HWMEM },
01183   { "hw_ldq/wl",     EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
01184   { "hw_ldq/wv",     EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
01185   { "hw_ldq/wvl",    EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
01186   { "hw_ldq_l",             EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
01187   { "hw_ldq_l/a",    EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
01188   { "hw_ldq_l/av",   EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
01189   { "hw_ldq_l/aw",   EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
01190   { "hw_ldq_l/awv",  EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
01191   { "hw_ldq_l/p",    EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
01192   { "hw_ldq_l/p",    EV6HWMEM(0x1B,0x3), EV6, ARG_EV6HWMEM },
01193   { "hw_ldq_l/pa",   EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
01194   { "hw_ldq_l/pav",  EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
01195   { "hw_ldq_l/paw",  EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
01196   { "hw_ldq_l/pawv", EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
01197   { "hw_ldq_l/pv",   EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
01198   { "hw_ldq_l/pw",   EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
01199   { "hw_ldq_l/pwv",  EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
01200   { "hw_ldq_l/v",    EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
01201   { "hw_ldq_l/w",    EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
01202   { "hw_ldq_l/wv",   EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
01203   { "hw_ld",         EV4HWMEM(0x1B,0x0), EV4, ARG_EV4HWMEM },
01204   { "hw_ld",         EV5HWMEM(0x1B,0x00), EV5, ARG_EV5HWMEM },
01205   { "hw_ld/a",              EV4HWMEM(0x1B,0x4), EV4, ARG_EV4HWMEM },
01206   { "hw_ld/a",              EV5HWMEM(0x1B,0x10), EV5, ARG_EV5HWMEM },
01207   { "hw_ld/al",             EV5HWMEM(0x1B,0x11), EV5, ARG_EV5HWMEM },
01208   { "hw_ld/aq",             EV4HWMEM(0x1B,0x5), EV4, ARG_EV4HWMEM },
01209   { "hw_ld/aq",             EV5HWMEM(0x1B,0x14), EV5, ARG_EV5HWMEM },
01210   { "hw_ld/aql",     EV5HWMEM(0x1B,0x15), EV5, ARG_EV5HWMEM },
01211   { "hw_ld/aqv",     EV5HWMEM(0x1B,0x16), EV5, ARG_EV5HWMEM },
01212   { "hw_ld/aqvl",    EV5HWMEM(0x1B,0x17), EV5, ARG_EV5HWMEM },
01213   { "hw_ld/ar",             EV4HWMEM(0x1B,0x6), EV4, ARG_EV4HWMEM },
01214   { "hw_ld/arq",     EV4HWMEM(0x1B,0x7), EV4, ARG_EV4HWMEM },
01215   { "hw_ld/av",             EV5HWMEM(0x1B,0x12), EV5, ARG_EV5HWMEM },
01216   { "hw_ld/avl",     EV5HWMEM(0x1B,0x13), EV5, ARG_EV5HWMEM },
01217   { "hw_ld/aw",             EV5HWMEM(0x1B,0x18), EV5, ARG_EV5HWMEM },
01218   { "hw_ld/awl",     EV5HWMEM(0x1B,0x19), EV5, ARG_EV5HWMEM },
01219   { "hw_ld/awq",     EV5HWMEM(0x1B,0x1c), EV5, ARG_EV5HWMEM },
01220   { "hw_ld/awql",    EV5HWMEM(0x1B,0x1d), EV5, ARG_EV5HWMEM },
01221   { "hw_ld/awqv",    EV5HWMEM(0x1B,0x1e), EV5, ARG_EV5HWMEM },
01222   { "hw_ld/awqvl",   EV5HWMEM(0x1B,0x1f), EV5, ARG_EV5HWMEM },
01223   { "hw_ld/awv",     EV5HWMEM(0x1B,0x1a), EV5, ARG_EV5HWMEM },
01224   { "hw_ld/awvl",    EV5HWMEM(0x1B,0x1b), EV5, ARG_EV5HWMEM },
01225   { "hw_ld/l",              EV5HWMEM(0x1B,0x01), EV5, ARG_EV5HWMEM },
01226   { "hw_ld/p",              EV4HWMEM(0x1B,0x8), EV4, ARG_EV4HWMEM },
01227   { "hw_ld/p",              EV5HWMEM(0x1B,0x20), EV5, ARG_EV5HWMEM },
01228   { "hw_ld/pa",             EV4HWMEM(0x1B,0xC), EV4, ARG_EV4HWMEM },
01229   { "hw_ld/pa",             EV5HWMEM(0x1B,0x30), EV5, ARG_EV5HWMEM },
01230   { "hw_ld/pal",     EV5HWMEM(0x1B,0x31), EV5, ARG_EV5HWMEM },
01231   { "hw_ld/paq",     EV4HWMEM(0x1B,0xD), EV4, ARG_EV4HWMEM },
01232   { "hw_ld/paq",     EV5HWMEM(0x1B,0x34), EV5, ARG_EV5HWMEM },
01233   { "hw_ld/paql",    EV5HWMEM(0x1B,0x35), EV5, ARG_EV5HWMEM },
01234   { "hw_ld/paqv",    EV5HWMEM(0x1B,0x36), EV5, ARG_EV5HWMEM },
01235   { "hw_ld/paqvl",   EV5HWMEM(0x1B,0x37), EV5, ARG_EV5HWMEM },
01236   { "hw_ld/par",     EV4HWMEM(0x1B,0xE), EV4, ARG_EV4HWMEM },
01237   { "hw_ld/parq",    EV4HWMEM(0x1B,0xF), EV4, ARG_EV4HWMEM },
01238   { "hw_ld/pav",     EV5HWMEM(0x1B,0x32), EV5, ARG_EV5HWMEM },
01239   { "hw_ld/pavl",    EV5HWMEM(0x1B,0x33), EV5, ARG_EV5HWMEM },
01240   { "hw_ld/paw",     EV5HWMEM(0x1B,0x38), EV5, ARG_EV5HWMEM },
01241   { "hw_ld/pawl",    EV5HWMEM(0x1B,0x39), EV5, ARG_EV5HWMEM },
01242   { "hw_ld/pawq",    EV5HWMEM(0x1B,0x3c), EV5, ARG_EV5HWMEM },
01243   { "hw_ld/pawql",   EV5HWMEM(0x1B,0x3d), EV5, ARG_EV5HWMEM },
01244   { "hw_ld/pawqv",   EV5HWMEM(0x1B,0x3e), EV5, ARG_EV5HWMEM },
01245   { "hw_ld/pawqvl",  EV5HWMEM(0x1B,0x3f), EV5, ARG_EV5HWMEM },
01246   { "hw_ld/pawv",    EV5HWMEM(0x1B,0x3a), EV5, ARG_EV5HWMEM },
01247   { "hw_ld/pawvl",   EV5HWMEM(0x1B,0x3b), EV5, ARG_EV5HWMEM },
01248   { "hw_ld/pl",             EV5HWMEM(0x1B,0x21), EV5, ARG_EV5HWMEM },
01249   { "hw_ld/pq",             EV4HWMEM(0x1B,0x9), EV4, ARG_EV4HWMEM },
01250   { "hw_ld/pq",             EV5HWMEM(0x1B,0x24), EV5, ARG_EV5HWMEM },
01251   { "hw_ld/pql",     EV5HWMEM(0x1B,0x25), EV5, ARG_EV5HWMEM },
01252   { "hw_ld/pqv",     EV5HWMEM(0x1B,0x26), EV5, ARG_EV5HWMEM },
01253   { "hw_ld/pqvl",    EV5HWMEM(0x1B,0x27), EV5, ARG_EV5HWMEM },
01254   { "hw_ld/pr",             EV4HWMEM(0x1B,0xA), EV4, ARG_EV4HWMEM },
01255   { "hw_ld/prq",     EV4HWMEM(0x1B,0xB), EV4, ARG_EV4HWMEM },
01256   { "hw_ld/pv",             EV5HWMEM(0x1B,0x22), EV5, ARG_EV5HWMEM },
01257   { "hw_ld/pvl",     EV5HWMEM(0x1B,0x23), EV5, ARG_EV5HWMEM },
01258   { "hw_ld/pw",             EV5HWMEM(0x1B,0x28), EV5, ARG_EV5HWMEM },
01259   { "hw_ld/pwl",     EV5HWMEM(0x1B,0x29), EV5, ARG_EV5HWMEM },
01260   { "hw_ld/pwq",     EV5HWMEM(0x1B,0x2c), EV5, ARG_EV5HWMEM },
01261   { "hw_ld/pwql",    EV5HWMEM(0x1B,0x2d), EV5, ARG_EV5HWMEM },
01262   { "hw_ld/pwqv",    EV5HWMEM(0x1B,0x2e), EV5, ARG_EV5HWMEM },
01263   { "hw_ld/pwqvl",   EV5HWMEM(0x1B,0x2f), EV5, ARG_EV5HWMEM },
01264   { "hw_ld/pwv",     EV5HWMEM(0x1B,0x2a), EV5, ARG_EV5HWMEM },
01265   { "hw_ld/pwvl",    EV5HWMEM(0x1B,0x2b), EV5, ARG_EV5HWMEM },
01266   { "hw_ld/q",              EV4HWMEM(0x1B,0x1), EV4, ARG_EV4HWMEM },
01267   { "hw_ld/q",              EV5HWMEM(0x1B,0x04), EV5, ARG_EV5HWMEM },
01268   { "hw_ld/ql",             EV5HWMEM(0x1B,0x05), EV5, ARG_EV5HWMEM },
01269   { "hw_ld/qv",             EV5HWMEM(0x1B,0x06), EV5, ARG_EV5HWMEM },
01270   { "hw_ld/qvl",     EV5HWMEM(0x1B,0x07), EV5, ARG_EV5HWMEM },
01271   { "hw_ld/r",              EV4HWMEM(0x1B,0x2), EV4, ARG_EV4HWMEM },
01272   { "hw_ld/rq",             EV4HWMEM(0x1B,0x3), EV4, ARG_EV4HWMEM },
01273   { "hw_ld/v",              EV5HWMEM(0x1B,0x02), EV5, ARG_EV5HWMEM },
01274   { "hw_ld/vl",             EV5HWMEM(0x1B,0x03), EV5, ARG_EV5HWMEM },
01275   { "hw_ld/w",              EV5HWMEM(0x1B,0x08), EV5, ARG_EV5HWMEM },
01276   { "hw_ld/wl",             EV5HWMEM(0x1B,0x09), EV5, ARG_EV5HWMEM },
01277   { "hw_ld/wq",             EV5HWMEM(0x1B,0x0c), EV5, ARG_EV5HWMEM },
01278   { "hw_ld/wql",     EV5HWMEM(0x1B,0x0d), EV5, ARG_EV5HWMEM },
01279   { "hw_ld/wqv",     EV5HWMEM(0x1B,0x0e), EV5, ARG_EV5HWMEM },
01280   { "hw_ld/wqvl",    EV5HWMEM(0x1B,0x0f), EV5, ARG_EV5HWMEM },
01281   { "hw_ld/wv",             EV5HWMEM(0x1B,0x0a), EV5, ARG_EV5HWMEM },
01282   { "hw_ld/wvl",     EV5HWMEM(0x1B,0x0b), EV5, ARG_EV5HWMEM },
01283   { "pal1b",         PCD(0x1B), BASE, ARG_PCD },
01284 
01285   { "sextb",         OPR(0x1C, 0x00), BWX, ARG_OPRZ1 },
01286   { "sextw",         OPR(0x1C, 0x01), BWX, ARG_OPRZ1 },
01287   { "ctpop",         OPR(0x1C, 0x30), CIX, ARG_OPRZ1 },
01288   { "perr",          OPR(0x1C, 0x31), MAX, ARG_OPR },
01289   { "ctlz",          OPR(0x1C, 0x32), CIX, ARG_OPRZ1 },
01290   { "cttz",          OPR(0x1C, 0x33), CIX, ARG_OPRZ1 },
01291   { "unpkbw",        OPR(0x1C, 0x34), MAX, ARG_OPRZ1 },
01292   { "unpkbl",        OPR(0x1C, 0x35), MAX, ARG_OPRZ1 },
01293   { "pkwb",          OPR(0x1C, 0x36), MAX, ARG_OPRZ1 },
01294   { "pklb",          OPR(0x1C, 0x37), MAX, ARG_OPRZ1 },
01295   { "minsb8",               OPR(0x1C, 0x38), MAX, ARG_OPR },
01296   { "minsb8",               OPRL(0x1C, 0x38), MAX, ARG_OPRL },
01297   { "minsw4",               OPR(0x1C, 0x39), MAX, ARG_OPR },
01298   { "minsw4",               OPRL(0x1C, 0x39), MAX, ARG_OPRL },
01299   { "minub8",               OPR(0x1C, 0x3A), MAX, ARG_OPR },
01300   { "minub8",               OPRL(0x1C, 0x3A), MAX, ARG_OPRL },
01301   { "minuw4",               OPR(0x1C, 0x3B), MAX, ARG_OPR },
01302   { "minuw4",               OPRL(0x1C, 0x3B), MAX, ARG_OPRL },
01303   { "maxub8",        OPR(0x1C, 0x3C), MAX, ARG_OPR },
01304   { "maxub8",        OPRL(0x1C, 0x3C), MAX, ARG_OPRL },
01305   { "maxuw4",        OPR(0x1C, 0x3D), MAX, ARG_OPR },
01306   { "maxuw4",        OPRL(0x1C, 0x3D), MAX, ARG_OPRL },
01307   { "maxsb8",        OPR(0x1C, 0x3E), MAX, ARG_OPR },
01308   { "maxsb8",        OPRL(0x1C, 0x3E), MAX, ARG_OPRL },
01309   { "maxsw4",        OPR(0x1C, 0x3F), MAX, ARG_OPR },
01310   { "maxsw4",        OPRL(0x1C, 0x3F), MAX, ARG_OPRL },
01311   { "ftoit",         FP(0x1C, 0x70), CIX, { FA, ZB, RC } },
01312   { "ftois",         FP(0x1C, 0x78), CIX, { FA, ZB, RC } },
01313 
01314   { "hw_mtpr",              OPR(0x1D,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } },
01315   { "hw_mtpr",              OP(0x1D), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } },
01316   { "hw_mtpr",              OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
01317   { "hw_mtpr/i",     OPR(0x1D,0x01), EV4, ARG_EV4HWMPR },
01318   { "hw_mtpr/a",     OPR(0x1D,0x02), EV4, ARG_EV4HWMPR },
01319   { "hw_mtpr/ai",    OPR(0x1D,0x03), EV4, ARG_EV4HWMPR },
01320   { "hw_mtpr/p",     OPR(0x1D,0x04), EV4, ARG_EV4HWMPR },
01321   { "hw_mtpr/pi",    OPR(0x1D,0x05), EV4, ARG_EV4HWMPR },
01322   { "hw_mtpr/pa",    OPR(0x1D,0x06), EV4, ARG_EV4HWMPR },
01323   { "hw_mtpr/pai",   OPR(0x1D,0x07), EV4, ARG_EV4HWMPR },
01324   { "pal1d",         PCD(0x1D), BASE, ARG_PCD },
01325 
01326   { "hw_rei",        SPCD(0x1E,0x3FF8000), EV4|EV5, ARG_NONE },
01327   { "hw_rei_stall",  SPCD(0x1E,0x3FFC000), EV5, ARG_NONE },
01328   { "hw_jmp",               EV6HWMBR(0x1E,0x0), EV6, { ZA, PRB, EV6HWJMPHINT } },
01329   { "hw_jsr",               EV6HWMBR(0x1E,0x2), EV6, { ZA, PRB, EV6HWJMPHINT } },
01330   { "hw_ret",               EV6HWMBR(0x1E,0x4), EV6, { ZA, PRB } },
01331   { "hw_jcr",               EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } },
01332   { "hw_coroutine",  EV6HWMBR(0x1E,0x6), EV6, { ZA, PRB } }, /* alias */
01333   { "hw_jmp/stall",  EV6HWMBR(0x1E,0x1), EV6, { ZA, PRB, EV6HWJMPHINT } },
01334   { "hw_jsr/stall",  EV6HWMBR(0x1E,0x3), EV6, { ZA, PRB, EV6HWJMPHINT } },
01335   { "hw_ret/stall",  EV6HWMBR(0x1E,0x5), EV6, { ZA, PRB } },
01336   { "hw_jcr/stall",  EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } },
01337   { "hw_coroutine/stall", EV6HWMBR(0x1E,0x7), EV6, { ZA, PRB } }, /* alias */
01338   { "pal1e",         PCD(0x1E), BASE, ARG_PCD },
01339 
01340   { "hw_stl",        EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
01341   { "hw_stl",        EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
01342   { "hw_stl",        EV6HWMEM(0x1F,0x4), EV6, ARG_EV6HWMEM }, /* ??? 8 */
01343   { "hw_stl/a",             EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
01344   { "hw_stl/a",             EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
01345   { "hw_stl/a",             EV6HWMEM(0x1F,0xC), EV6, ARG_EV6HWMEM },
01346   { "hw_stl/ac",     EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
01347   { "hw_stl/ar",     EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
01348   { "hw_stl/av",     EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
01349   { "hw_stl/avc",    EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
01350   { "hw_stl/c",             EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
01351   { "hw_stl/p",             EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
01352   { "hw_stl/p",             EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
01353   { "hw_stl/p",             EV6HWMEM(0x1F,0x0), EV6, ARG_EV6HWMEM },
01354   { "hw_stl/pa",     EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
01355   { "hw_stl/pa",     EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
01356   { "hw_stl/pac",    EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
01357   { "hw_stl/pav",    EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
01358   { "hw_stl/pavc",   EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
01359   { "hw_stl/pc",     EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
01360   { "hw_stl/pr",     EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
01361   { "hw_stl/pv",     EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
01362   { "hw_stl/pvc",    EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
01363   { "hw_stl/r",             EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
01364   { "hw_stl/v",             EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
01365   { "hw_stl/vc",     EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
01366   { "hw_stl_c",             EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
01367   { "hw_stl_c/a",    EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
01368   { "hw_stl_c/av",   EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
01369   { "hw_stl_c/p",    EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
01370   { "hw_stl_c/p",    EV6HWMEM(0x1F,0x2), EV6, ARG_EV6HWMEM },
01371   { "hw_stl_c/pa",   EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
01372   { "hw_stl_c/pav",  EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
01373   { "hw_stl_c/pv",   EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
01374   { "hw_stl_c/v",    EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
01375   { "hw_stq",        EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
01376   { "hw_stq",        EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
01377   { "hw_stq",        EV6HWMEM(0x1F,0x5), EV6, ARG_EV6HWMEM }, /* ??? 9 */
01378   { "hw_stq/a",             EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
01379   { "hw_stq/a",             EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
01380   { "hw_stq/a",             EV6HWMEM(0x1F,0xD), EV6, ARG_EV6HWMEM },
01381   { "hw_stq/ac",     EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
01382   { "hw_stq/ar",     EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
01383   { "hw_stq/av",     EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
01384   { "hw_stq/avc",    EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
01385   { "hw_stq/c",             EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
01386   { "hw_stq/p",             EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
01387   { "hw_stq/p",             EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
01388   { "hw_stq/p",             EV6HWMEM(0x1F,0x1), EV6, ARG_EV6HWMEM },
01389   { "hw_stq/pa",     EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
01390   { "hw_stq/pa",     EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
01391   { "hw_stq/pac",    EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
01392   { "hw_stq/par",    EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
01393   { "hw_stq/par",    EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
01394   { "hw_stq/pav",    EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
01395   { "hw_stq/pavc",   EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
01396   { "hw_stq/pc",     EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
01397   { "hw_stq/pr",     EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
01398   { "hw_stq/pv",     EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
01399   { "hw_stq/pvc",    EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
01400   { "hw_stq/r",             EV4HWMEM(0x1F,0x3), EV4, ARG_EV4HWMEM },
01401   { "hw_stq/v",             EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
01402   { "hw_stq/vc",     EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
01403   { "hw_stq_c",             EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
01404   { "hw_stq_c/a",    EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
01405   { "hw_stq_c/av",   EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
01406   { "hw_stq_c/p",    EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
01407   { "hw_stq_c/p",    EV6HWMEM(0x1F,0x3), EV6, ARG_EV6HWMEM },
01408   { "hw_stq_c/pa",   EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
01409   { "hw_stq_c/pav",  EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
01410   { "hw_stq_c/pv",   EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
01411   { "hw_stq_c/v",    EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
01412   { "hw_st",         EV4HWMEM(0x1F,0x0), EV4, ARG_EV4HWMEM },
01413   { "hw_st",         EV5HWMEM(0x1F,0x00), EV5, ARG_EV5HWMEM },
01414   { "hw_st/a",              EV4HWMEM(0x1F,0x4), EV4, ARG_EV4HWMEM },
01415   { "hw_st/a",              EV5HWMEM(0x1F,0x10), EV5, ARG_EV5HWMEM },
01416   { "hw_st/ac",             EV5HWMEM(0x1F,0x11), EV5, ARG_EV5HWMEM },
01417   { "hw_st/aq",             EV4HWMEM(0x1F,0x5), EV4, ARG_EV4HWMEM },
01418   { "hw_st/aq",             EV5HWMEM(0x1F,0x14), EV5, ARG_EV5HWMEM },
01419   { "hw_st/aqc",     EV5HWMEM(0x1F,0x15), EV5, ARG_EV5HWMEM },
01420   { "hw_st/aqv",     EV5HWMEM(0x1F,0x16), EV5, ARG_EV5HWMEM },
01421   { "hw_st/aqvc",    EV5HWMEM(0x1F,0x17), EV5, ARG_EV5HWMEM },
01422   { "hw_st/ar",             EV4HWMEM(0x1F,0x6), EV4, ARG_EV4HWMEM },
01423   { "hw_st/arq",     EV4HWMEM(0x1F,0x7), EV4, ARG_EV4HWMEM },
01424   { "hw_st/av",             EV5HWMEM(0x1F,0x12), EV5, ARG_EV5HWMEM },
01425   { "hw_st/avc",     EV5HWMEM(0x1F,0x13), EV5, ARG_EV5HWMEM },
01426   { "hw_st/c",              EV5HWMEM(0x1F,0x01), EV5, ARG_EV5HWMEM },
01427   { "hw_st/p",              EV4HWMEM(0x1F,0x8), EV4, ARG_EV4HWMEM },
01428   { "hw_st/p",              EV5HWMEM(0x1F,0x20), EV5, ARG_EV5HWMEM },
01429   { "hw_st/pa",             EV4HWMEM(0x1F,0xC), EV4, ARG_EV4HWMEM },
01430   { "hw_st/pa",             EV5HWMEM(0x1F,0x30), EV5, ARG_EV5HWMEM },
01431   { "hw_st/pac",     EV5HWMEM(0x1F,0x31), EV5, ARG_EV5HWMEM },
01432   { "hw_st/paq",     EV4HWMEM(0x1F,0xD), EV4, ARG_EV4HWMEM },
01433   { "hw_st/paq",     EV5HWMEM(0x1F,0x34), EV5, ARG_EV5HWMEM },
01434   { "hw_st/paqc",    EV5HWMEM(0x1F,0x35), EV5, ARG_EV5HWMEM },
01435   { "hw_st/paqv",    EV5HWMEM(0x1F,0x36), EV5, ARG_EV5HWMEM },
01436   { "hw_st/paqvc",   EV5HWMEM(0x1F,0x37), EV5, ARG_EV5HWMEM },
01437   { "hw_st/par",     EV4HWMEM(0x1F,0xE), EV4, ARG_EV4HWMEM },
01438   { "hw_st/parq",    EV4HWMEM(0x1F,0xF), EV4, ARG_EV4HWMEM },
01439   { "hw_st/pav",     EV5HWMEM(0x1F,0x32), EV5, ARG_EV5HWMEM },
01440   { "hw_st/pavc",    EV5HWMEM(0x1F,0x33), EV5, ARG_EV5HWMEM },
01441   { "hw_st/pc",             EV5HWMEM(0x1F,0x21), EV5, ARG_EV5HWMEM },
01442   { "hw_st/pq",             EV4HWMEM(0x1F,0x9), EV4, ARG_EV4HWMEM },
01443   { "hw_st/pq",             EV5HWMEM(0x1F,0x24), EV5, ARG_EV5HWMEM },
01444   { "hw_st/pqc",     EV5HWMEM(0x1F,0x25), EV5, ARG_EV5HWMEM },
01445   { "hw_st/pqv",     EV5HWMEM(0x1F,0x26), EV5, ARG_EV5HWMEM },
01446   { "hw_st/pqvc",    EV5HWMEM(0x1F,0x27), EV5, ARG_EV5HWMEM },
01447   { "hw_st/pr",             EV4HWMEM(0x1F,0xA), EV4, ARG_EV4HWMEM },
01448   { "hw_st/prq",     EV4HWMEM(0x1F,0xB), EV4, ARG_EV4HWMEM },
01449   { "hw_st/pv",             EV5HWMEM(0x1F,0x22), EV5, ARG_EV5HWMEM },
01450   { "hw_st/pvc",     EV5HWMEM(0x1F,0x23), EV5, ARG_EV5HWMEM },
01451   { "hw_st/q",              EV4HWMEM(0x1F,0x1), EV4, ARG_EV4HWMEM },
01452   { "hw_st/q",              EV5HWMEM(0x1F,0x04), EV5, ARG_EV5HWMEM },
01453   { "hw_st/qc",             EV5HWMEM(0x1F,0x05), EV5, ARG_EV5HWMEM },
01454   { "hw_st/qv",             EV5HWMEM(0x1F,0x06), EV5, ARG_EV5HWMEM },
01455   { "hw_st/qvc",     EV5HWMEM(0x1F,0x07), EV5, ARG_EV5HWMEM },
01456   { "hw_st/r",              EV4HWMEM(0x1F,0x2), EV4, ARG_EV4HWMEM },
01457   { "hw_st/v",              EV5HWMEM(0x1F,0x02), EV5, ARG_EV5HWMEM },
01458   { "hw_st/vc",             EV5HWMEM(0x1F,0x03), EV5, ARG_EV5HWMEM },
01459   { "pal1f",         PCD(0x1F), BASE, ARG_PCD },
01460 
01461   { "ldf",           MEM(0x20), BASE, ARG_FMEM },
01462   { "ldg",           MEM(0x21), BASE, ARG_FMEM },
01463   { "lds",           MEM(0x22), BASE, ARG_FMEM },
01464   { "ldt",           MEM(0x23), BASE, ARG_FMEM },
01465   { "stf",           MEM(0x24), BASE, ARG_FMEM },
01466   { "stg",           MEM(0x25), BASE, ARG_FMEM },
01467   { "sts",           MEM(0x26), BASE, ARG_FMEM },
01468   { "stt",           MEM(0x27), BASE, ARG_FMEM },
01469 
01470   { "ldl",           MEM(0x28), BASE, ARG_MEM },
01471   { "ldq",           MEM(0x29), BASE, ARG_MEM },
01472   { "ldl_l",         MEM(0x2A), BASE, ARG_MEM },
01473   { "ldq_l",         MEM(0x2B), BASE, ARG_MEM },
01474   { "stl",           MEM(0x2C), BASE, ARG_MEM },
01475   { "stq",           MEM(0x2D), BASE, ARG_MEM },
01476   { "stl_c",         MEM(0x2E), BASE, ARG_MEM },
01477   { "stq_c",         MEM(0x2F), BASE, ARG_MEM },
01478 
01479   { "br",            BRA(0x30), BASE, { ZA, BDISP } },  /* pseudo */
01480   { "br",            BRA(0x30), BASE, ARG_BRA },
01481   { "fbeq",          BRA(0x31), BASE, ARG_FBRA },
01482   { "fblt",          BRA(0x32), BASE, ARG_FBRA },
01483   { "fble",          BRA(0x33), BASE, ARG_FBRA },
01484   { "bsr",           BRA(0x34), BASE, ARG_BRA },
01485   { "fbne",          BRA(0x35), BASE, ARG_FBRA },
01486   { "fbge",          BRA(0x36), BASE, ARG_FBRA },
01487   { "fbgt",          BRA(0x37), BASE, ARG_FBRA },
01488   { "blbc",          BRA(0x38), BASE, ARG_BRA },
01489   { "beq",           BRA(0x39), BASE, ARG_BRA },
01490   { "blt",           BRA(0x3A), BASE, ARG_BRA },
01491   { "ble",           BRA(0x3B), BASE, ARG_BRA },
01492   { "blbs",          BRA(0x3C), BASE, ARG_BRA },
01493   { "bne",           BRA(0x3D), BASE, ARG_BRA },
01494   { "bge",           BRA(0x3E), BASE, ARG_BRA },
01495   { "bgt",           BRA(0x3F), BASE, ARG_BRA },
01496 };
01497 
01498 const unsigned alpha_num_opcodes = sizeof(alpha_opcodes)/sizeof(*alpha_opcodes);